A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology

Microelectronics Journal 58 (2016) 44–59

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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

A novel design of low power and high read stability Ternary SRAM (TSRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology

crossmark

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Ebrahim Abiri, Abdolreza Darabi

Electrical and Electronic Department of Shiraz University of Technology, Iran

A R T I C L E I N F O

A BS T RAC T

Keywords: Gate Diffusion Input (GDI) Technique Carbon Nano Tube (CNT) Field Effect Transistor (CNTFET) Multiple-Valued Logic (MVL) Ternary logic Process and temperature variations Static Noise Margin (SNM) Power-Delay Product (PDP)

The conventional complementary metal-oxide semiconductor (CMOS) design techniques confront to the limitation of designing the integrated circuits (ICs), especially memories, with multiple-valued logic (MVL) in nanotechnology. Gate diffusion input (GDI) technique, provides the possibility to design low power logic gates with small chip area and interconnection capacitors while the number of transistors is diminished. In this paper first ternary GDI (t-GDI) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is designed. Then, by using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is presented for nano process, which has smaller standby power dissipation and standard deviation for delay of writing and reading cycles, better read static noise margin (RSNM) and lower signal control complexity. The design of specific structure of 4-words×4-bits, ternary SRAM (4×4 T-SRAM) shows that the number of connections, chip area is decreased and power-delay product (PDP) criterion is improved for writing and reading cycles with significant small standard deviation in compare with the other similar T-SRAMs designed. The effects of different process variations such as density, number of CNTs and temperature variations are extensively evaluated by Monte-Carlo simulation, with respect to performance metrics such as delay, power dissipation and PDP of writing and reading cycles, also RSNM parameter for SRAM cells. The comparison exhibits that in all cases the proposed T-SRAM cell showing a substantial small standard deviation and considerable lower variability percentage than state-of-the art SRAM cells. So, the proposed T-SRAM cell design has the lowest sensitivity variations, thus it is an attractive choice for nano technology application in the presence of impact process and temperature variations. The simulation is done with Synopsys H-SPICE simulator in 32 nm technology under the condition of variations.

1. Introduction Static random-access memory (SRAM), which occupied 90% of chip area in 2013, is one of the main blocks in digital circuits [1]. Due to increase in demand of wireless sensor nodes and mobile multimedia applications, the demand of small size SRAM memory on chips increases. The design of T-SRAM with high capacity, smaller chip area and desired stability with the conventional complementary metal-oxide semiconductor (CMOS) technology is almost impossible as a result of increment of channel length modulation effect and leakage current because of high number of transistors. More than 70% of the area of very-large-scale integration (VLSI) circuits is included interior connections. This causes too many limitations in the fabrication and config-

⁎

uration of binary circuits [2]. The interior connection and output pins lead to the number limitation of interior and exterior connections [3]. Also the binary logic efficiency is decreased in robotics, controlling the processes and intelligent basic systems [4]. In order to overcome the difficulties, the logics with more than two values, which have finite or infinite logic levels with higher performance, like multiple-valued logic (MVL) [5] and fuzzy logic [6], are used instead of binary logic. By using MVL the performance, power dissipation and the energy storing ability is improved in compare with the conventional binary logic [7]. So far numerous investigations are done for designing the circuits with ternary logic in CMOS technology [8–10]. Also, more information can be conveyed over the same line and more data can be stored per memory cell by utilizing MVL technique [3].

Corresponding author. E-mail addresses: [email protected] (E. Abiri), [email protected] (A. Darabi).

http://dx.doi.org/10.1016/j.mejo.2016.10.009 Received 16 November 2015; Received in revised form 4 July 2016; Accepted 25 October 2016 0026-2692/ © 2016 Elsevier Ltd. All rights reserved.

Microelectronics Journal 58 (2016) 44–59

E. Abiri, A. Darabi

Fig. 1. The general view of CNTFET. (a) The top view. (b) The cross-sectional view.

cell in compare with the similar T-SRAM cells. The focus of the work is on the challenges faced in designing TSRAM circuit in nanoscale technology, where variations occur due to process such as density, number of CNTs and temperature. The impact of CNT density and also the effects of process (number of CNTs) and temperature variations are analyzed. Simulation results show that the proposed T-SRAM cell has lower write and read delay, power dissipation, PDP and better read static noise margin (RSNM) with substantial small standard deviation and the considerable lower variability percentage compared to other state-of-the art memory cells. The RSNM is also assessed in the presence of temperature variation. The results show that, the proposed T-SRAM cell has outperformed standard deviation and variability percentage than other SRAM cells. The paper is organized as follows: the fundamental structure of CNTFET is evaluated in Section 2, the proposed binary m-GDI cell and the proposed t-GDI cell are presented in Sections 3 and 4, respectively. The proposed T-SRAM cell is configured in Section 5. The array structure for the proposed T-SRAM cell is presented in Section 6 and the proposed decoder is presented in Section 7. The simulation results are provided in Section 8. Finally, the whole work is concluded in Section 9.

Different methods along ameliorating the operation, power dissipation and chip area for logic circuits are proposed in recent decade based on the conventional CMOS technology. One of the efficient techniques is the gate diffusion input (GDI) method [11]. This technique is useful for designing high stability and low power ternary memories with the minimum chip area. Nanoscale CMOS transistors are more susceptible to the long-term electrical-stress induced reliability degradations. When those devices are used for millimeter-wave frequency applications, a single transistor aging can lead to significant circuit performance degradation resulting from threshold voltage (Vth) shift and electron mobility (µn) drift [12]. Standard CMOS technology scaling driven by the benefit of integration density, higher speed of operation and lower power dissipation, has come across many barriers. It is now facing an acute problem of variability [12]. Carbon nanotube (CNT) field effect transistors (CNTFETs) are proposed in order to reach lower power and higher operation than silicon transistors [13,14]. The advantage of CNTFET in relation with the conventional silicon metaloxide-semiconductor field-effect transistors (Si-MOSFETs) is the dependency of threshold voltage to the dimension of the chip and the diameter of CNT which shows the best use of them in multi-threshold voltage (in other words, the MVL) designs [15]. Unlike the Si-MOSFET, p-type and n-type CNTFETs have the same carrier mobility (µn=µp) and hence the same drive current capability. This unique characteristic of the CNTFET device is very significant for simplifying the design and transistor sizing procedures of complex CNTFET-based circuits [16]. In this paper, first of all, the binary modified GDI (m-GDI) cell based on the basic GDI cell with regard to the unique properties of the CNTs is introduced. After that, the advantages of the efficient performance of the proposed m-GDI cell in designing the logical gates are presented [17] and flip-flops as the fundamental elements are described for designing the fundamental circuits with single-flux quantum (SFQ) logic (circuits provide faster operations with lower power consumption and information is stored in the form of magnetic flux quanta and transferred in the form of SFQ voltage pulses), such as demultiplexers, frequency dividers and binary counters [18]. So, the proposed m-GDI cell can be used for designing low power and high write and read stability binary static memory cells in nano technology [19]. Then, the first proposed design of ternary GDI (t-GDI) cell based on binary m-GDI cell is presented in nano process for designing circuits with MVL according to the unique characteristic of CNTs. By using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better performance, noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is designed and than compared with the conventional 6t-SRAM and load-less 4t-SRAM, P-Latch N-Access (PLNA) binary cells [20,21] and the other T-SRAM cells [22,23]. In the following, 4-words×4-bits memory with the help of the proposed T-SRAM cell (4×4 T-SRAM) and also with the conventional binary SRAM and the similar T-SRAM cells is designed. The achieved results express the higher performance and stability with the more improved PDP parameter in reading and writing cycle and with significant small standard deviation for the proposed ternary memory

2. CNTFET fundamental structure evaluation For CNTFETs fabrication as an electronic element, single-wall CNTs are used which is semiconductor. When chirality vector indexes are equal to n=m or n−m=3i (where i, is integer), a single-wall CNT is in the form of metal, else it is semiconductor. The diameter of CNTs (DCNT) due to (n,m) indexes can be measured from Eq. (1) [24]:

DCNT (nm ) =

a m 2 + n 2 + mn ≈ 0.0783 m 2 + n 2 + mn π

(1)

where a is a distance between two carbon atoms and equal to 2.495 Å. It is clear that in Eq. (1), the CNT diameter has a direct relationship with (n, m) indexes. Fig. 1 demonstrates the general view of CNTFET [24]. As it can be seen, the CNTFET has four terminals like silicon devices. The parts of CNT placed between gate and drain/source are heavily doped to decrease the series resistors of the transistor when the device is on [25]. Also by changing the gate voltage, the device is electrically ON and OFF. The (I–V) characteristic of CNTFET is like the one of Si-MOSFET. By decreasing the channel length due to the quantized energy along the axes (confined with the help of optical phonon scattering), the CNTFET current level is eliminated. The threshold voltage (Vth) is the voltage needed for activating a transistor. The threshold voltage of the individual CNT is equal to the half of first order energy gap which has a reversed relationship to the CNT diameter as Eq. (2) [24]:

Vth ≈

Eg = 2q

aVπ 3 × qDCNT

≈

0.436 DCNT (nm )

(2)

where Vπ = 3.033eV , Eg is the carbon π-π energy band, q is the load of electron and DCNT is the CNT diameter. According to the Eq. (2) with 45

Microelectronics Journal 58 (2016) 44–59

E. Abiri, A. Darabi 0.8

DCNT Vth 1.5

0.6

1

0.4

0.5 10

0.2

12

14

16

18

20

22

P

Threshold Voltage ( Vth (V) )

CNT Diameters ( DCNT (nm) )

2

G Out

N (a)

24

Chirality Vectors n ( with m = 0 )

(c)

Fig. 3. (a) Basic Gate Diffusion Input (GDI) cell. (b) With the minimum power dissipation. (c) With high speed (performance).

Fig. 2. Vth and DCNT with different chirality vectors for N-CNTFET.

Table 1 The producing of combinational logic gates with the basic GDI cell.

the change of chirality vectors, the CNTFET threshold voltage is altered consequently. In the structure of a CNTFET device (Fig. 1(a)), the distance between the centers of two adjoining nanotube channels under the same gate of a CNTFET is called a pitch, which considerably affects the width of the gate and the contacts of the transistor. The width of the gate of a CNTFET (Wgate) can be estimated based on the following Eq. (3) [16]:

Wgate = Max (Wmin, (N −1) × Pitch + DCNT ) ≅ Max (Wmin, N × Pitch )

(b)

N

(3)

where N is the number of nanotubes under the gate and Wmin is the minimum width of the gate. The gate width in CNTFET is not the effective channel width of the transistor. This only depends on the CNT diameter and the number of tubes under the gate and does not affect the drive current. As only CNT diameter has the strongest impact on the CNTFET performance while other process variations have only a small impact. The threshold voltage of the CNTFET has a reverse relationship with chirality vector of CNT (the diameter of CNT). Fig. 2 shows the threshold voltage (Vth) and CNT diameter (DCNT) with different chirality vectors for N-type CNTFET (N-CNTFET). For P-type CNTFET (P-CNTFET), the threshold voltage is the same as the one for N-CNTFET with considering the negative sign [26].

P

G

Out

Function

AB A +B A+B AB A B + AC A

F1

'0'

B

A

B '1' B C

'1' B '0' B

A A A A

'0'

'1'

A

F2 OR AND MUX NOT

decreasing the sub-threshold leakage current and the components of gate leakage current in most input states, related to the static conventional CMOS method [30]. As a consequence GDI technique not only facilitates the design with low number of transistors, but also decreases the power dissipation and the design complexity and increases the speed (performance) of Boolean function [11]. Up to now, several schemes have been introduced to modify and improve the GDI method [31,32]. But these proposals just worked on the conventional Boolean functions and particularly some of these schemes just designed for special circuits [33–35]. However according to the obtained results from designing the fundamental logical gates based on the m-GDI cell, the basic GDI cell has been re-implemented in such a way that can improve the PDP factor for all of the Boolean functions [17]. In Fig. 4, the proposed binary m-GDI cell with its layout is shown. The cell implementation is done by replacing the Si-MOSFET with CNTFET and then connecting the bulk terminal to the transistors’ gates (the use of DT-MOSFET technique). The special storage capacity in the used area in designing the proposed GDI cell as compared to the base GDI cell (the chip area for the pull-up “P” and pull-down “N” networks are reduced about 80% and 35% respectively, in comparison with the basic GDI cell at 32 nm technology [17]) is in such a way that complex

3. The proposed binary modified GDI (m-GDI) cell Among the main factors increasing the leakage current in the circuits that are the main causes of the power dissipation increment, the threshold voltage, channel length, decrement in gate oxide and number of transistors can be mentioned. Up to now there have been a lot of methods introduced to decrease the leakage current [11,27–29] including GDI [11] and dynamic threshold-voltage MOSFET (DTMOSFET) [29] methods. GDI method [11], which is based on employing simple cell, is shown in Fig. 3 with its layout to fulfill the low power dissipation and high speed (performance) cell. As it is clear in the figure a basic GDI cell has three inputs. G node, is the common gate input of N-type MOSFET (N-MOSFET) and P-type MOSFET (P-MOSFET) transistor, P node, is the drain or source of the P-MOSFET input and N node, is the drain or source of the N-MOSFET input. Also Out node is the output. It should be noted that the bulks of N-MOSFET and P-MOSFET transistor are connected to the N and P diffusion nodes, respectively. According to Table 1, by varying the configuration of the diffusing inputs of the pull-up “P” and pull-down “N” networks in the two transistors of basic GDI cell, different logical and Boolean functions can be obtained [11]. It should be noted that the producing of all logic, in Table 1, can’t be possible in CMOS process, therefore twin-wall CMOS or silicon oxide insulator (SOI) technology can be used for the cell fabrication. This method with the unique cell topology has an important role in

P

G Out

N (a)

(b)

Fig. 4. (a) The proposed binary m-GDI cell. (b) The layout.

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E. Abiri, A. Darabi

N NTI

Table 2 The truth table of ternary inverters.

Vdd

G Vdd

NTI (a)

PTI (a)

STI (a)

0 1 2

2 0 0

2 2 0

2 1 0

Out three types of ternary inverter operators. Due to Eq. (4) and suitable selection of diffusion inputs (Table 1) of the proposed t-GDI cell, a STI gate is created. Fig. 6 shows the STI gate based on the proposed t-GDI cell and voltage transfer characteristic (VTC) curves (figures of merit for the static behaviour of the ternary inverter gates to specific input voltage) of the STI gate. This ternary inverter, like the one proposed STI gate cell in Ref. [4], has a unique structure and is included NTI gate, STI and PTI gates in a 6-transistor structure. According to the Fig. 6(b), the proposed STI gate is the primary building block for the proposed T-SRAM cell design because of its ability to produce a suitable logic level ‘1’ at the output. Due to this figure, the voltage of each level is equal to Vdd/3, which means that 0.9 V supply voltage is divided into three equal parts. If the input voltage is 0 V, the output voltages of PTI and NTI gates equal to Vdd, and the effective voltage of PTI equals to Vdd. Similarly, for Vdd input voltage, the output voltages of PTI and NTI gates equal to 0 V, which leads to 0 V of PTI gate effective voltage. Finally, if the input voltage is Vdd/2, PTI and NTI gates output equal to Vdd and 0 V, respectively. PTI and NTI gates connect to the diffusion input of each other with P-CNTFET and N-CNTFET in pull-up and pull-down networks respectively, which have same dimensions, and the output voltage of STI gate (VSTI) equals to Vdd/2 based on Eq. (5):

PTI

P

(a)

(b)

Fig. 5. (a) The proposed t-GDI cell. (b) The layout.

logical circuits and binary static memory cells can be implemented with higher integration density on a smaller chip area [17,19]. 4. The proposed ternary m-GDI (t-GDI) cell Despite binary logic in which logical levels are restricted to two possible states, namely false ‘0’ and true ‘1’, there exists an alternative named multiple-valued logic (MVL) [5]. In this system, theoretically, one can define an unlimited number of logical levels, but in reality it is limited and this limitation mainly depends on the used technology. Ternary logic functions are defined as those functions having significance if a third value is introduced to the binary logic. So, the ternary logic, which is a kind of MVL, has three meaningful logic levels. The logic levels are shown with ‘0’, ‘1’ and ‘2’ symbols which are equals to 0, Vdd/2 and Vdd, respectively. Fig. 5 shows the first presented design of t-GDI cell, based on the proposed binary mGDI cell, with its layout. The t-GDI cell is configured with employing binary inverters with negative ternary inverter (NTI) gate cell and positive ternary inverter (PTI) gate cell unbalanced voltage transfer characteristic (VTC) curve to the common diffusion input of each transistors in pull-up and pull-down respectively of binary m-GDI cell (Fig. 4) and also with re-placing of P and N diffusion terminals. The creating of ternary logic levels in the proposed t-GDI cell is done with selecting the appropriate threshold voltages for each of the CNTFETs. In the proposed cell, PTI and NTI gate cells transmission points are set due to the appropriate threshold voltages for CNTFETs with the determined CNTs diameter [36]. In this design, P-CNTFET transistors with high threshold voltage and N-CNTFET with low threshold voltage for the configuration of NTI gate and P-CNTFET with low threshold voltage and N-CNTFET with high threshold voltage for the configuration of PTI gate are used. The proposed t-GDI cell has more ability of storing energy, better noise margin and lower limitation of interior and exterior connections, in designing of ternary logic circuits, than the conventional binary logic circuits. A general ternary inverter is an operator (gate) with one input a and three outputs (denoted by y0, y1, and y2) such that (Eq. (4)):

VSTI =

(5)

5. The proposed differential T-SRAM cell with employing the STI gate and CNTFET The design of simple CMOS ternary memory cell with high performance is always challenging. For example, in Ref. [37] multiple supply voltage is used for ternary designing which leads to considerable complexity of design and increasing the expenses. In Ref. [38] only one supply voltage is used, but the configuration of it with CMOS technology is complicated now a days. Also in designing of ternary memory cell in Ref. [39], the large dimension transistors are used which is inappropriate in designing high density ICs. The design of first ternary memory cell with employing CNTFET has been presented in [40].also, a modified cell with the same substrate structure has been proposed [22,23]. In the proposed ternary memory, the design is done based on storing ternary logic levels by the best selection of chirality vectors of CNTs which differs from the conventional designs with the additional supply voltage [41]. Fig. 7 shows the structure of the proposed novel design of a TSRAM cell which has lower complexity of control signals, with minimum width of transistors and simpler layout than equal cell of Ref. [22,23,40] in the same technology. The proposed STI gates (left

⎪ ⎪

⎧ 2, if a ≠ 2 y2 = C2(a ) = ⎨ ⎩ 0, if a = 2

VNTI + VPTI 2

where VNTI and VPTI are output voltages of NTI and PTI gates, respectively. Due to VTC curve of Fig. 6(b), it is clear that STI gate has nearly to 0.3 V noise margin for the other operational nodes. The noise margin is described as the voltage difference between input operational ∂V output nodes of (0.02 V, 0.45 V, 0.9 V) with unit gain ( ∂Vinput = − 1). According to the Table 1, by selecting the appropriate P and N diffusion terminals, fundamental gates of AND, OR and MUX in ternary circuit designs can be gained. Therefore more energy storing, higher noise margin and lower complexity of interior and exterior connections are the advantages of the proposed t-GDI cell.

⎧ 2, if a = 0 y0 = C0(a ) = ⎨ ⎩ 0, if a ≠ 0 y1 = C1(a ) = a = 2 − a ⎪ ⎪

Input (a)

(4)

So, the implementation of ternary inverter requires three inverters, and they are a NTI gate, a standard ternary inverter (STI) gate, and a PTI gate, if y0, y1, and y2 in equation (4) are the outputs [9]. The truth table of the three ternary inverters is shown in Table 2. As there are 47

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E. Abiri, A. Darabi

D = 0.783 nm

Vdd D = 2.583 nm

~ 320 mV

NTI (a)

Input (a) (output)

Input (a)

PTI (a)

a) STI (a)

D = 1.252 nm ∂Voutput = −1 ∂Vinput

Vdd D = 1.252 nm

STI (a)

~ 280 mV

PTI (a) D = 0.783 nm

~ 300 mV

NTI(a)

D = 2.583 nm

Vdd (b)

(a) Fig. 6. (a) The STI gate cell. (b) VTC curve of the STI gate.

Bit Line (BL)

Bit Line Bar (BLB)

WL (Word Line) Vdd

Vdd

N-Access N-Access

AL

qb

q Vdd

Vdd

AR

P-Access

P-Access

Vdd

Vdd

STIL gate

STIR gate

WLB (Word Line Bar) Fig. 8. The array structure for designing T-SRAM cells.

Fig. 7. The proposed T-SRAM cell with employing STI gates.

6. Presenting the array structure for the proposed T-SRAM cell

STI gate (STIL) and right STI gate (STIR)) are used as the basic storing element such as conventional six-transistor binary memory cell. According to the figure, it is obvious that the employing of left and right access transistor pairs of N-CNTFET and P-CNTFET (AL, AR) with word line (WL) and its complementary (WLB) in each data line of the memory cell. Writing cycle: In writing cycle data quickly stores, refreshes and reaches to the constant state in q and qb nodes from AL and AR transistors by setting WL and WLB control words to the high and low level voltages, respectively. Holding cycle: This cycle is started by setting WL and its complementary (WLB) to the low voltage and consequently deactivating of AL and AR transistors which causes separation of memory cell core (STI gates). Reading cycle: Before this cycle, bit data lines (BL, BLB) are precharged (PRE) to Vdd/2 and the data storing in q and qb nodes from writing cycle is initiated by setting WL and WLB control words in high and low voltage levels, respectively. The advantages of the proposed TSRAM cell are higher speed transferring data to the inside and outside of the cell, lower complexity of cell controlling structure and its layout in compare with the other state-of-the art ternary memory [22,23] cells.

The array structure for the designed T-SRAM cell is shown in Fig. 8. The proposed structure has an important role in designing the T-SRAM cell logic structure with high capacity. Fig. 9 shows the structure of a 1word×1-bit T-SRAM (1×1 T-SRAM) cell with single storing cell. It should be noted that for designing reading and writing blocks in this topology, all transistors use the proposed binary m-GDI cell with F2 function and STI gates as a particular t-GDI cell. Before this cycle, write_bit line (W_BL) and its complementary (W_BLB) writing lines in data writing block charges to Vdd/2 by P2 and P3 transistors in binary m-GDI cell with F2 function, while write_enable/pre-charge (W_EN/PRE) is set to the low voltage level. Therefore with OFF, N2 and N3 transistors in m-GDI cell, no input is received from D_in and its complementary (D_inb) input lines, even by applying low voltage to the virtual ground (VGND1), in other words the structure has no connection to the outer world. In this case writing block is separated from T-SRAM cell block, as a result of deactivated A1 and A2 gate transfer transistors and it is prepared for receiving data. By adjusting W_EN/PRE to the high level of voltage and virtual ground to the low level of voltage, the input data

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E. Abiri, A. Darabi

STI gate

Vdd VGND 1

Data Input (D_in)

Complementary Data Input (D_inb)

MP1

MN1

N3

Vdd

Write Enable (W_EN)/ Precharge

P2

P3 Vdd/2

Vdd/2

Word 2 (d2)

A2

A1 WL ( Word Line ) Vdd

Vdd

AR

AL

N-Access

Bit Line (BL)

T-SRAM Cell

Word 1 (d1)

N-Access

qb

q

Vdd

Vdd

Decoder Enable

Bit Line Bar (BLB)

W_BL

N2

Word 0 (d0)

F2 Function

W_BLB

Write Block

Vdd F2 Function

Vdd

Vdd

Vdd

Word 3 (d3)

Vdd

a Address Inputs

P-Access

P-Access

“0”

b

NOT gate

WLB (Complementary Word Line)

A3

Vdd

VGND 2

Outb

Out Vdd

N5

R_BLB

R_BL

Fig. 10. The proposed 2×4 decoder with an employed CNTFETs. Vdd N4

respectively, by the arranged ternary inverters and they are placed to Out and its complementary (Outb) output nodes. Finally the basic data with the maximum voltage swing is received from data_output (D_Out) and its complementary (D_Outb) ternary inverters.

Vdd

P4

P5

Vdd/2 F2 Function Vdd

Vdd/2 Vdd F2 Function

Vdd

7. The proposed decoder with employing CNTFET and inverter (particular functional of binary m-GDI cell)

Vdd

D_Out

Vdd

D_Outb

Read Block (Sense Amplifier Block )

NOT gate

A4

Read Enable(R_EN) (Sens Enable (SAEN)) / Precharge

The selection of the special word is done in memory by choosing the address and providing the path with the decoder. Since the 4×4 SRAM has 4-words for designing it the 2×4 decoder is required (four controlled outputs with two selecting line). Fig. 10 shows, the proposed decoder which includes the CNTFET transistors [19]. Based on Fig. 10, the decoder is activated by selecting the enable pin connected to the PCNTFET transistors as the up-networks. Otherwise no pulse is created on the word lines as the output of decoder and no word is selected. The decoder structure is based on controlling of the down networks (NCNTFETs) with two m-GDI inverters in order to create the controlling pulse for selecting the word in (D0-D3) memory. By employing the two-bit address only high logic employed to the enable pin can pass through the decoder and reach to the output terminal. The other output terminals reach to the low logic by activation high logic or two down networks connected to the word line. Therefore the controlling pulse is created for selecting the word.

Vdd

Vdd Vdd

Fig. 9. A 1×1 T-SRAM cell by the proposed reading and writing blocks with the proposed ternary memory cell.

are inserted to the D_in and D_inb input lines with an organized ternary inverter and then they are prepared for storing from the on transistors path of A1 and N2, A2 and N3 for BLB and BL lines respectively. Finally the data are stored by placing the WL with decoder and selecting the cell from access transistors in T-SRAM cell from q and qb nodes. It should be mentioned that the reading block is separated from a ternary memory cell in writing cycle by setting read_enable/sense_enable/pre-charge (R_EN/SAEN/PRE) at the low level. By adjusting the WL and W_EN/PRE control signal terminals to the low level of voltage and setting the virtual ground to the high level of voltage for the second time, the writing cycle is finished and the data holding cycle initiates by separating the memory cell from BL and BLB lines as a consequence of deactivating access transistors. Before the reading cycle is started, in holding cycle, the data of received lines charge to Vdd/2 by P4 and P5 transistors from the proposed binary m-GDI cell with F2 function, while R_EN/SAEN/PRE is set to the low level of voltage. When R_EN/SAEN/PRE is in a high voltage and also the voltage of virtual ground (VGND2) is set to the low level of voltage and WL is switched to the high voltage with the help of decoder, ternary memory cell is selected again. In this situation the data are sensed and amplified with A3, N4 and also A4 and N5,

8. Simulation results In this part, first, evaluating VTC curves, noise margins and standard deviations of the STI gate cell designed based on the proposed t-GDI cell with other CNTFET-based STI gate designed is presented. Then, the results obtained from the proposed 2×4 decoder are presented. In the following, the read stability of the proposed TSRAM cell and the similar CNTFET-based T-SRAMs at the same power supply are compared with each other. Also reading and writing delays, standby power dissipation and standard deviations of the other memory cells are evaluated. The simulation results waveforms of the proposed 1×1 T-SRAM cell, also the results of delay, power dissipation, PDP and standard deviations for other 4×4 T-SRAM cells, with the proposed structure, are provided. The simulation is done at the 0.9 V 49

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for low voltage applications. Besides, the higher gain and more desired behaviour in transient region of the proposed STI gate cell with different logic level result in significant decrease of static power dissipation in compare with the other presented cells. According to the results, Table 3 shows that with process variation, the worst noise margins of the proposed STI gate is 128 mV at 0.9 V power supply and more than any other the ternary inverters. A binary cell has a single type of signal variation (such as ‘0–2 (2– 0)’), while the ternary cell has three types of signal variations (such as ‘0–1 (2–1)’, ‘0–2 (2–0)’, and ‘1–0 (1−2)’). Noise margins of the ternary inverter circuits for all logic level transitions (low levels signal noise margin (NML) and high levels signal noise margin (NMH)) with average noise margin (Avg.) and standard deviation (Std. Dev.) have been measured and are shown in Table 3. According to the results, the proposed designs have larger noise margin (about 1.055 times) and lower standard deviation (about 1.087 times) as compared with the other CNTFET-based STI gate designs. Fig. 12 shows the comparison results of the proposed STI gate cell and the presented STI gate cells in [45–47] based on various power supply voltages and frequencies. The simulation is done under the condition of 0.9 V supply voltage, 10fF load capacitor (CL) and room temperature in 32 nm technology. The delay of gates is measured by considering all possible variations after employing three-level buffers. According to the Fig. 12, it can be seen that the proposed STI gate cell has the ameliorated delay, power dissipation and energy consumption as expected.

supply voltage, 500 MHz frequency and room temperature. The cell ratio (CR) and the pull-up rate (PR) for the 6T-SRAM are 1.33 and 1 respectively, the corresponding rates for the proposed T-SRAM are CR=PR=1 (because of the equal ability of N-CNTFET and P-CNTFET current). For the load-less 4T-SRAM P-Latch N-Access (PLNA) the CR is unit. The simulations for the memory cells based on the CNTFET and the Si-MOSFET are done by using the Stanford model [42] and the BSIM PTM [43] in the Synopsys H-SPICE simulator. The selection of minimum dimensions for transistors leads to the low parasitic capacitors and high speed for a design. In the simulations, by opting the pitch parameter to 4 nm and 8 tubes equal to 32 nm, the minimum widths of CNTFETs are set in order to decrease the delay [44]. Similar to [44], the minimum width for Si-MOSFETs is chosen 48 nm. As [22,23] used the CNTFET-based ternary memory cells with the same length of the gate dimensions, therefore the proposed ternary cell based on CNTFET technology is compared with [22,23] ternary memory cells. At the end of this section, the impact of CNT density and also the effects of process (number of CNTs) and temperature variations with the standard deviation and the variability percentage are analyzed for all SRAM cells.

8.1. Evaluating VTC curve and noise margin of the ternary inverters STI gates are used as a fundamental logic gates in T-SRAM cell designs. In this section, the VTCs and the standard deviation comparison of the STI gate designed by the proposed t-GDI cell with other designed CNTFET-based STI gates is presented. Fig. 11 shows the results of the Monte-Carlo DC analyses for the VTC curve of the proposed STI gate cells and [45–47], at the same supply voltage. For CNT-based devices, the variations in the oxide and gate width have no negligible impact, due to the nature of CNTFETs, the diameter of the tubes (thus the chirality), the distance between tubes (pitch), and the number of tubes under the gate (that determine the effective width of the transistor) affect CNTFET based circuits and devices [40]. The Monte-Carlo simulation (with 30 runs) has been performed to assess process variations; for simulation, chirality and pitch are modeled as a ± 5% Gaussian distribution with variation at the ± 3 sigma level. As demonstrated in Fig. 11, the VTC curves of the proposed STI gate has very steep transition regions and are quite less sensitive to the simultaneous variations of process as compared to the STI gate cell designs of [45–47]. Due to Fig. 11, the voltage divided of each levels for inverters is equal, which means that supply voltage is divided into equal parts for proposed STI gate compared with other ternary inverter designs and it is clear from the VTC curve that the proposed STI gate has higher noise margin than the other designs which makes it suitable

8.2. Evaluating the performance of the proposed decoder and RSNMs of memory cells In Fig. 13 the simulated output waveforms of the 2×4 decoder (shown in Fig. 10) are presented with the selected data sequence for addressing the decoder by the enabler signal. The data sequences a and b are chosen in such a way to cover all the probable states of the decoder's input signals. According to the figure, based upon the address's inputs in each cycle, just one of the decoder's outputs will be activated and the others will be inactivated. This means that only single word can be chosen based on the applied address. According to the achieved butterfly curve, static noise margin (SNM), for a SRAM cell equals to the largest diameter of the squares created between VTC curves, and is measured visually [48]. Usually stability is described with SNM [48], which is stated with the maximum DC noise voltage that the cell can tolerate before any changes in the stored data. In order to evaluate SNM criterion butterfly curve can be used which is achieved from the combination of VTCs related to the q and qb nodes (VTC for STIL gate and the VTC¹‫ ־‬for STIR gate) of memory cell in the same surface. Fig. 14 shows the Monte-Carlo DC analyses of the butterfly curves in reading cycle (read static noise margins (RSNMs)) for the proposed T-SRAM and its similar ternary memory cells in Ref. [22,23], with the conventional load less 4t-SRAM P-Latch N-Access (PLNA) and 6t-SRAM binary cells [20,21] for the purpose of comparison and evaluation, at the same supply voltage. According to Fig. 14, RSNM of the ternary memory cell has two more extra squares than the one of binary memory cell. RSNM of the ternary memory cell is concluded from the smallest square diameter of all squares [40]. A and E points in the figure show the fixing of ‘0’ and ‘2’ data in q and qb nodes of the SRAM cells. Also B, C and D (slip points) show the unstable fixing of data in q and qb nodes. For the desired read stability, A and E stability points are closer to the characteristic axes and C semi-stability point is set to the center (on the angle bisector which is created from characteristic axes). The simulation results show that RSNM is 148.4 mV for the proposed ternary memory cell at the supply voltage is 0.9 V and the memory cell is in the storing state of logic ‘1’, while the one for ternary memory cell of Refs. [22] and [23] is 123.7 mV and 125.3 mV, respectively. Also RSNM parameter for the conventional 6t-SRAM

Fig. 11. The results of the Monte-Carlo DC analyses for the VTC curve of STI gate cells.

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Table 3 Noise margins of the ternary inverter gates (Vdd=0.9 V, T=27 °C). Design

Proposed STI STI of [45] STI of [46] STI of [47]

Noise margins

NML 0 ↔ 1 (mV)

NMH 0 ↔ 1 (mV)

NML 1 ↔ 2 (mV)

NMH 1 ↔ 2 (mV)

Noise Margin (mV)

128 114 62 121

286 280 297 290

298 297 256 286

132 97 113 103

128 97 62 103

Avg.

Std. Dev.

211 197 182 200

81.12 91.89 97.29 88.24

Fig. 12. Maximum delay, power dissipation and energy consumption of the proposed STI gate and Ref. [45–47] STI gate cells. (a–c) Frequency variations, (d–f) Supply voltage variations.

modeled as a ± 5% Gaussian distribution with variation at the ± 3 sigma level. According to the Fig. 14, it is seen that with process variation, the worst RSNM of the proposed CNTFET ternary memory cell is 82.3 mV, while the one for ternary memory cell of Ref. [22] and [23] is 58.1 mV and 68.6 mV respectively, at same power supply, hence close to the 32 nm CMOS binary cells in the ideal case. The power dissipation for a memory cell during writing cycle is

and load less 4t-SRAM are 72.3 mV and 58.7 mV, respectively. Therefore the best read stability belongs to the T-SRAM cell, while the lowest read stability belongs to the conventional load less 4t-SRAM cell. By decreasing supply voltage, RSNM is decreased for all SRAM cells and it can’t be evaluated for load less 4t-SRAM as it is too small. The Monte-Carlo simulation (with 30 runs) has been performed to assess process variations; for simulation, chirality and pitch are

Fig. 13. The simulated output waveforms of the proposed 2×4 decoder.

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significantly important for memory systems which occupied large portion of chip area. Ref. [24] shows that the relation of ON to OFF current of the CNTFET is lower than the one of the Si-MOSFET. The standby power dissipation of the ternary and binary memory cells with average standby power dissipation (Avg.) and standard deviation (Std. Dev.) is presented in Table 5. According to the results presented in Table 5 and as expected, the standby power dissipation and the standard deviation (about 2.398 times) of the proposed T-SRAM cell are significantly lower than for other T-SRAM cells. Fig. 15 shows the relation between RSNM and write time for SRAM cells. This relationship for the proposed T-SRAM cell is more than the other T-SRAM cells [22,23] with minimum width for CNTFETs and the conventional binary SRAM cells [20,21]. It shows that the proposed TSRAM cell has higher stability with the worst writing time in compare with the one of the similar CNTFET-based T-SRAM cells and the conventional binary SRAM cells designed with Si-MOSFET. According to Fig. 15, this relationship is significantly improved for the proposed T-SRAM when the memory cell is in logic ‘1’ during the state of storing. Fig. 16 shows the writing block waveforms of 1×1 T-SRAM cell which is shown in Fig. 9. As it is clear in Fig. 16, before the writing cycle is started, holding cycle prepares writing block for receiving the data. Fig. 17 shows the simulation results for evaluating the performance of ternary memory cell block in Fig. 9. The simulation results for evaluating the reading cycle is shown in Fig. 18. It should be marked that the ruined effects of loading in a reading and writing cycles of the proposed design is considerably diminished related to the conventional topologies, as a repercussion of floating the T-SRAM cell block during the holding cycle. Given the fact that transmission gates, which their bulk is connected to the gate (tied-gate), are employed, the speed of transferring data during the executive cycle is noticeably ameliorated. Fig. 19 presents the layout of proposed decoder circuit which is used CNTFETs and 1×1 T-SRAM cell with the proposed T-SRAM cell topology. As a result of choosing CNTFETs with the same width, the dimensions of GDI cell are considerably decreased (the pull-up and pull-down networks area is decreased about 80% and 35%, respectively in binary m-GDI cell than basic GDI cell [17]) which culminates in designing the high storing capacity T-SRAM cells with the proposed structure in nano process. The achieved results of delay, power dissipation, PDP criteria and the power consumption of holding cycle with average of delay, power dissipation and PDP (Avg.) and standard deviation (Std. Dev.) for the arranged 4-words×4-bits T-SRAM (4×4 TSRAM) cell with the proposed structure is presented in Table 6 for

Fig. 14. The Monte-Carlo DC analyses of RSNMs for the proposed T-SRAM cell and TSRAM cells of [22,23], binary SRAM cells of [20,21].

more than the one for reading cycle as a result of swing charge and discharge in bit lines during writing cycle [16]. Power-Delay Product (PDP) is the main factor for performance measurement. It makes a balance between delay and power consumption parameters and can be obtained from the following equation: (6)

PDP = Maximum(Delay) × Average(Power Consumption )

Thus in this paper, the PDP criterion of the memory cell is considered with the production of maximum delay of changing the states of 1←0 ، 1←2 ،0←1، 2←0، 2←1 and 0←2 during reading and writing cycles of ternary logics with the maximum power consumption. Table 4 shows the delay for writing and reading cycles with average write and read delays (Avg.) and standard deviation (Std. Dev.) of the ternary and binary memory cells. According to the results of Table 4, the proposed ternary memory cell has lower standard deviation (about 2.197 times and 1.019 times for writing delay and reading delay, respectively) as compared with the other CNTFET-based ternary memory designs. The power dissipation, especially standby power dissipation is Table 4 Reading and writing delays for ternary and binary memory cells. Tech.

Write Delay (ps)

Change of Values ‘0’→‘1’

‘1’→‘2’

‘2’→‘0’

‘0’→2’

‘2’→1’

‘1’→0’

27.7 22 6.23

8.54 13.33 5.41

14.1 12.7 2.20

11.11 16.8 2.11

18.54 13.04 10.70

CNTFET (Ternary)

Ref. of [23] Ref. of [22] Proposed

39.74 30.2 5.01

Si-MOSFET (Binary)

Write Delay (ps)

Change of Values ‘0′→‘2’, ‘2′→0’ 15.33 11.3

6t-SRAM [20] 4t-SRAM [21] Tech.

Read Delay (ps)

CNTFET (Ternary)

Ref. of [23] Ref. of [22] Proposed

Si-MOSFET (Binary)

Read Delay (ps) 6t-SRAM [20] 4t-SRAM [21]

Change of Values ‘0’ 93.1 84.4 89.2

‘1’ 67.3 50.6 47.2

Change of Values ‘0′→‘2’, ‘2′→0’ 11.6 9.40

52

‘2’ 42.7 39.9 83.5

Avg.

Std. Dev.

19.95 18.01 5.27

10.772 6.334 2.883

Avg.

Std. Dev.

71.10 59.96 73.3

20.577 18.965 18.601

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Table 5 Standby power dissipation for ternary and binary memory cells. Tech.

Standby Power Dissipation (W)

Storing ‘0′

Storing ‘1′

Storing‘2′

Avg.

Std. Dev.

CNTFET (Ternary)

Ref. of [23] Ref. of [22] Proposed

2.456 e-07 3.515 e-07 14.845 e-09

9.827 e-08 9.113 e-08 2.023 e-08

1.418 e-08 5.104 e-10 1.490 e-07

3.580 e-07 1.477 e-07 6.135 e-08

2.571 e-07 1.487 e-07 6.200 e-08

Si-MOSFET (Binary)

Standby Power Dissipation (W)

6t-SRAM [20] 4t-SRAM [21]

Storing‘0’, Storing ‘2’ 8.26 e-07 8.16 e-07

consumption criteria, it can be concluded that the PDP for the proposed 4×4 T-SRAM cells is properly improved, where, the standard deviation of PDP in writing and reading cycles, which is about 2.63 times and 1.314 times, respectively as comparison to the similar CNTFET-based 4×4 T-SRAM cells implemented in the same technology. According to the results obtained from the different parts we can say that for the proposed T-SRAM cell, we can obtain to the better results as comparison to the similar CNTFET-based T-SRAM cells implemented in the same technology. 8.3. Evaluating process and temperature variations of SRAM cells In a CNTFET technology there are two types of process variations such as conventional and CNT-particular process variations. Conventional process variations such as channel length, channel width, oxide thickness and threshold voltage have a smaller impact on a CNTFET technology compared to a Si-MOSFET due to unique properties such as high scaling, electrostatic properties and ballistic transport. However, CNT-particular process variations that directly change the number of CNTs and the pitch in each CNTFET can significantly degrade the performance of a CNTFET circuit [49–51]. The threshold voltage (Vth) compensation technique effectively reduces the temperature and process variability on the voltage multiplier performance [52].

Fig. 15. RSNM /Write Time relation for the proposed T-SRAM, ternary memory cells of Ref. [22,23] and the binary SRAM cells of Ref. [20,21].

reading and writing cycles. According to the result of delay in reading and writing cycles, proposed T-SRAM cell has the appropriate performance. The power consumption of the proposed T-SRAM cell in all writing, holding and reading cycles is eliminated as a consequence of decreasing the leakage currents, the suitable sub-threshold behaviour of CNTFETs and also employing t-GDI cell. At last, by evaluating the delay and power

Fig. 16. The simulation result waveforms of the proposed 1×1 T-SRAM cell of writing block.

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W rite ‘2’

Hold/Sleep Cycle

Read ‘2’

Hold/Sleep Cycle

W rite ‘1’

Hold/Sleep Read ‘1’ Cycle

Hold/Sleep Cycle

Q [V]

WLB [V]

WL [V]

BLB [V]

BL [V]

Hold/Sleep Cycle

884 m V

886 m V 450 m V

Qb [V]

450 m V 0.267 m V

450 m V

450 m V

0.28 m V

Fig. 17. The simulation result waveforms of the proposed 1×1 T-SRAM cell.

to the increase in gate width (but no increase in the number of CNTs). It can be seen that the increase of power dissipation is relatively small compared to the increase of delay. When the density is changed from ND to HD, more CNTs can be deposited at the same 32 nm gate width of each CNTFET; hence, the delay of write and read cycles is decreased. However, the power dissipation of write and read cycles is increased which leads to the increasing of the PDP of write and read cycles. As for the RSNM parameter, Table 7 shows that the density does not so affected the RSNMs, because no change in threshold voltage and gate width sizing ratio between CNTFETs are involved. Finally, According to the results presented in this Table, it can be seen that 30 CNTs/um (normal density (ND)) is the best value of density for the proposed TSRAM cell.

In this article, for T-SRAM cells which are based on CNTFET, the CNTparticular process variations or changing the pitch and the number of CNTs in each CNTFET are also considered. Priority to the previous implicit variations, the density of a CNTFET must be determined, because the performance of a circuit based on CNTFET is strongly affected by this parameter and different values for the gate width and the number of CNTs are used in the design of CNTFET circuits. To evaluate the effect of a process variations, Monte-Carlo simulation has been performed 500 times with a limited and Gaussian distribution ( ± 5% distribution at the ± 3 sigma level) for the gate width and length of all SRAM cells considered in this section. 8.3.1. Density In the previous sections presented simulation results were obtained at a pitch of 4 nm. Also the minimum gate width is 32 nm and there are eight CNTs. In this case, the density is about 30 CNTs/um and in this paper, it is referred to as the normal density (ND). According to previous research [49] has shown that a high density ( > 100 CNTs/um) is required for the CNTFET to have better performance than a SiMOSFET for digital circuit design (memory cell is not included in [49]). However, a density of 10 CNTs/um is allowed using present technology, at this density most semiconducting CNTs can be aligned [50]. In the following, the performance of all SRAM cells mentioned in the previous is assessed when the density is changed (the change in pitch and the number of CNTs). Using high density (HD), (100 CNTs/ um), normal density (ND), (30 CNTs/um) and low density (LD), (10 CNTs/um) different density values, the SRAM cells are designed with the same conditions as discussed in previous sections. Table 7 shows the performance metrics for all SRAM cells at different density values. According to this Table, it can be seen that when the density is changed from ND to LD, delay of write and read cycles and power dissipation of write and read cycles for T-SRAM cells are significantly increased, due

8.3.2. Number of CNTs As mentioned previously, during manufacturing not all CNTs may be deposited on the substrate. This can significantly degrade the performance of a CNTFET [49–51]. Monte-Carlo simulation (with 500 runs) was performed for the ND and LD CNTFET-based T-SRAM cells. A random limit distribution function was utilized i.e. decreasing the number of CNTs in each CNTFET on a random basis till the TSRAM cell ceases to operate correctly. Other the decrease such as the number of CNTs in T-SRAM cells with the HD value and the increase of the number of CNTs in T-SRAM cells with the different ND and LD values were not considered due to the limitations in the Synopsys HSPICE simulator (that cannot support the simulation of unevenly positioned CNTs [51]). The root causes of variations are scaling. Variability is becoming a metric of equal importance as RSNM and write static noise margin (WSNM) in SRAM cell [53]. The problem of variability (defined as the ratio of standard deviation (σ ) to mean ( μ ) of a design metric) becomes even more acute with greater miniaturization. 54

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Fig. 18. The simulation result waveforms of the proposed 1×1 T-SRAM cell of reading block.

Vdd=0.9 V and 1.2 V). So, the variability percentage of RSNMs for the proposed T-SRAM cell is smaller for different ND and LD values with temperature variation, due to the unique design, is intended to start at the lowest chip area and power dissipation of the proposed ternary memory cell in same technology.

When the number of CNTs is decreased randomly, the average standard deviations of the delay, power dissipation and PDP in write and read cycles have been measured in the SRAM cells and the results are shown in Table 8. There are three corners process models evaluated; namely, slow P-MOSFET, slow P-MOSFET (SS model), typical N-MOSFET, typical P-MOSFET (TT model) and fast NMOSFET, fast P-MOSFET (FF model) [52]. According to the results presented in Table 8, it is observed that the values of the standard deviations and percent variability (σ / μ) of delay, power dissipation and PDP in write and read cycles are very small for the proposed T-SRAM with different ND and LD values (at various process corners), in comparison with other ternary memory cells. The RSNM for other TSRAM cells has been also assessed under the scenario of randomly decreasing the number of CNTs. According to the results presented in Table 8, the percent variability of RSNM parameter for proposed TSRAM cell is nearly zero because the unique design is intended to start at the lowest chip area and power dissipation of the proposed ternary memory cell in same technology.

9. Conclusion CNTFETs are a viable candidate for ternary memory design based on MVL in the nano scale technology and by considering the extensive process and temperature variations analysis. In this paper, first t-GDI cell based on the m-GDI cell is proposed in order to design the low power and high performance ternary circuits using MVL. In designing t-GDI cell, the unique characteristic of threshold voltage dependency to the CNTs’ diameter in CNTFETs is used. The proposed t-GDI cell with the minimum width is utilized in designing ternary logic memory circuits in nano process. The optimization of the PDP criterion of the proposed cell is done due to the same current sinking of P-CNTFET and N-CNTFET and choosing the minimum and equal sizes of transistors. By using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margin (about 1.055 times) and also small standard deviation (about 1.087 times) of results, first novel design of a ternary SRAM (T-SRAM) cell is proposed. The presented T-SRAM cell has the improvement with small standard deviation for delay of writing and reading cycles (about 2.197 times and 1.019 times, respectively) and also in the standby power dissipation (about 2.398 times), so better RSNM parameters in comparison with the similar T-SRAM cells in 32 nm technology. According to the results obtained from the different parts it can be said that for the proposed TSRAM the better results are obtained as comparison to the similar T-

8.3.3. Temperature The RSNMs has been also assessed under the conditions of randomly decreasing the number of CNTs for temperature variation at various process corners and the results are presented in Table 9. ITRS anticipates temperature variation within the range from −55 to 155 °C [1]. Therefore, temperature is randomly varied within this range. According to the results presented in this Table, the proposed TSRAM cell for different ND and LD values shows a very small standard deviation and lower percent variability for the CNT-particular process variation. Also, according to the results, RSNM parameter with a small numerical changes with increasing temperature is decreasing (at 55

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Fig. 19. The layout of (a) proposed decoder circuit. (b) 1×1 T-SRAM cell with the proposed reading and writing blocks and the proposed memory cell.

the standard deviation of PDP in writing and reading cycles, which is about 2.63 times and 1.314 times, respectively) as comparison to the similar CNTFET-based 4×4 T-SRAM cells implemented in the same technology. Also it can be considered that the data transmission and storing is done with high performance and precision which is appropriate for designing modern ternary memories. Extensive simulations to find the best density and to evaluate the effect of process and temperature variations have also been presented.

SRAM cells implemented with the method in the same technology with minimum width for CNTFETs. Finally specific and simple structure of 4×4 T-SRAM with low interior connection and high energy storing is designed with proposed ternary memory cell. The achieved results of the proposed 4×4 TSRAM simulation in 32 nm technology under the condition of 0.9 V supply voltage, 500 MHz frequency and room temperature, show the improvement of PDP criterion in writing and reading cycles, (where,

Table 6 The result of delay, power dissipation and PDP for 4×4 T-SRAM cells in reading and writing cycles with the proposed structure. Tech.

4×4 SRAM Cell

@ Vdd=0.9 V, f=500 MHz, T=27 (°C) Delay Parameters

Power dissipation Parameters

PDP Parameters

Write (ps)

Read (ps)

Write (uW)

Hold (uW)

Read (uW)

PDP (Write) (aJ)

PDP (Read) (aJ)

12.04 16.53

28.35 37.64

5.04 5.55

2.89 11.17

5.88 3.27

60.68 91.74

166.69 123.08

Si-MOSFET (Binary)

4t (PLNA) of[21] 6t (Conventional) of [20]

CNTFET (Ternary)

Ref. of [23]

‘0’ ‘1’ ‘2’ Avg. Std. Dev.

21.61 41.02 26.30 29.643 8.269

69.20 23.81 55.73 49.58 19.033

4.01 4.72 3.28 4.003 0.587

9.12 7.20 10.23 8.850 1.251

4.47 4.88 3.19 4.180 0.719

86.656 193.614 86.264 118.660 4.853

309.32 116.192 177.77 207.244 13.684

Ref. of [22]

‘0’ ‘1’ ‘2’ Avg. Std. Dev.

19.80 19.03 35.20 24.676 7.447

71.01 34.80 53.60 53.136 14.786

3.81 4.53 3.07 3.803 0.596

8.65 7.81 9.26 8.573 0.594

3.76 3.07 2.84 3.223 0.390

75.43 86.20 101.92 93.842 4.438

266.99 116.04 152.22 171.257 5.766

Proposed

‘0’ ‘1’ ‘2’ Avg. Std. Dev.

30.12 16.80 14.20 20.373 6.973

68.20 33.30 24.11 41.870 18.992

2.65 2.13 2.64 2.473 0.242

4.88 4.98 5.43 5.096 0.239

1.84 1.75 2.28 1.956 0.231

79.81 35.78 37.48 50.382 1.687

125.48 58.27 54.97 81.897 4.387

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Table 7 Density and performance (The change in pitch and the number of CNTs). Tech.

SRAM Cells

Density

Average performance

RSNM (mV)

Write Cycle

Read Cycle

Delay (ps)

Power (uW)

PDP (aJ)

Delay (ps)

Power dissipation (uW)

PDP (aJ)

Si-MOSFET (Binary)

4t (PLNA) of [21] 6t (Conventional) of[20]

N/A

15.33 11.3

1.47 1.93

22.53 21.81

11.6 9.4

1.13 1.24

13.11 11.65

58.7 72.3

CNTFET (Ternary)

Ref. of [23]

LD ND HD

44.19 22.08 19.23

0.0944 0.0768 0.0961

4.171 1.695 1.848

136.8 131.5 79.6

0.0272 0.0241 0.0388

3.721 3.169 3.088

129.44 129.25 127.28

Ref. of [22]

LD ND HD

36.73 18.22 17.44

0.1022 0.0789 0.0912

3.753 1.437 1.591

121.4 119.5 74.62

0.0135 0.0142 0.0194

1.638 1.696 1.447

126.34 126.93 123.13

Proposed

LD ND HD

12.57 8.62 7.12

0.0333 0.0202 0.0281

0.418 0.174 0.210

101.3 81.19 66.34

0.0093 0.0081 0.0154

0.942 0.657 1.021

153.77 153.43 151.06

Table 8 Process variation in the number of CNTs and its percent variability. Tech.

T-SRAM Cells

Average performance

RSNM (mV)

Write Cycle

CNTFET (Ternary)

Read Cycle

Delay (ps)

Power (uW)

PDP (aJ)

Delay (ps)

Power dissipation (uW)

PDP (aJ)

Ref. of [23] (LD)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ ) [%]

48.034 2.33 46.963 51.058 4.85

0.0914 0.0040 0.0961 0.0895 4.37

4.708 0.183 4.936 4.614 3.88

135.982 0.0261 135.951 136.001 0.019

0.0246 0.0007 0.0253 0.0240 2.84

3.489 0.009 3.500 3.495 0.257

129.942 0.0081 129.951 129.937 0.006

Ref. of [23] (ND)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ ) [%]

34.773 1.36 32.948 35.013 3.91

0.0784 0.0018 0.0802 0.0768 2.29

2.738 0.0831 2.710 2.851 3.03

131.163 0.0781 131.092 131.247 0.059

0.0241 0.0005 0.0237 0.0248 2.36

3.361 0.0119 3.347 3.370 0.354

129.214 0.0052 129.219 129.210 0.004

Ref. of [22] (LD)

Mean ( μ ) Std. Dev.(σ ) FF SS Variability (σ / μ ) [%]

47.002 2.47 45.623 50.117 5.255

0.0998 0.0004 0.1050 0.0974 4.609

4.726 0.186 4.982 4.701 3.93

121.012 0.0276 120.991 121.044 0.022

0.0148 0.0004 0.0151 0.0143 2.70

1.895 0.0107 1.907 1.886 0.564

126.063 0.0148 126.076 126.047 0.0117

Ref. of [22] (ND)

Mean ( μ ) Std. Dev.(σ ) FF SS Variability (σ / μ ) [%]

22.506 1.138 20.989 23.023 5.056

0.0722 0.00251 0.0741 0.0693 3.476

1.685 0.0461 1.704 1.623 2.735

119.343 0.0831 119.249 119.413 0.069

0.0133 0.0004 0.0137 0.0129 3.00

1.665 0.0149 1.683 1.655 0.894

126.756 0.0241 126.785 126.740 0.019

Proposed (LD)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ ) [%]

14.432 0.5801 13.920 15.042 4.019

0.0309 0.0009 0.0315 0.0299 2.912

0.4704 0.0171 0.4862 0.4683 3.51

101.226 0.0093 101.217 101.234 0.009

0.0092 0.0001 0.0093 0.0090 1.08

1.0299 0.0004 1.0301 1.0294 0.0388

153.383 0.0021 153.385 153.382 0.001

Proposed (ND)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ ) [%]

9.885 0.3120 9.494 10.061 3.156

0.0200 0.0002 0.0202 0.0198 1.00

0.2018 0.0057 0.1943 0.2036 2.82

81.014 0.0178 80.993 81.020 0.021

0.0084 0.0001 0.0085 0.0083 1.19

0.6810 0.0011 0.6823 0.6804 0.161

153.912 0.0020 153.914 153.910 0.001

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Table 9 RSNMs versus temperature variation and its variability percentage. Tech.

SRAM Cells

Temperature Variation RSNM (mV) @ Vdd=0.6 V

Si-MOSFET (Binary)

CNTFET (Ternary)

@ Vdd=0.9 V

@ Vdd=1.2 V

-20 °C

0 °C

70 °C

-20 °C

0 °C

70 °C

-20 °C

0 °C

70 °C

4 t (PLNA) of [21]

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ )[%]

86.12 5.78 90.03 78.94 6.71

67.25 4.31 70.04 61.82 6.41

48.34 2.89 51.01 45.23 5.99

87.36 4.03 92.00 84.04 4.61

72.83 2.86 74.24 69.03 3.93

59.92 2.23 61.01 56.95 3.73

49.37 2.66 52.87 47.98 5.39

38.54 1.83 40.14 36.49 4.77

29.89 1.30 31.00 28.41 4.60

6 t(Conventional) of [20]

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ )[%]

67.24 4.24 70.01 61.92 6.30

57.67 3.13 60.03 53.92 5.43

42.18 2.14 44.24 39.97 5.06

98.72 4.07 103.02 94.89 4.12

77.71 3.04 80.15 74.16 3.91

68.52 2.53 71.04 65.98 3.69

83.60 3.02 86.79 80.74 3.62

63.51 2.04 65.16 61.13 3.22

51.63 1.56 52.34 49.53 3.03

Ref. of [23] (LD)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ )[%]

84.58 0.044 84.60 84.52 0.052

113.96 0.047 114.02 113.93 0.041

114.66 0.050 114.70 114.60 0.044

146.26 0.045 146.30 146.21 0.030

129.59 0.038 129.61 129.54 0.029

120.02 0.04 120.06 119.98 0.033

135.57 0.055 135.62 135.51 0.040

128.66 0.04 128.70 128.62 0.031

123.67 0.04 123.71 123.63 0.032

Ref. of [23] (ND)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ )[%]

84.37 0.045 84.41 84.32 0.053

113.82 0.05 113.87 113.77 0.043

114.53 0.055 114.59 114.48 0.048

146.03 0.045 146.07 145.98 0.031

129.42 0.035 129.46 129.39 0.027

119.99 0.031 120.03 119.97 0.026

135.45 0.055 135.50 135.39 0.041

128.47 0.045 128.51 128.42 0.035

123.33 0.045 123.37 123.28 0.036

Ref. of [22] (LD)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ )[%]

66.97 0.041 67.00 66.92 0.061

74.21 0.035 74.25 74.18 0.047

86.44 0.04 86.48 86.40 0.046

142.47 0.05 142.52 142.42 0.035

131.99 0.045 132.03 131.94 0.034

126.24 0.045 126.29 126.20 0.035

128.46 0.065 128.53 128.40 0.050

115.00 0.044 115.06 114.98 0.038

106.03 0.04 106.07 105.99 0.037

Ref. of [22] (ND)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ ) [%]

66.53 0.045 66.58 66.49 0.068

74.03 0.041 74.06 73.98 0.055

86.24 0.045 86.28 86.19 0.052

142.23 0.055 142.29 142.18 0.038

131.97 0.041 132.00 131.92 0.031

126.04 0.047 126.07 125.98 0.037

128.13 0.076 128.19 128.04 0.059

114.98 0.045 115.02 114.93 0.039

105.96 0.041 106.01 105.93 0.038

Proposed (LD)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ ) [%]

86.96 0.04 87.00 86.92 0.045

103.10 0.03 103.13 103.07 0.029

124.00 0.048 124.06 123.97 0.038

154.97 0.04 155.01 154.93 0.025

150.16 0.03 150.19 150.13 0.019

142.00 0.025 142.03 141.98 0.018

140.14 0.0453 140.18 140.09 0.032

133.62 0.03 133.65 133.59 0.022

126.03 0.038 126.05 125.98 0.030

Proposed (ND)

Mean ( μ ) Std. Dev. (σ ) FF SS Variability (σ / μ )

86.71 0.04 86.75 86.67 0.046

103.02 0.0358 103.05 102.98 0.034

123.96 0.05 124.01 123.91 0.040

154.66 0.0418 154.71 154.63 0.027

150.02 0.035 150.05 149.98 0.023

141.97 0.031 142.01 141.95 0.022

140.04 0.050 140.09 139.99 0.035

133.47 0.035 133.50 133.43 0.026

126.03 0.0416 126.06 125.98 0.033

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It has been found that 30 CNTs/um (normal density (ND)) is the best value of density for the proposed T-SRAM cell. Also, the standard deviations and variability percentage to process variation in the number of CNTs have also been calculated. Simulation results have shown that proposed T-SRAM is very small sensitive to process variations, because of the unique design is intended to start at the lowest chip area and power dissipation of the proposed ternary memory cell. Finally, the RSNM parameter has been also analyzed when temperature variation occur and the results show that a presented T-SRAM cell has a smaller standard deviation and lower variability percentage for different ND and LD values, compared to other state-of-the art ternary memory cells. Thus, comparative analysis based on the Monte-Carlo simulation exhibits that the proposed TSRAM cell design is capable of process and temperature variations to a large extent.

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