New low power adders in Self Resetting Logic with Gate Diffusion Input Technique

JKSUES 129 3 April 2014 Journal of King Saud University – Engineering Sciences (2014) xxx, xxx–xxx

No. of Pages 17

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King Saud University

Journal of King Saud University – Engineering Sciences www.ksu.edu.sa www.sciencedirect.com

ORIGINAL ARTICLE

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New low power adders in Self Resetting Logic Q1 with Gate Diffusion Input Technique

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R. Uma a

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, Jebashini Ponnian b, P. Dhavachelvan

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Department of Computer Science, Pondicherry University, Puducherry, India Department of Electrical and Electronics Engineering, Universiti Infrastruktur Kuala Lumpur, Malaysia

Received 17 April 2013; accepted 24 March 2014

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KEYWORDS

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Self Resetting Logic; Gate Diffusion Input Technique; Dynamic logic; Full adders

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Abstract The objective vividly defines a new low-power and high-speed logic family; named Self Resetting Logic with Gate Diffusion Input (SRLGDI). This logic family resolves the issues in dynamic circuits like charge sharing, charge leakage, short circuit power dissipation, monotonicity requirement and low output voltage. In the proposed design structure of SRLGDI, the pull down tree is implemented with Gate Diffusion Input (GDI) with level restoration which apparently eliminated the conductance overlap between nMOS and pMOS devices, thereby reducing the short circuit power dissipation and providing High Output Voltage VoH. The output stage of SRLGDI has been incorporated with an inverter to produce both true and complementary output function. The Resistance Capacitance (RC) delay model has been proposed to obtain the total delay of the circuit during precharge and evaluation phases. Using SRLGDI, the primitive cells and 3 different full adder circuits were designed and simulated in a 0.250 lm Complementary Metal Oxide Semiconductor (CMOS) process technology. The simulated result demonstrates that the proposed SRLGDI logic family is superior in terms of speed and power consumption with respect to other logic families like Dynamic logic (DY), CMOS, Self Resetting CMOS (SRCMOS) and GDI.

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1. Introduction

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With continual technology scaling and improvements in lithography, the integrated system has become faster and thus

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* Corresponding author. Tel.: +91 04132274906. E-mail addresses: [email protected] (R. Uma), [email protected] (J. Ponnian), [email protected] (P. Dhavachelvan). Peer review under responsibility of King Saud University.

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it is employed in diverse real-time applications like mobile, digital signal processing, multimedia application and scientific computation. To support high-performance applications, proper choice of technology selection and topology for implementing various logic are the mandatory issues in designing low-power devices (Uma and Dhavachelven, 2012a). The Pass Transistor Logic (PTL) (Chatzigeorgiou and Nikolaidis, 2001) circuit offers better characteristics than static Q4 CMOS. PTL can implement most functions with fewer transistor counts, thus reducing the overall capacitance, which results in faster switching times and low power dissipation. The general issue pertaining to this PTL logic is voltage variation due to threshold drop owing to series resistance between input and output. These demerits were surmounted using

1018-3639 ª 2014 Production and hosting by Elsevier B.V. on behalf of King Saud University. http://dx.doi.org/10.1016/j.jksues.2014.03.006 Q1 Please cite this article in press as: Uma, R. et al., New low power adders in Self Resetting Logic with Gate Diffusion Input Technique. Journal of King Saud University – Engineering Sciences (2014), http://dx.doi.org/10.1016/j.jksues.2014.03.006

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Complementary Pass-Transistor Logic (CPL) and Swing Restored Pass-Transistor Logic (SRPL) (Yano et al., 1990; ParaQ5 meswar et al., 1994; Sasaki et al., 1996). However this logic produced larger short circuit currents, high transistor count to realize a simple gate and high wiring overhead due to the dual-rail signals. The GDI (Morgenshtein et al., 2002; Uma and Dhavachelvan., 2012b; Agrawal et al., 2009) is the lowest power design technique, which is suitable for designing of fast, low-power circuits, using reduced number of transistors (as compared to Transmission Gate and CMOS). The main drawbacks associated with GDI include: The bulk terminals are not properly biased thereby the circuit exhibits threshold drop and variation in Vt. Because of floating bulk, the cells can be implemented in SOI process which would increase the cost of fabrication. These demerits can be overcome by permanently connecting the bulk terminals pMOS to VDD and nMOS to GND which resolves the threshold variation. This configuration provides suitability for fabricating the logic cells in CMOS p-well and n-well process. Until today static CMOS has been the design style of choice for IC designers due to its robustness against voltage scaling and transistor sizing (high noise margins) and thus the operation is reliable at low voltages (Bisdounis et al., 1998). The disadvantage of CMOS is the substantial number of large pMOS transistors, resulting in high input loads and when the operating frequency increases the circuit dissipates more power. The propagation delay is slightly higher when compared to other logic family due to its larger node capacitances. Dynamic logic families are a good candidate for high speed and high performance circuit than the conventional static CMOS. Dynamic logic requires fewer transistors to implement a given logic function, less area and faster switching speed due to its reduced load capacitance (Yee and Sechen, 1996; Balsara and Steiss., 1996; Srivastava et al., 1998. However this circuit suffers from charge sharing, charge leakage, loss of noise immunity, timing problem due to clock input and feed through. These issues can be suppressed using an asynchronous dynamic circuit named Self Resetting CMOS (Kim, 2001). Asynchronous SRCMOS circuit operation has a separate precharge and evaluation phase which discharges the dynamic storage nodes to evaluate the desired logic function and then resetting these nodes back to their original charged state by a local feedback timing chain instead of a global clock. One of the advantages of self-resetting logic is that when the data present at the evaluation phase do not require dynamic node to discharge, which makes the precharge device inactive thereby reducing power (Litvin and Mourad, 2005; Uma, 2011. However this scheme endures from short circuit power and low output voltage due to nMOS pull down network producing conductance (direct path between) overlap between nMOS and pMOS. So the primary objective of this work focuses to resolve the problem incurred in the existing SRCMOS to support low-power and high-speed applications.

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2. Various dynamic logic

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The group of dynamic logic family offers good performance over traditional CMOS logic. The basic operation of dynamic logic is normally done with charging and selectively discharging capacitance. The logic operation needs two sub-cycles to

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R. Uma et al. complete (precharge and evaluation). During the precharge phase the clock signal charges the capacitance and during the evaluation phase the clock discharges the capacitance depending upon the condition of logic inputs. Various dynamic logic circuits are portrayed in Fig. 1. The logic circuit in Fig. 1(a) leads to contention problem during precharge and this problem is resolved by incorporating an nMOS stack at the bottom as shown in Fig. 1(b). The demerits associated with circuit as shown in Fig. 1(c) are loss of noise immunity and a serious restriction on the inputs of the gate (monotonicity problem) and only non-inverting logic can be implemented. These problems are surrogated using NORA CMOS circuit as shown in Fig. 1(d). But the problem with the logic is global clock presenting clock distribution grid and routing to dynamic gates that presents a problem to CAD tools and introduces issues of delay and skew into the circuit design process. Domino logic with charge-keeper circuit has been developed to combat this problem. The circuit realization is shown in Fig. 1(e), but the demerits of the circuit are: a slow clock slope leading to conductance overlap between nMOS and pMOS devices resulting in dc power dissipation and high sensitivity to noise. An asynchronous dynamic logic self-resetting CMOS (SRCMOS) circuit technique is shown in Fig. 1(f). In this logic no global clock is required and all the operation is controlled through the inverter chain between pMOS and output. The general issue related to this logic is static power consumption and if the width of the pulses must be controlled carefully or else there may be contention between nMOS and pMOS devices, or even worst, oscillations may occur.

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3. Proposed Self Resetting Logic with Gate Diffusion Input (SRLGDI)

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3.1. Problem statement

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Self-resetting circuitry automatically precharges themselves (i.e., reset themselves) after a prescribed delay by conditionally charging the dynamic nodes to evaluate the desired logic function using a local feedback timing chain instead of a global clock. Although this SRCMOS logic inherits lot of merits, it still suffers from static power dissipation due to the nMOS logic structure. As stated earlier, during precharge the nMOS stack is completely open and the output is fed back to the pMOS block to charge the capacitor Cy. During this period the nMOS transistors operate in cut-off region exhibiting subthreshold current. Moreover during the evaluation phase when the entire nMOS transistor in the n-block and Preset transistor is ON direct impedance path exists between the VDD of Preset transistor and nMOS block leading to static power dissipation. The width of the pulses must be controlled carefully or else there may be contention between nMOS and pMOS devices, or even worst, oscillations may occur. These demerits can be surmounted using GDI technique. The change done in the existing SRCMOS, instead of nMOS logic pull down tree, it is replaced as GDI logic with level restoration.

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3.2. Circuit topology of SRLGDI logic

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In the existing SRCMOS logic the pull-down tree is realized using nMOS block which consumes lot of static power.

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CLK

CLK

CLK

CLK Out

Out

Out I n p u t s

nMOS Logic

I n p u t s

(a)

Out

I n p u t s

nMOS Logic

I n p u t s

nMOS Logic

nMOS Logic

(c)

(b)

(d) Resetting transistor

Presetting transistor

CLK

Delay path

Out

I n p u t s

nMOS Logic

Cx

I n p u t s

Out

Y

CLK

nMOS Logic

Vout

Cy

(e) (f) Figure 1 Various dynamic circuits. (a) Unfooted dynamic logic, (b) footed dynamic logic, (c) conventional domino logic, (d) no race complementary metal oxide semiconductor (NORA CMOS), (e) domino logic with charge keepers and (f) self-resetting CMOS. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 174

To surrogate this issue the proposed SRLGDI has been replaced by GDI technique instead of nMOS block. A Gate Diffusion Technique Input (GDI) inherits the properties of Pass Transistor Logic and Complementary Metal Oxide Semiconductor. The basic structure realization resembles the CMOS inverter and the operational feature resembles the PTL logic. GDI basic cell and general block diagram are depicted in Fig. 2. The basic cell structure realization is similar to CMOS inverter containing series connected to pMOS and nMOS. Each GDI cell contains three inputs: VG is the shorted gate input common to pMOS and nMOS, VP is the drain/source Pdiffusion input at the pMOS terminal and VN is the source/ drain N-diffusion input at the nMOS terminal. Any Boolean function in GDI technique which is simple or complex is realized using this basic structure. Boolean function using GDI logic is a Y=Y network in which each control signal (variable) connects to a pair of series connected to pMOS and nMOS switches and the residue of each input can be GND, VDD or a true literal. Generally, a GDI logic circuit implements the following switching function: Y ¼ VP  T þ VN  T

ð1Þ

where T is implemented by pMOS and T is implemented by nMOS transistor. A logic expression in GDI can be implemented by applying the Shannon’s expansion theorem to decompose Y with respect to one of its input variable. For example to implement a 2-input OR logic gate, namely, Y = a + b, apply Shannon’s expansion theorem to decompose Y with respect to variable a, Y¼aþb¼abþa1

ð2Þ

where a is the control variable connected to the gate terminal of pMOS and nMOS (VG), the P-diffusion terminal is connected to input b and n-diffusion input is connected to VDD. The logic-1 signal at the input will be deteriorated by either pMOS or nMOS switch due to threshold drop. To obtain a full swing voltage a buffer should be added at the output terminal. In GDI technique both pMOS and nMOS are given with independent inputs so as to accommodate more logic function thereby minimizing transistor count. Whatever may be the input combination there is no chance that all the tran- Q6 sistors are ON at the same time. So the subthreshold power is very nominal in the proposed logic technique. The primitive cells of GDI are shown in Fig. 3. The circuit is realized with restoration buffer for full swing output.

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VP VP

T(PMOS)

VP

Y

Y Y

VG

VN VN

T(NMOS)

VG VG

VN

(a)

Control Variables

(c)

(b)

Figure 2 (a) Basic GDI cell using inverter structure (b) alternate basic GDI cell representation using PTL (c) general block diagram of GDI logic.

A A

B A

NANDOUT

ANDOUT

B XOROUT

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(b)

(a)

(c)

B

A

A OROUT

A

B

B NOROUT

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(e)

XNOROUT

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Figure 3 2-Input primitive cells in gate diffusion input with level restoration buffer. AND gate, (b) OR gate, (c) NAND gate, (d) NOR gate, (e) XOR gate and (f) XNOR gate.

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The general structure of Self Resetting Logic with Gate Diffusion Input technique (SRLGDI) is shown in Fig. 4. The structure consists of GDI block to realize any Boolean function. The transistors Ppreset and Preset are used to charge and discharge the dynamic node capacitor Cy during precharge

and evaluation phases. The noteworthy aspect of Preset transistor is that it acts as charge keeper to resolve the charge sharing problem which is the significant issue in dynamic circuit. The Preset transistor will pull the voltage level high even after the precharge phase to hold the output value high in the

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5 Resetting transistor

Presetting transistor

CLK

I n p u t s

Delay path

Preset Ppreset

Output inverter to provide both true and complementary output

Y INV1

GDI block

Vout

Cy

INV2

Dynamic node

GDI block with level restoration buffer

Figure 4 General circuit topology of self resetting gate diffusion input. The nMOS pull down network in the conventional scheme is replaced with gate diffusion input block with level restoration and output inverter offers true and complementary output.

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existence of charge sharing. The output is fed back to the precharge control input and, after a specified time delay, the pullup is reactivated. The inverter INV1 and the internal inverter in the GDI block completely eliminate the contention problem and provide compatibility to cascade the output from one node to another node. The output of the gate provides a pulse if the logic function becomes true. This output is buffered and it is connected to pMOS structure to precharge. The delay line is implemented as a series of inverters. The signals that propagate through these circuits are pulses. The inverter (INV2) present at the output side provides both true and complementary output and also it acts as level restoration circuit to cascade more number of circuits without logical degradation. By using a buffered form of input, the loading (input) is kept almost low when compared to normal dynamic logic while local generation of the reset assures that it is properly timed and occurs only when required. This modification produces less power consumption and high VOH, while apparently maintaining the logical functionality.

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3.3. Operational feature of SRLGDI logic

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The general behaviour of SRLGDI logic can be portrayed as an ability of a logic block to reset its output pulse after it has been asserted. The reset signal is often generated within the block based on the output pulse. The circuit operation is defined in two phases as precharge and evaluation. The switching behaviour is elucidated in Fig. 5, where Ppreset and Preset define the pMOS precharge and reset transistor. During the precharge phase CLK = 0 in Fig. 5a, the GDI block is open, the transistor Ppreset is ON so a direct impedance path exists between node y and VDD thereby charging the capacitance Cy to VDD. The output node Vout is discharged and makes the reset voltage Vreset to be ‘0’ insuring that Preset is cut-off during this time. For the evaluation phase CLK = 1 as shown in Fig. 5b, the GDI logic is closed, the transistor Ppreset is OFF, in this case Vy fi 0 V and the output capacitance charges to give an output voltage Vout fi VDD. This voltage is fed through the delay path and produces Vreset fi VDD and the transistor Preset is active after the specified delay path. The Preset transistor recharges the node capacitor

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Cy back up to a voltage of Vy fi VDD. This action resets the output voltage to its original precharge value of Vout fi 0 V. The timing diagram of SRLGDI is shown in Fig. 6.

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3.4. Primitive cell design in SRLGDI logic

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Basic SRLGDI logic gates (AND, OR, NAND, NOR, XOR, and XNOR) are shown in Fig. 7. Each gate consists of a GDI logic tree, half-latch circuits, Preset device, and a diagnostic (static_evaluate) weak pMOS (Preset) device. The GDI tree is a parallel/series network of nMOS and pMOS devices between ground and the inputs to the output inverters (the dynamic storage nodes). The GDI network is incorporated with level restoration circuit for full swing output. The delay path is limited with one inverter in order to have smaller pulse width to avoid the contention problem between the GDI network and the dynamic nodes. This structure produces equal fall and rise delay. The delay line should be implemented with odd number of inverters in order to ensure the correct transition (ON and OFF) for Preset transistor charging and discharging the dynamic capacitor Cy. The inverter at the output node produces both true and complementary outputs. The illustration and the working principle of SRLGDI AND cell are shown in Fig. 8. The GDI block is constructed using (P1, P2, P3) and (N1, N2, N3) pMOS and nMOS transistors which are used to realize the function A.B. The transistors P4 and N4 which are connected between the dynamic and output node eliminate the contention and cascading problem. The delay path is formed by the transistors P5 and N5 which control the ON/OFF transition of Preset charge keeper circuit. The output inverter constructed using the transistors P6 and N6 provides the true output of the function A.B. During the precharge phase (CLK = 0) the Ppreset transistor is ON, which makes the dynamic node to be high and in turn it makes N4 to be ON and P4 to be OFF. The output of the dynamic inverter is low, making the transistors P5 ON and N5 OFF resulting in high output in turn it ceases the conduction of Preset transistor. During the precharge phase there will not be any conduction path between GDI block and dynamic node. The gate level representation of SRLGDI AND gate during the precharge phase is portrayed in Fig. 8a.

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Ppreset

Vreset =0V

Preset

Delay path Preset

Ppreset CLK=’0’

ON

OFF

ON

OFF

ON

CLK=1

OFF OFF

Y

After delay Vreset=VDD→0V

OFF Y Cy

Open

OFF

ON

ON

ON

Output OFF

Delay path

Output

Vout=0V

ON

Vy=VDD

Vy=VDD→0V

Open

GDI block

Cy

GDI block OFF

Vout →0V→VDD→0V After delay

ON

(b)

(a)

Figure 5 Switching behaviour of self-resetting complementary metal oxide semiconductor (SRCMOS). (a) Switching characteristics during precharge and (b) switching characteristics during evaluation phase.

Vreset Vy

Vout

Volts Precharge

Evaluate

Precharge

Evaluate

Precharge

Evaluate

Precharge

Evaluate

CLK

Data1

Data2 Time (ns)

Figure 6 phases.

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Timing diagram of self-resetting complementary metal oxide semiconductor (SRLGDI) during precharge and evaluation

During the evaluation phase (CLK = 1) the Ppreset transistor is OFF, so the dynamic node gets discharged due to the non-existence of path between Ppreset transistor, which make the transistors P4 ON and N4 OFF exhibiting high logical level in turn the delay inverter (P5 is OFF and N5 is ON) is OFF thereby the Preset transistor becomes ON and holds the dynamic node high. Throughout this period, for the inputs ‘‘00’’, ‘‘01’’ and ‘‘10’’ there will not be any conduction path existing between GDI block and dynamic node which makes the output to remain at a low logical level. The switching behaviour during the evaluation phase for the inputs ‘‘00’’, ‘‘01’’ and ‘‘11’’ is illustrated in Fig. 8b. For the input ‘‘11’’ the output of GDI block is high which connects the dynamic node to output node resulting Q7 in a high logical level. During this time, the inverter between dynamic node and output node is low; in turn it makes the

delay inverter ON and due to its consequence Preset transistor is automatically reset to its initial condition. The switching behaviour during the input transition ‘‘11’’ is elucidated in Fig. 8c. The input/output wave form of SRLGDI AND gate is shown in Fig. 9. Only for CLK = 1 and input A = 1 and B = 1, the output is high and for the remaining cases the output remains low.

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3.5. RC delay model for SRLGDI logic

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SRLGDI supports pulse-mode operation; therefore it is necessary to formulate the static timing analysis to find the rising and falling transition. To ensure the correct operation of pulse based circuit, the pulses arriving at different inputs must be active for a specified period of time. For SRLGDI the gate will generate an output pulse only if the inputs are valid or the

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CLK CLK

NANDOUT

A ANDOUT

B

A

(b)

(a) B

CLK CLK B NOROUT

A

OROUT

B

A

(d)

(c)

CLK CLK

XNOROUT XOROUT A B

A B

(e)

(f)

Figure 7 2-Input primitive cells in Self Resetting Logic with gate diffusion input level restoration buffer. (a) AND gate, (b) OR gate, (c) NAND gate, (d) NOR gate, (e) XOR gate and (f) XNOR gate.

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output will remain at zero. The timing parameters used in the derivation of rise and fall time are: Rreset: Resistance of reset transistor Preset Rpreset: Resistance of preset transistor Ppreset RGDI: Resistance along the GDI block during evaluation phase Rinv: Resistance of inverter at output side Rdelay: Resistance along the delay path Cy: Dynamic node capacitance Cout: Output capacitance tdf: Forward delay in the inverter path [delay path] tgd: Delay due to the ON and OFF transition of GDI block tpreset: Delay during precharge period treset: Delay during evaluation period Wp: Denotes width of the output pulse td: Total delay

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behaviour of GDI block and the output inverter. During the evaluation phase a combination of active high inputs creates a conduction path between the bottom of the GDI block tree and ground. This forces the node at the top of the logic tree to its active low state and switches the output inverter to create an active high output signal. The active high output causes the reset transistor to be ON and conditionally discharge the dynamic storage nodes to evaluate the desired logic function and thus resetting these nodes back to their original charged state due to the delay inverter chain. During precharge: tpreset ¼ Rpreset  Cy During evaluation when grounding VDD: Rreset RGDI þ Req ðRreset þ RGDI Þ treset ¼ ðCy þ Cout Þ Rreset þ RGDI

ð3Þ

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ð4Þ

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The RC switching delay during precharge and evaluation phases is shown in Fig. 10. During precharge the Ppreset transistor is ON and makes the dynamic capacitor to charge to VDD. Thus the output pulse will be zero due to open circuit

Rinv  Rdelay where Req ¼ Rinv þ Rdelay

ð5Þ

To generalize Eq. (4)

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Figure 8

Operational characteristics of SRLGDI AND gate (a) switching behaviour during precharge phase (b) switching behaviour

Q12 during evaluation phase for the inputs ‘‘00’’, ‘‘01’’ and ‘‘11’’ (c) switching behaviour during the input transition ‘‘11’’. 364 365 366 368

treset ¼ Wp þ tdf þ tgd

ð6Þ

So the total delay of SRLGDI circuit is td ¼

tpreset þ treset 2

ð7Þ

The width of the output pulse Wp depends strongly on the characteristics of the output stage of the gate. So the delay of SRLGDI gate depends on the width of the output pulse, delay of the feedback inverter chain and delay of the GDI block.

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Input/output simulation waveform of SRLGDI AND gate for the input voltage of 5 V.

4. General virtues of the proposed SRLGDI logic The subsequent topics explain the general merits of the proposed SRLGDI logic with the existing dynamic SRCMOS logic in terms of subthreshold leakage, charge sharing and monotonicity requirements. 4.1. Reduction of subthreshold current in SRLGDI The proposed structure realized using GDI technique will reduce the subthreshold leakage during precharge and evaluation phases. As in the case of nMOS structure the subthreshold leakage is predominant due to ON state of nMOS and pMOS stack. Nevertheless in the case of the proposed SRLGDI there is no chance that all the transistors are ON at the same time whatever may be the input combination. To elucidate this condition the switching activity of basic GDI cell is presented. Consider the case when the control input at terminal VG is low, P-diffusion input VP is high and N-diffusion input VN is low, which makes the pMOS device to enter into linear region and the device is set to be in ON state, while nMOS enters into cut-off region and the device is OFF which produces direct path between VP and output (refer Fig. 2). Consequently the output of the multiplexer will be high. The switching characteristic of basic GDI cell is shown in Fig. 11. The transistor behaviour for various input combinations along with the pMOS and nMOS device characteristics is listed in Table 1. The subthreshold current is high for nMOS device. During the precharge phase when the entire nMOS device is OFF the effect of leakage current between the nMOS stack to VDD of pMOS stack is predominant. The leakage current for SRCMOS and the proposed SRLGDI is calculated for various Vgs using Hspice and its result is depicted in Fig. 12. The graph is plotted against gate-source voltage (Vgs) and subthreshold

current (Ids). Fig. 12(a) shows the subthreshold leakage of series nMOS stack with properly biased substrate input. Similarly Fig. 12(b) presents the subthreshold leakage of series GDI stack with different substrate (Vb) inputs. It is noticed that the subthreshold leakage is 4.0 mA for Vgs nearly equal to 0.8 which is very high when compared to GDI block with the same applied condition having 2.0 mA. This shows that the proposed SRLGDI consumes nominal leakage current when compared Q8 to the existing dynamic SRCMOS logic (see Fig. 13).

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4.2. Monotonicity requirement

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A fundamental difficulty with dynamic circuits is a loss of noise immunity and a serious timing restriction on the inputs of the gate. During the evaluation phase the input signal must never change to validate the correct operation of logic function, which is addressed as the monotonicity problem. In the proposed logic the inverter between the dynamic node and the output node will completely eliminate the timing restriction. Consider the case, when the CLK = 0 the output voltage of the dynamic gate is elevated by the Ppreset transistor, thereby the output of the inverter will necessarily be low. Therefore, during evaluation, the signal can only remain low or change from low to high, so the undesirable high to low transition is prevented. During cascading one circuit to another circuit the timing restriction is nullified due to the presence of a reset circuit (the delay path) which commands the precharge transistor to a ready state so that it can accept input signals and perform the logical operation correctly.

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4.3. Reduction of charge leakage in SRLGDI

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The main limitation in the existing dynamic logic is the potential logic upset due to the charge sharing effects. This charge sharing problem occurs internally due to the charge inversion

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Vreset =0V

Ppreset

Clk=’0’

Preset

OFF

ON

OFF

ON

Delay path

Y

ON

OFF

Rpreset Output

Cy OFF

Vout=0V

Vy=VDD

Open GDI block

Cy OFF

(a)

After delay Vreset=VDD→0V

Preset

Ppreset Clk=’1’

OFF OFF

ON

Delay path OFF

ON

Rreset Y

Rdelay

ON

Rinv Output

ON

Cy Vy=VDD→0V

close

Vout →0V→VDD→0V After delay

GDI-block

RGDI

Cy

Cout

ON

(b) Q13 436 437 438 439 440 441 442

443 444 445 446 447 448 449 450 451 452 453 454 455 456

Figure 10

RC delay model for self-resetting logic with gate diffusion input. (a) During precharge.

under the gate oxide region and cascading the load and driver connected between two dynamic circuits. In the proposed SRLGDI the charge sharing problem is minimized using the pMOS transistor Preset. After precharge, the Preset pMOS device is ON and it continues to pull up the node even after the precharge phase is complete. The other added features of the proposed SRLGDI logic are:  The signals that propagate through these circuits are pulses to ensure the correct operation when it is cascaded with multiple devices.  When data present at evaluation do not require dynamic node to discharge, the precharge device is not active hence reducing power.  The stringent timing constraints encountered in pulse mode circuits can be relaxed without affecting circuit robustness.  By using a buffered form of the input, the input loading is kept almost as low as in the normal dynamic logic while local generation of the reset assures that it is properly timed and occurs only when needed.  Fast cycle time and minimum delay are observed when compared to dynamic SRCMOS logic.

 No global clock is required thus it reduces the synchronization problem.

457 458 459

To fulfil the requirement of monotonicity, charge sharing and cascading effects, multiple inverters, delay path inverters and level restoration circuit have been incorporated which slightly increase the total gate count of the circuit, which is the only deficit of the proposed SRLGDI logic.

460

5. Simulated results

465

The proposed SRLGDI primitives are simulated using Tanner EDA with BSIM3v3 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V. All the primitive gates are simulated with same setup. The test bed is supplied with a nominal voltage of 5 V in steps of 0.2 V and it is invoked with the technology library file Generic 025. To establish an unbiased testing environment, the simulations have been carried out using a comprehensive input signal pattern, which covers every possible transition for a logic gate. All the primitive structures are implemented in CMOS, Dynamic logic (DY), SRCMOS and SRLGDI with the same

466

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0

11

ON

Y

0

OFF

1 OFF Y

1

Y

ON

ON

0

0 Figure 11

OFF

1

1

0

1 OFF

OFF 1

Y

0

OFF

0

0

ON Y

0

OFF

0

1 ON

ON Y

0

Table 1

0

1

Y

1

OFF Y

1

ON

1

ON

1

Switching activity of GDI cell.

Operational characteristics of basic GDI cell.

Input VG

Input VN

Input VP

PMOS device characteristics

NMOS device characteristics

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Linear: VP  VTP < Vout < VDD Linear: VP  VTP < Vout < VDD Linear: VP  VTP < Vout < VDD Linear: VP  VTP < Vout < VDD Cut-off: Vp > VDD + VTP Cut-off: Vp > VDD + VTP Cut-off: Vp > VDD + VTP Cut-off: Vp > VDD + VTP

Cut-off: VN < VTN Cut-off: VN < VTN Cut-off: VN < VTN Cut-off: VN < VTN Linear:0 < Vout < VN  VTN Linear:0 < Vout < VN  VTN Linear:0 < Vout < VN  VTN Linear:0 < Vout < VN  VTN

Figure 12

Subthreshold leakage current (a) nMOS stack (b) pMOS stack.

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Logic diagram

Transistor Representation

CLK

A B

A D D E R 1

SUM

B

A

C

A B

CARRY CLK C

B

CARRY

A B SUM C

CLK

A D D E R 2

CLK B

SUM

A A B SUM A B

C A B

C CARR Y

B

CLK

CARRY

A B

C

A D D E R 3

CLK SUM A

SUM B

B

A

C A B

C CLK

CARRY A

CARRY

C

A B

Figure 13 477 478 479 480

Proposed full adders in SRLGDI.

set up, providing the same temperature, biasing, aspect ratio and testing condition. All transitions from one input combination to another have been tested, and the delay at each transition has been

measured. The average has been reported as the cell delay. The power consumption is also measured for Q9 these input patterns and its average power has been reported in 2. Table 2 shows the performance of SRLGDI

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Table 2 Performance of self-resetting logic with gate diffusion input primitive cells with other logic families. (Delay in ns, Power (PWR) in lW, Transistor count #tr). Library

AND OR NAND NOR XOR XNOR

CMOS

DY

SRCMOS

GDI

Proposed SRLGDI

Delay

PWR

#tr

Delay

PWR

#tr

Delay

PWR

#tr

Delay

PWR

#tr

Delay

PWR

#tr

20.14 10.03 19.98 10.04 5.211 5.054

52.45 108.28 140.12 89.69 96.74 98.23

6 6 4 4 14 14

19.97 8.14 17.45 8.65 4.043 4.456

50.45 99.28 120.12 82.69 98.74 102.23

6 6 10 10 12 12

19.62 10.15 20.02 10.03 4.567 4.86

49.45 96.28 110.12 79.56 97.74 103.23

8 8 12 12 14 14

20.38 10.40 19.95 10.13 5.258 5.18

42.45 88.28 90.12 69.69 89.74 81.23

6 6 8 8 8 8

18.89 9.31 18.23 9.623 4.983 4.99

47.69 94.38 96.14 78.69 95.74 96.63

14 14 16 16 16 16

Complementary Metal Oxide Semiconductor (CMOS), Dynamic logic (DY), Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS), Gate Diffusion Input (GDI) and proposed Self Resetting Logic with Gate Diffusion Input (SRLGDI).

0

0

0

1

0

1

0

1

0

CARRY

SUM

0

1

0

0

0

0

0

1

0

CLK

Volts from 0v to 5V

0

0

1

0

0

0

1

0

1

1

1

0

0

1

0

0

1

1 A

B

0

1

0

0

0

0

1

0

1

0

0

1

0

1

0

1

1

1 C

Time in (ns)

Figure 14 Input/output transition of self-resetting logic with gate diffusion input adder1 with different inputs operating at 100 MHz clock frequency, time in ns and Voltage ranging from 0 V to 5 V.

486

with other logic like CMOS, GDI, SRCMOS and Dynamic logic.

487

6. Proposed full adders

485

488 489 490

Addition is an indispensable operation for any high speed digital system, digital signal processing or control system. The primary issues in the design of adder cell are area, delay

and power dissipation. Several adder topologies have been reported by Uma and Dhavachelven (2012a,b,c), Shubin (2011), Aguirrre-Hernandez (2011), Mirzaee et al. (2010), Ghadiry et al. (2010) and Navi et al. (2008). The proposed adder circuit realizations are shown in Fig 8. Adder1 is implemented with XOR and multiplexer. The sum logic is evaluated by XOR gate and carry logic is realized using MUX. Adder2 is designed using XNOR and MUX with sum realization using XNOR and MUX, while carry logic is struc-

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Table 3 Performance comparison of the proposed adders with different logic families (Delay in ns, Power in lW, Transistor count #tr, Power–delay product (PDP) lW · ns in fW-s). Present study Adder1

Adder2

Adder3

Delay PWR #tr PDP Delay PWR #tr PDP Delay PWR #tr PDP

SRLGDI

GDI

CMOS

DY

SRCMOS

22.2 200.1 34 4442.22 29.1 212.4 44 6180.84 23.3 235.4 34 5484.82

33.1 188.9 18 6252.59 36.5 202.6 22 7394.9 36.2 210.9 18 7634.58

35.4 402.2 38 14237.88 40.3 531.4 48 21415.42 38.8 545.3 38 21157.64

28.2 350.2 40 9875.64 30.2 459.7 46 13882.94 26.3 434.2 40 11419.46

27.63 323.4 30 8935.542 32.13 409.8 38 13166.87 25.56 412.5 30 10543.5

Self Resetting Logic With Gate Diffusion Input (SRLGDI), Gate Diffusion Input (GDI), Complementary Metal Oxide Semiconductor (CMOS), Dynamic logic (DY) and Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS).

Table 4 Performance comparison of the proposed and existing adders (Delay in ns, Power in lW, Transistor count #tr, Power–delay product (PDP) lW · ns in fW-s. Full adders

Delay

Power

#tr

PDP

Present study (adder1) Present study (adder2) Present study (adder3) Existing circuit Uma and Dhavachelvan Uma and Dhavachelven (2012a) Existing circuit Uma and Dhavachelvan (2012b) Existing circuit Uma and Dhavachelvan (2012c) Existing circuit Shubin (2011) Existing circuit Aguirrre-Hernandez (2011) Existing circuit Mirzaee et al. (2010) Existing circuit Ghadiry et al. (2010) Existing circuit Navi et al. (2008)

22.2 29.1 23.3 36.34

200.12 212.45 235.46 196.78

34 44 34 18

4442.664 6182.295 5486.218 7150.985

35.67 32.31 32.87 37.2 40.23 39.78 38.45

203.67 194.35 275.98 315.67 215.13 234.56 387.65

18 14 36 26 15 26 16

7264.909 6279.449 9071.463 11742.92 8654.68 9330.797 14905.14

tured using MUX. Adder3 is proposed with XNOR and MUX with sum evaluation using XNOR and carry using MUX. To 502 test the performance of the proposed and existing adders, de503 tailed comparisons were performed. The simulations were 504 run with the tanner software. All the schematics are based 505 on TSMC 0.250 lm technology with supply voltage ranging 506 from 1.2 V to 5 V in steps of 0.2 V. All the full adders are sim507 ulated with multiple design corners (TT, FF, FS, and SS) to 508 verify that operation across variations in device characteristics 509 and environment. The W/L ratios of both nMOS and pMOS 510 transistors are taken as 2.5/0.25 lm. The circuits are simulated 511Q10 with a 100 MHz clock frequency. Since the operation of the 512 proposed SRLGDI adders is based on dynamic logic charac513 teristics, the input should be changed in the precharge phase 514 and the results are obtained during the evaluation phase. 515 The delay parameter is calculated from all the transitions from 516 an input combination to another, and the delay at each transi517 tion has been measured from the time the clock signal reaches 518 50% of the supply level. 519 Power delay product (PDP) has been calculated by taking 520 the product term of delay and average power consumption. 521 The input/output waveform generated for SRLGDI adder1 522 with clock frequency of 100 MHz is shown in Fig 14. The 523 waveform indicates the complete transition characteristics of 524 SRLGDI adder with the three inputs A, B and C having the 500 501

bit patterns (000, 001, 010, 011, 100, 101, 110 and 111). The input patterns are changed only during the precharge phase. The output shows the full swing voltage because of the level restoration circuit in GDI network. In this study the performance evaluation of the proposed adders is compared with the different logic families and the existing adders. Table 3 presents the performance of adder1, adder2, and adder3 with different logic families in terms of delay, power and transistor count. Table 4 shows the performance comparison of the proposed and existing adders.

525

7. Discussion

535

A new family of self-resetting logic (SRL) cells implemented with GDI technique is presented. The proposed primitive cells have been tested against its existing techniques in terms of delay, power and PDP which are report in Table 2. The comparison result is shown in Fig. 15. The proposed SRLGDI primitive cells and the adder cells perform better than different logic and existing counterparts. Table 5 depicts the percentage of improvement in delay, power and PDP of adder1, adder2, and adder3 with respect to different logic. The analysis of the proposed study illustrates progressive improvements with CMOS logic in terms of delay, power and PDP when compared with other logic families. The negative sign in the table

536

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Delay of Primive cell in various logic DY

SRCMOS

GDI

proposedSRLGDI

AND

OR

NAND

NOR

5.054 4.456 4.86 5.18 4.99

5.211 4.043 4.567 5.258 4.983

10.04 8.65 10.03 10.13 9.623

10.03 8.14 10.15 10.4 9.31

19.98 17.45 20.02 19.95 18.23

20.14 19.97 19.62 20.38 18.89

CMOS

XOR

XNOR

(a) Power consumpon of primive cell

AND

OR

NAND

NOR

98.23 102.23 103.23 81.23 96.63

proposedSRLGDI 96.74 98.74 97.74 89.74 95.74

GDI

89.69 82.69 79.56 69.69 78.69

SRCMOS

140.12 120.12 110.12 90.12 96.14

DY

108.28 99.28 96.28 88.28 94.38

52.45 50.45 49.45 42.45 47.69

CMOS

XOR

XNOR

(b) Power-Delay Product of Primve Cell

AND

OR

NAND

NOR

XOR

496.4 555.5 501.6 420.7 482.1

proposedSRLGDI

504.1 499.2 486.3 471.8 477

GDI

900.4 790.2 797.9 705.9 757.2

SRCMOS

2799.5 2096 2204.6 1797.8 1752.6

DY

1086 892.1 977.2 918.1 878.6

1056.3 1007.4 970.2 865.1 900.8

CMOS

XNOR

(c) Figure 15

Table 5

Performance of primitive cell of SRLGDI logic (a) delay performance (b) power comparison (c) Power-delay product.

Percentage of improvement in delay, power and PDP of adder1, adder2, and adder3 with respect to different logic.

Present study

Percentage of improvement in delay, power and PDP with respect to different logic GDI

Adder1 Adder2 Adder3

CMOS

DY

SRMOS

Delay

Power

PDP

Delay

Power

PDP

Delay

Power

PDP

Delay

Power

PDP

32.93 20.27 35.64

5.929 4.837 11.62

28.9 16.4 28.1

37.28 27.79 39.94

50.249 60.03 56.831

68.7 71.1 74.07

21.28 3.642 11.41

42.86 53.8 45.79

55.01 55.41 51.96

19.65 9.43 8.84

38.13 48.17 42.93

50.28 53.05 47.97

Self-Resetting Logic with Gate Diffusion Input (SRLGDI), Gate Diffusion Input (GDI), Complementary Metal Oxide Semiconductor (CMOS), Dynamic logic (DY) and Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS).

548 549 550 551

indicates an increase in power consumption factor. The overall delay improvement is 32.45%, achieved with different logic families. Expect for GDI logic the proposed adders have nearly 60% of power improvement. The PDP improvement of the

proposed adders with different logic families is shown in Fig 16. Table 6 elucidates the performance improvement for PDP of the proposed SRLGDI adders with the existing adders. In this study it is examined that the PDP improvement

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Performance improvement of PDP with different logic families

% PDP

80 60 Present study adder1

40

Present study adder2

20

Present study adder3

0 GDI

CMOS

DY

SRCMOS

Different logic families

Figure 16 Performance improvement of PDP with Gate Diffusion Input (GDI), Complementary Metal Oxide Semiconductor (CMOS), dynamic logic (DY) and Self-resetting (SRCMOS).

Table 6

Percentage of improvement in power delay product (PDP) of adder1, adder2, and adder3 with respect to existing adders.

Existing adders

Present study adder1

Present study adder2

Present study adder3

% PDP improved

% PDP improved

% PDP improved

Uma and Dhavachelvan (2012a) Uma and Dhavachelvan (2012b) Uma and Dhavachelvan (2012c) Shubin (2011) Aguirrre-Hernandez (2011) Mirzaee et al. (2010) Ghadiry et al. (2010) Navi et al. (2008)

37.87 38.85 29.25 51.03 62.17 48.67 52.39 70.19

13.55 14.9 15.47 31.85 47.35 28.57 33.74 58.52

23.28 24.48 12.63 39.52 53.28 36.61 41.2 63.19

PDP in %

Percentage of improvement in PDP for exisng adders 80 70 60 50 40 30 20 10 0

Present study adder1 Present study adder2 Present study adder3

Exisitng adders

Figure 17

Performance improvement of Power Delay Product (PDP) between present study and existing adders.

564

of adder1 is well enunciated when compared to the proposed adder2 and adder3. The performance improvement in PDP in the proposed adders with existing adders is illustrated in Fig. 17. It is recognized that for all the proposed adders the PDP is much better in Navi et al. (2008); when compared to the other existing adders. To consolidate this study adder1 designed with XOR and MUX produces significant improvements in terms delay, power and PDP with its existing counterparts.

565

8. Conclusion

556 557 558 559 560 561 562 563

566 567

The proposed structure does not require global clock therefore the SRLGDI structure will not encounter into any clock distri-

bution problem. The transistor incorporated between dynamic node acts as charge keeper circuit to pull the output node high in order to maintain the signal integrity. The loading effect and the monotonicity requirement have been surrogated by the proposed SRLGDI logic. The performance of these proposed primitive cells in SRLGDI presents 62% of power reduction when compared to other logic families with a slight increase in transistor count. About 38% of delay reduction has been achieved using this SRLGDI logic. Three adders have been proposed and its performance has been evaluated with different logic families and existing adders. The proposed SRLGDI adder cell performs better than different logic and existing counterparts. While comparing the three adders, adder1 designed with XOR and MUX presents low power and less de-

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lay when compared to adder1 and adder2. On the whole about 32% of improvement in delay, 58% of power and 60% of PDP have been achieved using this proposed SRLGDI logic. To fulfil the requirement of monotonicity, charge sharing and cascading effects, multiple inverters, delay path inverters and level restoration circuit have been incorporated which slightly increase the total gate count of the circuit, which is the only deficit of the proposed SRLGDI logic.

590

9. Uncited reference

582 583 584 585 586 587 588

591Q11

Yano et al. (1996).

592

References

593

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