Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits

Int. J. Electron. Commun. (AEÜ) 100 (2019) 32–38

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Short communication

Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits Fabian Khateb a,b,⇑, Tomasz Kulej c, Harikrishna Veldandi d, Winai Jaikla e a

Department of Microelectronics, Brno University of Technology, Technická 10, Brno, Czech Republic Faculty of Biomedical Engineering, Czech Technical University in Prague, nám. Sítná 3105, Kladno, Czech Republic c Department of Electrical Engineering, Cze˛stochowa University of Technology, 42-201 Cze˛stochowa, Poland d Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, India e Department of Engineering Education, Faculty of Industrial Education and Technology, King Mongkut’s Institute of Technology Ladkrabang, Bangkok 10520, Thailand b

a r t i c l e

i n f o

Article history: Received 26 September 2018 Accepted 29 December 2018

Keywords: Bulk-driven Quasi-floating-gate Low-voltage low-power CMOS

a b s t r a c t This brief presents the first experimental results of the multiple-input bulk-driven quasi-floating-gate (MI-BD-QFG) MOS transistor (MOST) which is suitable for low-voltage (LV) low-power (LP) integrated circuits design. The MI-BD-QFG MOST is an extension to the principle of the bulk-driven quasifloating-gate (BD-QFG) MOST. However, unlike the BD-QFG the MI-BD-QFG MOST offers multipleinput that simplifies specific CMOS topologies and reduce their power consumption. To confirm the advantages of the MI-BD-QFG MOST a Differential Difference Current Conveyor (DDCC) with very simple CMOS structure has been designed and fabricated in a standard n-well 0.18 mm CMOS process from TSMC with total chip area 350 mm
78 mm. The fabricated circuit uses a 0.5 V power supply, consumes 1.7 mW power and offers near rail-to-rail input common mode range. Ó 2018 Elsevier GmbH. All rights reserved.

1. Introduction Low-voltage (LV) low-power (LP) system-on-chip is required in portable electronics and biomedical applications to extend the battery lifetime. In the last decade, a lot of efforts have been made in exploring alternative materials for the silicon MOST as silicon transistor is approaching its physical limit [1,2]. The continuous scaling of the widely used CMOS technologies results in increasing the density of integration and enhanced digital circuits performances. However, due to the fact that the channel length of the MOS transistor is scaled down into submicrons and the gate-oxide thickness becomes only several nanometers thick, the reduction of the supply voltage becomes necessary to ensure device reliability and prevent chip overheating. Extremely voltage supply scaling becomes an effective lever to reduce power consumption of the integrated circuit design. However, operation at reduced voltage supplied degrades dramatically the speed of digital circuits; therefore, digital designers keep striving to reduce the circuits delay so that the clock constraint remains met when the voltage supply drops [3–5]. For analog circuits the voltage scaling also induces circuit performance degradation where the main obstacle is the rather ⇑ Corresponding author. E-mail addresses: [email protected] (F. Khateb), [email protected] (T. Kulej), [email protected] (H. Veldandi), [email protected] (W. Jaikla). https://doi.org/10.1016/j.aeue.2018.12.023 1434-8411/Ó 2018 Elsevier GmbH. All rights reserved.

high threshold voltage (VTH) compared to the voltage supply (VDD) of a given CMOS technology. Therefore, recently several design techniques have been developed to build LV LP CMOS structures [6–19]. The most interesting techniques are the floating-gate (FG), quasi-floating-gate (QFG) and bulk-driven (BD) [6]. These techniques are considered as non-conventional and have their own pros and cons [6]. The main drawbacks of the FG MOST is the large capacitors area occupied on chip, reduction of the effective transconductance and output impedance in comparison to the conventional gate-driven (GD) MOST and also the FG MOST cannot process DC signals. The QFG MOST offers smaller occupied chip area and relatively higher effective transconductance than the FG MOST but it is still smaller than the transconductance of GD MOST. The QFG MOST has lower effective output impedance than the FG and GD MOST and the QFG MOST as well cannot process DC signals. However, both the FG and QFG MOST offers the possibility of multiple-input that simplify specific structures. Further, the threshold voltage of the FG and QFG MOST can be shifted (usually reduced or removed) according to the application’s requirements. The main drawback of the BD MOST is smaller transconductance in comparison to FG, QFG and GD MOST. However, the threshold voltage is removed from the signal path and wider input common mode voltage range (ICMR) is obtained (usually rail-to-rail). The BD MOST unlike of the FG and QFG MOST can process DC signals [6].

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F. Khateb et al. / Int. J. Electron. Commun. (AEÜ) 100 (2019) 32–38

(a)

Vin

S

Cin

G

B

Cb

M

(b)

Vin Vb

G Cin

Vin B M D

D

through the high resistance shunt resistor RL to conduct a channel between the source (S) and the drain (D) terminals. To avoid increased chip area the RL is simply replaced and implemented by transistors ML configured in cutoff region as shown in Fig. 2(c). The signal voltage at the gate terminal (VG) could be simplified as:

S Vin

RL

Vb

Fig. 1. (a) The BD-FG P-MOST and (b) the BD-QFG P-MOST [20,21].

C TG ¼ C GS þ C GD þ C GB þ

V1 VN

G

B

M D

V1 VN

Vb

VN

RL1 CB1

CBN

C Gi

ð2Þ

i¼1

ð3Þ

where CBi (i = 1, 2. . . N) is the coupling capacitance of the B terminal. CTB is the total capacitance seen from the B terminal and is given by:

C T ¼ C BS þ C BD þ C BSUB þ

N X

C GDMLi þ

N X

i¼1

C Bi

ð4Þ

i¼1

where CBS, CBD, CBSUB is the parasitic capacitance of bulk to source, bulk to drain, bulk to substrate of the transistor M, respectively. Eqs. (1) and (3) show that the input voltage Vi is attenuated at the gate and bulk terminals by the factors of CGi/CTG and CBi/CTB, respectively, hence the input voltage swing range is extended. The input transconductances gmi of the MI-BD-QFG MOST (from i-th input) is given by:

g mi ¼

C Gi C Bi g þ g C TG m C TB mb

ð5Þ

where gm, gmb, is the gate and bulk transconductance of the MOST, respectively. Note, that the first term of (5) is the input transconductance gmiQFG of the QFG MOST. Hence, the input transconductance of the MIBD-QFG is higher than the QFG MOST by the second term of (5). Even though the resulting transconductance is attenuated by the input capacitive dividers, it does not need to be smaller than for example the input transconductance of the BD MOST (provided that the number of inputs is not excessive), since both, the gate and the bulk terminals are controlled by the input signal. Comparing the input transconductances of the MI-BD-QFG to the BD-QFG MOST then the input transconductance of the

S

CG1

G

B

RLN

N X

N X C Bi Vi C TB i¼1

VB 

The symbol and the CMOS realization of MI-BD-QFG MOST PMOST is shown in Fig. 2(a) and (b), respectively. The input voltage terminals Vi (i = 1, 2 . . ., N) are capacitively coupled to the gate (G) terminal from one side and to the bulk (B) terminal from other side. In parallel to each of input capacitor CBi a high resistance shunt resistor RLi is connected ensuring the DC signal path. The gate terminal is further connected to a suitable bias voltage Vb

V1

C GDMLi þ

where CGS, CGD, CGB is the parasitic capacitance of gate to source, gate to drain and gate to bulk of the transistor M, respectively, and CGD-MLi is the parasitic capacitance of gate to drain of the transistor MLi. In a similar way the signal voltage at the bulk terminal (VB) could be approximated as:

2.1. The principle of operation of MI-BD-QFG MOST

(b)

N X i¼1

2. Circuit description

S

ð1Þ

where CGi (i = 1, 2. . . N) is the coupling capacitance of the G terminal. CTG is the total capacitance seen from the G terminal and is given by:

In the year 2014 and 2015 a new techniques named bulk-driven floating-gate (BD-FG) and bulk-driven quasi-floating-gate (BDQFG) were firstly presented, experimentally verified and published in the literature [20,21]. In these techniques, as shown in Fig. 1, the gate (G) terminal is biased by proper voltage Vb (through the biasing capacitor Cb for FG and the biasing large resistance RL for QFG) to conduct current between the drain (D) and source (S) terminals of the MOST. The transistor bulk (B) terminal along with the gate one (through the input capacitor Cin) are used to drive the transistor simultaneously (i.e. both are connected to input voltage Vin) and hence the effective transconductance is increased. Unlike the FG and QFG techniques the BD-FG and the BD-QFG transistors are capable to process DC signal through the bulk terminal. The BD-QFG technique was employed for the first time to build ±0.5 V and 37 mW DDCC and the advantages were experimentally verified [21]. Later more applications using the BD-QFG MOST were presented in the literature [10,22–25]. Despite of the advantages offered by the BD-QFG technique unfortunately it offer a MOST with a single input, preventing further simplification in specific CMOS topologies such as Differential Difference Amplifier or Differential Difference Current Conveyor. Therefore, this brief presents the principle and the first experimental results of the multiple-input bulk-driven quasi-floating-gate MOST suitable for LV LP integrated circuits. To demonstrate the advantages of the MI-BD-QFG MOST a DDCC is presented. Thanks to the MI-BD-QFG MOST the DDCC use one differential pair instead of conventional two, hence the power consumption and the circuit’s complexity are reduced. Note, that the same principle could be applied to achieve multiple-input bulk-driven floating-gate (MIBD-FG) MOST.

(a)

N X C Gi Vi C TG i¼1

VG 

M D

CGN RL

Vb

(c)

V1 VN

ML

RL

ML

Fig. 2. The MI-BD-QFG P-MOST: (a) symbol, (b) MOS realization and (c) MOS realization of RL.

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F. Khateb et al. / Int. J. Electron. Commun. (AEÜ) 100 (2019) 32–38

VY2 VY3

IY2 IY3

DDCC

v 2niMIBDQFG ¼

Y1 Y2 Y3

Z

IZ

  g mi - QFG þ g mb 2 2 v nBDQFG g mi  2 g m þ Ng mb ¼ v 2nBDQFG g m þ g mb

VZ

VX

Fig. 3. Symbol of the DDCC.

MI-BD-QFG is slightly reduced due to the attenuation of the bulk transconductance by CBi/CTB whereas the gate transconductances for both techniques are the same due to the attenuation by the same factor CGi/CTG. Finally, the relationship between the inputs-referred noises power spectral density of MI-BD-QFG MOST compared to BD, QFG and BD-QFG MOST and assuming for simplicity that CGi/CTG = CBi/CTB = 1/N, we obtain respectively:

 2 g mb N2 v 2nBD ¼  2 v 2nBD g mi gm 1þg

ð6Þ

ð8Þ

Eqs. (6)–(8) show that the inputs-referred noise power spectral density of MI-BD-QFG MOST can be even lower than for a BD MOST (provided that the number of inputs of the MI-BD-QFG is not excessive). It is also lower than for QFG MOST. However, it is slightly higher than for BD-QFG MOST. 2.2. DDCC based on the MI-BD-QFG MOST The differential difference current conveyor was firstly proposed in 1996 [26]. It is widely used in analog signal applications since it has the capability of performing arithmetic operations (voltage summation and subtraction). The symbol of DDCC is shown in Fig. 3. The ideal relationships between voltages and currents of the DDCC terminals can be described by the following matrix:

mb

M3 Y1 Y3 IB

ð7Þ

v 2niMIBDQFG ¼

IX

v 2niMIBDQFG ¼

  g mi - QFG 2 2 1 v nQFG ¼  2 v 2nQFG g mi 1 þ ggmb m

X

VY1

IY1

M1

Y1 Y3 Vb

MB M4

Y2

M2

VDD M9

M7 Y2 Vb

M5

RC CC M6

X

M8

Fig. 4. The CMOS structure of the MI-BD-QFG DDCC.

(a)

78 µm

350 µm

(b) Fig. 5. The MI-BD-QFG DDCC: (a) circuit layout and (b) chip microphotograph.

Z

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F. Khateb et al. / Int. J. Electron. Commun. (AEÜ) 100 (2019) 32–38

Fig. 6. Measured frequency response of the voltage gain: (a) VX/VY1 and (b) VX/VY2.

Fig. 8. Measured transient step response (input VY1 (CH1) and output VX (CH2)) for 450mVpp and: (a) 1 kHz and (b) 5 kHz.

Fig. 9. Measured and simulated DC characteristic VX versus VY1 with near rail-torail operation.

0

IY1

1

0

0

0

0

C B B B IY2 C B 0 0 0 C B B B IY3 C ¼ B 0 0 0 C B B C B B @ V X A @ 1 1 1 0 0 0 IZ Fig. 7. (a) Input VY1 (CH1) and output VX (CH2), and (b) input VY2 (CH1) and output VX (CH2) waveforms for 450 mVPP and 1 kHz input sinusoidal signal.

0 0

10

V Y1

1

CB C 0 0 CB V Y2 C CB C C B 0 0 CB V Y3 C C CB C 0 0 A@ I X A 1 0 VZ

ð9Þ

The DDCC based on MI-BD-QFG MOST is shown in Fig. 4. Unlike the conventional structure of the DDCC that use two differential pairs the proposed structure use only one pair created by

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F. Khateb et al. / Int. J. Electron. Commun. (AEÜ) 100 (2019) 32–38

Fig. 10. Corner analysis for the DC characteristic VX versus VY1.

MI-BD-QFG M1, M2, hence, the current branches and the power consumption are reduced. The DC operating point of the gate terminal is set to a suitable bias voltage Vb (by transistors ML from Fig. 2c). Transistors M4, M5 act as current sources loading the differential pair. Transistor M3 act as tail current source for the differential pair. Transistors M6, M7 create the second amplification stage of the DDCC. The drain terminal of M6, M7 is connected in unity gain feedback to the input terminal of transistor M2 hence the unity gain buffer between the Y and X terminals is ensured. Transistors M8, M9 ensure the current transfer between the X and Z terminals. Bias current IB along with transistor MB set the bias current of the DDCC. The compensation network (RC, CC) insure the stability of the circuit. The minimum voltage supply of the proposed topology is very low and is given by one gate-source and one drain-source voltage i.e. VgsM3 + VDSM5. To the best of the authors’ knowledge, the proposed DDCC structure is by now the simplest one in the literature. 3. Measurement and simulation results The proposed MI-BD-QFG DDCC circuit was designed in Cadence platform and fabricated using the 0.18 mm TSMC CMOS technology with total chip area 350 mm
78 mm including the

electrostatic discharge (ESD) protections. The circuit layout (including the components names) and chip microphotograph are shown in Fig. 5(a) and (b), respectively. The circuit uses a supply voltage 0.5 V (±0.25 V for the purpose of measurement), the bias current IB = 0.5 mA and the power consumption is only 1.7 mW. The transistor aspect ratios (W/L) are: 20 mm/3 mm for M1, M2, 30 mm/3 mm for M4, M5 and MB, 2
30 mm/3 mm for M6 and M8, 2
200 mm/1 mm for M3, M7 and M9. The input bulk and gate capacitors are implemented by MIM (Metal–Insulator–Metal) capacitor. Each of the bulk capacitor CB is 0.5 and each of the gate capacitor CG is 1 pF. Each of the transistor ML has 4 mm/5 mm. The bias voltage Vb = GND. RC = 100 kO, CC = 6 pF and the load capacitance CL is 30 pF. Selected post-layout simulation and experimental results are shown in Figs. 6–10. Fig. 6(a) and (b) shows the measurement result of the frequency response of the voltage gains VX/VY1 (for VY2 = VY3 = 0 V) and VX/VY2 (for VY1 = VY3 = 0 V) using the Vector Network Analyzer – Bode 100. The voltage gain @ 1 Hz and the cutoff frequency are 85 mdB, 149 kHz for both VX/VY1 and VX/VY3 and 13.8 mdB, 158 kHz for VX/VY2. Fig. 7(a) and (b) shows, respectively, the measured output waveforms VX for a sinusoidal input signal VY1 (for VY2 = VY3 = 0 V) and VY2 (for VY1 = VY3 = 0 V) with peak-to-peak of 450 mV and f = 1 kHz. The total harmonic distortion (THD) was 0.25%. It is evident the near rail-to-rail operation with low THD. Fig. 8 shows the measured transient response of the output VX to a 450 mV peak-to-peak input step VY1 (for VY2 = VY3 = 0 V) with: (a) 1 kHz and (b) 5 kHz frequency. The slew rate SR+ is 72 V/ms and SR is 28.3 V/ms. The SR was mainly constrained by the class A output stage (input stage operates in class AB), thus resulting in non-symmetrical SR behavior. This disadvantage could be overcome with class AB output stage. Figs. 6–8 show the good performances of the circuit. The measured and post-layout simulated DC characteristic of VX versus VY1 (for VY2 = VY3 = 0 V) is shown in Fig. 9. The near rail-torail DC operating range is evident. Fig. 10 shows the post-layout simulated DC characteristics VX versus VY1 using the corner analysis over process, voltage and temperatures (PVT) worst-case corners. The process corners were fastfast, fast-slow, slow-fast and slow-slow; the supply voltage corners were 490 mV and 510 mV and the temperature corners were 0 °C and 50 °C. From Fig. 10, it is evident that the performance is insensitive over PVT corners.

Fig. 11. The histogram of the input referred offset voltage based on Monte Carlo analysis.

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F. Khateb et al. / Int. J. Electron. Commun. (AEÜ) 100 (2019) 32–38 Table 1 Experimental and simulated results of the MI-BD-QFG DDCC and compared to BD, QFG and BD-QFG DDCCs.

a

Parameter

BD-QFG DDCC [21]

BD DDCC [19]

QFG DDCC [19]

BD-QFG DDCC [19]

This work MI-BD-QFG DDCC 45 nm

This work MI-BD-QFG DDCC 180 nm

Supply voltage [V] Power consumption [mW] Slew rate SR+ [V/ms] Slew rate SR [V/ms] 3dB bandwidth IZ/IX [kHz] 3dB bandwidth VX/VY1, VX/VY2, VX/VY3 [kHz]

±0.5 37 – – 8E3 650

±0.3 18.5 – – 27E3 27E3

±0.3 18.5 – – 24E3 24E3

±0.3 18.5 – – 42E3 42E3

±0.25 1.7 72 28.3 250 149, 158, 149

Current gain IZ/IX [–] Voltage gains VX/VY1, VX/VY2, VX/VY3 [–] DC current range [lA] DC voltage range [mV] Input noisea) [nV/Hz1/2] (VTH/VDD) * 100 [%] (Vin-max/VDD) * 100 [%] CL [pF] CMOS technology [nm]

1 1 4 to 4 800 – 70 80 20 350 AMIS

1 1 8 to 8 300 – 83.3 50 1 180 TSMC

1 1 Blocked Blocked – 83.3 50 1 180 TSMC

1 1 8 to 8 300 – 83.3 50 1 180 TSMC

±0.25 0.35 15.2 5.7 50.6 44.1, 44.7, 44.1 1 1 0.2 to 0.2 220 – 100 44 30 45 nm

Chip area [mm2] Results

0.0566 Meas.

– Sim.

– Sim.

– Sim.

– Sim.

0.999 0.993, 0.998, 0.993 1 to 1 450 – 100 90 30 180 TSMC 0.0273 Meas.

73 29 265 175, 181, 175

0.999

150

Sim.

Thermal noise @ 10 kHz.

The histogram of Fig. 11 shows the simulated distribution of the input referred dc offset voltage of the DDCC based on Monte Carlo (MC) mismatch analysis (200 runs). The standard deviation of the dc offset is around 4.93 mV that proves acceptable low circuit sensitivity to transistor mismatches. Finally, the simulated and measured performance parameters of the proposed MI-BD-QFG DDCC are summarized in Table 1 and compared to the BD, QFG and BD-QFG DDCCs presented in [19,21]. However, since the comparison is done for different designs in different CMOS technologies (i.e. different values of threshold voltage) using also different supply voltages two realistic indicators are used. The first indicator shows the effectiveness of a design to work under low supply voltage and it is defined as the threshold-to-supply voltage ratio (VTH/VDD). The second indicator shows the effectiveness of a design of extending the input common mode voltage range and it is defined as the ratio between the maximum input voltage range and the corresponding supply voltage (Vin-max/VDD). It is evident that the proposed MI-BD-QFG DDCC consumes much less power than others DDCCs due to the less count of current branches. Other parameters are also attractive including VTH/VDD, Vin-max/VDD and chip area. It is worth to mention that comparing the MI-BD-QFG DDCC that employ one differential pair to BD-QFG DDCC that employ two differential pairs, then the MI-BD-QFG has about 5% increased chip area due to the extra chip area occupied by the input capacitors CBi and the high resistance transistors MLi; however, the power consumption is reduced by about 28%. Hence, the MI-BD-QFG technique is the most suitable for low-voltage low-power applications. The proposed MI-BD-QFG DDCC circuit was also simulated in Pspice using 45 nm CMOS spice model available in [27]. The transistor aspect ratios, passive components, voltage supply were the same, however, the bias current has been reduced to IB = 0.1 mA to insure the proper biasing of the circuit. The simulation results are included in Table 1. As it can be concluded from these results, the circuit operates properly also in this case, which proves the applicability of the proposed technique in circuits realized with contemporary nanometric technologies. 4. Conclusion In this paper the principle and the first experimental results of the multiple-input bulk-driven quasi-floating-gate MOS transistor

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