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Journal Pre-proofs Analysis of Fluorine Effects on Charge-Trap Flash Memory of W/TiN/Al2O3/ Si3N4/SiO2/Poly-Si Gate Stack Tae Yoon Lee, Seung Hwan Lee, Jun Woo Son, Sang Jae Lee, Jae Hoon Bong, Eui Joong Shin, Sung Ho Kim, Wan Sik Hwang, Jung Min Moon, Yang Kyu Choi, Byung Jin Cho PII: DOI: Reference:
S0038-1101(19)30396-X https://doi.org/10.1016/j.sse.2019.107713 SSE 107713
To appear in:
Solid-State Electronics
Received Date: Revised Date: Accepted Date:
26 June 2019 16 November 2019 20 November 2019
Please cite this article as: Yoon Lee, T., Hwan Lee, S., Woo Son, J., Jae Lee, S., Hoon Bong, J., Joong Shin, E., Ho Kim, S., Sik Hwang, W., Min Moon, J., Kyu Choi, Y., Jin Cho, B., Analysis of Fluorine Effects on Charge-Trap Flash Memory of W/TiN/Al2O3/Si3N4/SiO2/Poly-Si Gate Stack, Solid-State Electronics (2019), doi: https://doi.org/ 10.1016/j.sse.2019.107713
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
© 2019 Published by Elsevier Ltd.
Analysis of Fluorine Effects on Charge-Trap Flash Memory of W/TiN/Al2O3/Si3N4/SiO2/Poly-Si Gate Stack
Tae Yoon Leea, Seung Hwan Leea, Jun Woo Sona, Sang Jae Leea, Jae Hoon Bonga, Eui Joong Shina, Sung Ho Kima, Wan Sik Hwangb, Jung Min Moona, Yang Kyu Choia and Byung Jin Choa, *
a School
of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291
Daehak-ro, Yuseong-gu, Daejeon 305-701, South Korea b
Department of Materials Engineering, Korea Aerospace University, Goyang 412-791, South Korea
* Corresponding
Author: Professor Byung Jin Cho
School of Electrical Engineering, KAIST E-mail address: [email protected] Tel.: +82 (0)42 350 3485; fax: +82 (0)42 350 8565
1
Abstract A charge-trap flash (CTF) memory stack of chemical vapor deposition (CVD) tungsten (W) was systematically compared with a physical vapor deposited (PVD) W memory stack. The residual F in the CVD W was diffused into Al2O3, Si3N4, SiO2, and the interface at SiO2/poly-Si after the subsequent annealing process at 900˚C for 1 sec. The diffused F increased the SiO2 thickness and altered the chargetrap density in the Al2O3, Si3N4, SiO2, and SiO2/poly-Si interface, and this eventually affected memory performance and reliability. The memory window and program/erase retention properties degraded while the charge-transport and endurance characteristics improved with the CVD W memory as compared to the PVD W memory.
Highlights: •
Investigation of Fluorine effects on flash memory characteristics and transfer characteristics.
•
Analysis of Fluorine effects on each gate stack by Secondary Ion Mass Spectroscopy (SIMS), Transmission Electron Microscopy (TEM), and AC-Transconductance method.
Keywords: Chemical vapor deposition (CVD), tungsten (W), fluorine (F), charge-trap flash (CTF), memory device
2
1. Introduction The continued demands for higher bit densities and lower bit costs triggered a transition from planar NAND to 3-dimensional (3D) stacked vertical NAND flash memory [1-3]. The associated structures have in turn introduced critical challenges such as process integration [4]. The conventional physical vapor deposited (PVD) tungsten (W) used in the metal electrodes found in planar NAND structures is unsuitable for 3D vertical NAND structures because of its anisotropic deposition. Unlike PVD W, chemical vapor deposited (CVD) W provides conformal deposition with excellent step coverage, making it suitable for the process integration of 3D NAND flash memory [5]. However, residual F in CVD W originates from the tungsten hexafluoride (WF6) gas, which raises potential concerns in terms of memory operation and device reliability. This residual F in the W can diffuse into a memory stack during a subsequent annealing process. Despite the importance of CVD W in 3D NAND flash memory, the effects of F on 3D NAND memory devices are not well known. Of note, several groups have investigated F effects on charge-trap flash (CTF) memory devices [6-8]; the F atoms in their studies were induced via implantation [6], plasma [7], and high pressure gas annealing [8], eliciting concerns regarding ion implantation, high pressure conditions, and plasma. Very recently, F effects originating from CVD W were investigated on a CTF NAND structure [9]. However, the moderate annealing conditions in that work caused insufficient F diffusion into the memory stack, and the effects of F on the memory device were thereby underestimated. In addition, the F effects on the interface between the single crystal Si wafer and tunnel oxide did not represent the memory stack of the state-of-the-art NAND memory device. In the present work, the CVD W-derived effects of F were investigated on the 3D NAND memory cell of a poly-Si channel, which underwent an elevated annealing temperature of 900 ˚C for 1 sec. In detail, the effects of F on the memory cell device were investigated and compared to those of PVD W memory in terms of drain current (ID), subthreshold swing (SS), field-effect electron mobility (μ), program-erase (P/E) speed, charge-trap density, charge retention, and endurance.
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2. Experimental In this experiment, the CTF memory transistors of a W/TiN/Al2O3/Si3N4/SiO2/poly-Si gate stack were fabricated. The starting substrate was a (100) lightly doped p-type Si wafer. 100-nm thick SiO2 was thermally grown over the Si wafer via wet oxidation. On top of the insulating SiO2 layer, 100-nm thick un-doped poly-Si was deposited via low pressure chemical vapor deposition (LP-CVD) using SiH4 gas at 620˚C for 180 min. To realize an n-channel metal-oxide semiconductor field-effect transistor (nMOSFET), B ion implantation was conducted on the poly-Si channel with a dose of 5x1012 cm-2 and an energy of 6 keV, followed by the dopant activation via rapid thermal annealing (RTA) at 1050˚C for 1 min. After dopant activation, the active channel area was defined via conventional photolithography and a dry-etch process. A gate-last process was adopted to form the memory transistors. Thus, initially, source/drain formation was conducted via As ion implantation with a dose of 5x1015 cm-2 and an energy of 20 keV. To form a memory gate stack, 7-nm thick SiO2 was thermally grown as a tunnel oxide after a standard pre-gate cleaning process. Next, 7.5-nm thick Si3N4 was deposited as a charge-trap layer via LPCVD using a dichlorosilane (DCS) precursor and NH3 reactant gas at 720˚C. As a blocking oxide, 13-nm thick Al2O3 was deposited via thermal atomic layer deposition (ALD) using a trimethylaluminum (TMA) precursor and H2O as a reactant gas at 350˚C. Before CVD W deposition, 10-nm thick TiN was deposited via plasma enhanced ALD (PE-ALD) using a TEMA-Ti precursor with NH3 plasma at 230˚C. This TiN layer served as an adhesion and barrier metal. Finally, 70-nm thick W was deposited via thermal-CVD with a two-step deposition process. W was nucleated using the SiH4 reduction of the WF6, and the bulk W was subsequently deposited via the H2 reduction of the WF6 at 430˚C for 7 min. To compare the Fcontaining CVD W memory device, F-free PVD W memory device was also fabricated. After the memory gate stack was completed, the gate area was defined using dry etching, followed by an annealing process at 900˚C for 1 sec. 100-nm thick Al was deposited on the source and drain regions via the PVD process to improve the electrical contact. Finally, forming gas annealing (FGA) was performed at 410˚C for 30 min. 4
3. Results and discussion
Figure 1. Back-side SIMS profiles of Si, Al, Ti, W, O, N, and F in CTF memory stack with (a) PVD W and (b) CVD W after an annealing process at 900˚C for 1 sec Figure 1 shows the back-side SIMS profiles of Si, Al, Ti, W, O, and N, as well as the residual F in the CTF memory stack with PVD W and CVD W after the annealing process at 900˚C for 1 sec. It was found that the residual F in the CVD W diffused and accumulated in the TiN layer at the as-deposited condition [9]. This F in the TiN and CVD W further diffused into the CTF memory stack and remained to a significant extent in the Al2O3 and Si3N4. Furthermore, the diffused F was also found in the SiO2 and the interface at the poly-Si/SiO2 after annealing at 900˚C for 1 sec. Unlike the CTF memory stack with CVD W, the F concentration in the PVD W memory stack constituted insignificantly low noise levels.
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Figure 2. Cross sectional STEM images of CTF memory stack with (a) PVD W and (b) CVD W after an annealing process at 900˚C for 1 sec. Figure 2 shows a comparison of the STEM images of a CTF memory stack with PVD W and CVD W. The results demonstrate that the thicknesses of the Al2O3 and Si3N4 in the CVD memory were comparable to those of the PVD memory. On the other hand, the SiO2 thickness in the CVD W memory increased by around 10% over that of the PVD W memory. This increase was presumably due to the F incorporation, which was also reported by several groups [10, 11]. These groups proposed that the diffused F atoms reacted with the locally strained Si/SiO2 interface, which broke the Si-O bonds and released the O atoms. These atoms in turn caused the re-oxidization of the Si/SiO2 interface and thereby increased the SiO2 thickness. The increase in SiO2 thickness with the residual F in this work suggested that diffused F atoms reacted with the locally strained interface at the poly-Si/SiO2, and it thereby re-oxidized the poly-Si/SiO2 interface in the CTF memory stack.
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Figure 3. (a) Program/erase speed of CTF memory transistors with PVD W and CVD W metal gates. (b) Energy band diagram of CTF memory device during erase operation. The F effects on the memory stack were further investigated using CTF memory transistors. Figure 3 shows a comparison of the program/erase (P/E) characteristics of the CVD W memory and PVD W memory. The results show that the P/E speed and memory window with the CVD W memory degraded compared to the PVD W memory. Interestingly, the results in the present study, the F remained in the tunneling SiO2 and poly-Si/SiO2 interface, were inconsistent with previous findings where F did not diffused into the tunneling SiO2 and poly-Si/SiO2 interface [9]. It is presumed that the F in the tunneling SiO2 and poly-Si/SiO2 interface caused this discrepancy, as will be discussed with the experimental results below. It was presumed that the increased SiO2 thickness and decreased dielectric constant of Al2O3 by F incorporation led to lower applied filed on the tunnel oxide in the CVD W memory, compared to that in the PVD W memory. Figure 3(a) also showed that erase window in the CVD W memory was significantly degraded compared to the program window, which was related to the erase saturation. In general, an erase saturation phenomenon occurs when the electron back-tunneling current (J1), electron de-trapping current (J2), and hole injection current (J3) reaches dynamic equilibrium (J1=J2+J3), as shown in figure 3(b) [12]. In the present study, when the gate-substrate voltage of -21V was applied to both the 7
CVD W and PVD W memories during the erase operation, the electric field applied to the blocking oxide of the CVD W and PVD W memories were comparable. On the other hand, electric field applied on tunnel oxide was -12.1 (MV/cm) in PVD W memory and -11.3 (MV/cm) in CVD W memory. Smaller applied electric field on tunnel oxide of CVD W memory leads to reduce J2 and J3 than PVD W memory. Eventually, erase saturation is occurred at lower delta VT in CVD W memory because J1 increases as pulse width time increases. The decrease of dielectric constant of Al2O3 will be demonstrated further in figure 6.
Figure 4. (a) Retention characteristics of CTF memory transistors with PVD W and CVD W metal gates. (b) Energy band diagram of CTF memory device during programmed retention state and (c) erased retention state. 8
Figure 4(a) shows the charge-retention characteristics of the CTF memories with PVD W and CVD W in programmed/erased states over time at different temperatures. The results showed that the charge-loss in the CVD W memory was higher than that in the PVD W memory in both the programmed and erased states regardless of measurement temperatures. To understand the charge-loss mechanism in the CVD W memory, several possible electron-loss paths in the programmed state were described and discussed in figure 4(b). Electron de-trapping through tunnel oxide (①) was improbable considering retention result because of greater thickness and lower oxide trap density of SiO2 in CVD W memory. The trap density of the tunnel oxide was further reduced by the F incorporation, which is demonstrated in further detail in figure 9. The hole injection (③, ④) was also neglected due to the large valence band offset. Thus, the poor programmed retention characteristics of the CVD W memory at room temperature (RT) could be explained by the trap-assisted tunneling (②) via the electron trap sites in the blocking of the CVD W memory, as shown in figure 4(b). The electron-trap sites were generated by the F incorporation, which will be demonstrated further in figure 6. This explanation is well supported by previous studies [13, 14], which claimed that the blocking oxide was the main path of the charge-loss instead of the tunnel oxide in the programmed retention of the CTF memory. For elevated temperatures, thermionic emissions (⑤) are dominant charge-loss mechanism that are highly affected by the band offset and trap energy depth of the charge trap layer (Si3N4) [15, 16]. For the present study, this implies that shallow-level electron-trap sites were generated in the Si3N4 due to the incorporation of F, which affected the charge-loss mechanism at the elevated temperature. Figure 4(c) shows the several possible paths of the hole-loss in the erased state. Similar to the programmed state, the charge-loss through the tunnel oxide (①, ③) was negligible, but the electron injection from the gate (②) was possible. The de-trapping of holes through the blocking oxide (④) also contributed to the retention properties in the erased state. These results implied that not only the electrons, but also the holes affected the charge retention properties of the CTF memory, which will be 9
further discussed below.
Figure 5. Charge loss after 104 sec in program- and erase-state retention tests at room temperature
Figure 5 shows a comparison of the delta VT in the programmed and erased states of the PVD W and CVD W memory after 1000 sec at room temperature. While the delta VT values in the PVD memory were indistinguishable in each state, the delta VT values in the erased state were much higher than those in the programmed state in the CVD W memory. This indicated that an additional charge-loss path was involved in the erased state of the CVD W memory, unlike in the P/E retention properties of the PVD W memory. The additional charge-loss was presumably due to the hole-trap sites in the Al2O3, as shown in Figure 4(c). Normally, under elevated temperatures, the thermionic emission (⑤) of the holes will dominate the charge-retention in the erased state. Thus, the poor retention-property of the CVD W memory compared to the PVD W memory could be explained by the generation of the shallow-level hole-trap sites in the Si3N4 caused by the F diffusion in the CVD W memory.
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Figure 6. (a) Capacitance-voltage curves (frequency = 100 kHz). The 27-nm thick Al2O3 was deposited via the thermal ALD, and it was subsequently annealed at 900˚C for 1 sec. (b) Gate leakage current of MOS capacitors with PVD W and CVD W metal gates as a function of the applied electric field on oxide. Negative bias was applied to the gate. To further investigate the charge retention behavior through the blocking oxide at RT, metal-oxidesemiconductor (MOS) capacitors consisting of a W/TiN/27-nm thick Al2O3/p-type Si substrate were fabricated, as shown in the inset of figure 6(a). Figure 6 (a) shows the capacitance-voltage (CV) curves of the CVD W and PVD W capacitors. The results showed that the accumulation value of the CV curve of the CVD W capacitor was smaller than that of the PVD W capacitor. It was inferred that this reduction in the capacitance value in the CVD W capacitor was due to the decreased dielectric constant of the Al2O3 via F incorporation because the AlOxFy could be partially formed in the Al2O3 via the residual F incorporation. Of note, the AlF3 dielectric constant was about 6.0 [17]. The Al2O3 in the PVD W capacitor was extracted to be about 9.58, while that in the CVD W capacitor was about 9.06. Figure 6(b) shows the gate leakage current of the MOS capacitors with the PVD W and CVD W metal gates as functions of the electric field. The CVD W capacitor showed a higher leakage current at the low field region, indicating that the additional charge conduction path was generated due to the F incorporation. The generation of electron traps in the Al2O3 degraded the retention characteristics. The lower leakage current of the CVD W compared to the PVD W at the high field region was caused by the trapped charges that prevented further leakage conduction. 11
Figure 7. The endurance characteristics of the CTF memory transistors with PVD W and CVD W metal gates. Next, the endurance characteristics of the CTF memories with the PVD W and CVD W were compared depending on the number of P/E cycles, as shown in figure 7. In contrast to the P/E speed and data retention behaviors, the CVD W memory showed better endurance characteristics than the PVD W memory. Cycling tests are known to degrade memory performance mainly due to the trap generation in the tunnel oxide and tunnel oxide/channel interface [18, 19]. Thus, it was inferred that the F incorporation in the tunnel oxide reduced the trap generation in the tunnel oxide and tunnel oxide/channel interface, which will be demonstrated further in Figure 8 and 9. Likewise, reductions in interface trap density (Dit) and improvements in the charge to the breakdown (QBD) distribution of the SiO2 via F incorporation have also been reported [10, 11].
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Figure 8. Charge-transfer characteristics of the CTF memory transistors with PVD W and CVD metal gates. (a) Drain current as a function of gate voltage (b) Extracted field effect mobility from transconductance. Figure 8(a) shows the charge-transfer characteristics of the CTF transistor with PVD W and CVD W. The subthreshold swings (SSes) of the PVD W and CVD W transistors were 446 and 384 mV/decade, respectively. The SS distributions of the PVD W and CVD W are shown in the inset of figure 8(a). In addition, the field-effect electron mobility (μ) was also compared, as shown in figure 8(b). The fieldeffect peak mobility of the PVD W and CVD W memory transistors were 8.35 cm2/Vs and 11.09 cm2/Vs, respectively. These results indicated that the CVD W memory showed improved SS and μ values over the PVD W memory, and the CVD W transistor showed reduced trap generation in the tunnel oxide and tunnel oxide/channel interface caused by the F incorporation.
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Figure 9. Depth profile of charge-trap density as a function of energy inside the TO. The interface of the poly-Si channel/TO is position x=0. To correlate the charge-transfer characteristics shown in figure 8, AC-gm measurements were performed, and the trap distributions of the tunnel oxide in terms of energy and depth were extracted [20]. The position of the oxide trap (x) from the interface was expressed via electron trapping and de-trapping along the frequency shown in Eq. (1).
x = λln
( ) 1 ωτ0
(1)
where λ is the tunneling distance, ω is the frequency, and τ0 is the trap time constant when x=0 and ET=EF. Meanwhile, the trap energy from the conduction band of the poly-Si channel was expressed as shown in Eq. (2) where ET is the trap energy level, and x0 is the total thickness of the gate dielectric.
x 𝑥0
ET - EF = (VG,dc - VT)
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(2)
Finally, the trap density was extracted by differentiating the measured AC-gm with the frequency, as shown in Eq. (3). dgm Not(ET,x) ≈
dlnω x W x 1― qλVDμdc x0 L x0
(
)
(3)
By using these equations, tunnel oxide trap density as a function of energy and depth was extracted, as shown in figure 9. The CVD W memory showed a reduced charge-trap density than the PVD W memory. As mentioned, the diffused F in the tunnel oxide in the CVD W reduced the charge-trap density in the tunnel oxide and improved the hot-carrier immunity in the CTF memory transistor.
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4. Conclusion CTF memory stacks with Al2O3/Si3N4/SiO2/poly-Si substrate stacks were systemically compared with PVD W and CVD W. It was found that the residual F in the CVD W diffused into the Al2O3, Si3N4, SiO2, and SiO2/poly-Si interface after the subsequent annealing process at 900˚C for 1 sec. The diffused F in the Al2O3 generated charge-trap sites that became a major charge-loss path during the retention test at room temperature. The residual F in the Si3N4 was responsible for the poor-retention characteristics at the elevated temperature in the CVD W. The SiO2 thickness in the CVD W increased due to the diffused F, which degraded the program and erase speed, and eventually the memory window. The diffused F in the SiO2 also reduced the SiO2 trap density, which was evidenced using an AC-gm analysis. This reduced trap density in the SiO2 caused by the diffused F was responsible for the improved charge-transfer behavior in the CVD W transistor compared to the PVD W transistor.
Acknowledgements This paper was the result of a research project funded by SK Hynix Inc, Icheon-si, Korea.
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Byung Jin Cho (M’97–SM’01) received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 1985 and the M.S. and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1987 and 1991, respectively. From 1991 to 1993, he was with Interuniversity Microelectronics Center, Leuven, Belgium, as a Research Fellow, where he worked on advanced silicon processing. From 1993 to 1997, he joined the Memory Research and Development Division, Hyundai Electronics (currently Hynix Semiconductor), Ichon, Korea, as a Section Manager, where he led a research team for the process development for 256Mb and 1G dynamic random access memory and Flash electrically erasable programmable read-only memory (EEPROM). In 1997, he joined the Department of Electrical and Computer Engineering, National University of Singapore (NUS), as a Faculty Member. Since 2007, he has been with the Department of Electrical Engineering, KAIST, as a Faculty Member. His main research interests are advanced complementary metal–oxide–semiconductor device and front-end process technology, memory devices, graphene-based devices, graphene synthesis and process, thermoelectric generator devices, and flexible electronics. He has published over 456 technical papers. He is the holder of over 33 patents.
Highlights: •
Investigation of Fluorine effects on flash memory characteristics and transfer characteristics.
•
Analysis of Fluorine effects on each gate stack by Secondary Ion Mass Spectroscopy (SIMS), Transmission Electron Microscopy (TEM), and AC-Transconductance method.
18
S0038-1101(19)30396-X https://doi.org/10.1016/j.sse.2019.107713 SSE 107713
To appear in:
Solid-State Electronics
Received Date: Revised Date: Accepted Date:
26 June 2019 16 November 2019 20 November 2019
Please cite this article as: Yoon Lee, T., Hwan Lee, S., Woo Son, J., Jae Lee, S., Hoon Bong, J., Joong Shin, E., Ho Kim, S., Sik Hwang, W., Min Moon, J., Kyu Choi, Y., Jin Cho, B., Analysis of Fluorine Effects on Charge-Trap Flash Memory of W/TiN/Al2O3/Si3N4/SiO2/Poly-Si Gate Stack, Solid-State Electronics (2019), doi: https://doi.org/ 10.1016/j.sse.2019.107713
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
© 2019 Published by Elsevier Ltd.
Analysis of Fluorine Effects on Charge-Trap Flash Memory of W/TiN/Al2O3/Si3N4/SiO2/Poly-Si Gate Stack
Tae Yoon Leea, Seung Hwan Leea, Jun Woo Sona, Sang Jae Leea, Jae Hoon Bonga, Eui Joong Shina, Sung Ho Kima, Wan Sik Hwangb, Jung Min Moona, Yang Kyu Choia and Byung Jin Choa, *
a School
of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291
Daehak-ro, Yuseong-gu, Daejeon 305-701, South Korea b
Department of Materials Engineering, Korea Aerospace University, Goyang 412-791, South Korea
* Corresponding
Author: Professor Byung Jin Cho
School of Electrical Engineering, KAIST E-mail address: [email protected] Tel.: +82 (0)42 350 3485; fax: +82 (0)42 350 8565
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Abstract A charge-trap flash (CTF) memory stack of chemical vapor deposition (CVD) tungsten (W) was systematically compared with a physical vapor deposited (PVD) W memory stack. The residual F in the CVD W was diffused into Al2O3, Si3N4, SiO2, and the interface at SiO2/poly-Si after the subsequent annealing process at 900˚C for 1 sec. The diffused F increased the SiO2 thickness and altered the chargetrap density in the Al2O3, Si3N4, SiO2, and SiO2/poly-Si interface, and this eventually affected memory performance and reliability. The memory window and program/erase retention properties degraded while the charge-transport and endurance characteristics improved with the CVD W memory as compared to the PVD W memory.
Highlights: •
Investigation of Fluorine effects on flash memory characteristics and transfer characteristics.
•
Analysis of Fluorine effects on each gate stack by Secondary Ion Mass Spectroscopy (SIMS), Transmission Electron Microscopy (TEM), and AC-Transconductance method.
Keywords: Chemical vapor deposition (CVD), tungsten (W), fluorine (F), charge-trap flash (CTF), memory device
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1. Introduction The continued demands for higher bit densities and lower bit costs triggered a transition from planar NAND to 3-dimensional (3D) stacked vertical NAND flash memory [1-3]. The associated structures have in turn introduced critical challenges such as process integration [4]. The conventional physical vapor deposited (PVD) tungsten (W) used in the metal electrodes found in planar NAND structures is unsuitable for 3D vertical NAND structures because of its anisotropic deposition. Unlike PVD W, chemical vapor deposited (CVD) W provides conformal deposition with excellent step coverage, making it suitable for the process integration of 3D NAND flash memory [5]. However, residual F in CVD W originates from the tungsten hexafluoride (WF6) gas, which raises potential concerns in terms of memory operation and device reliability. This residual F in the W can diffuse into a memory stack during a subsequent annealing process. Despite the importance of CVD W in 3D NAND flash memory, the effects of F on 3D NAND memory devices are not well known. Of note, several groups have investigated F effects on charge-trap flash (CTF) memory devices [6-8]; the F atoms in their studies were induced via implantation [6], plasma [7], and high pressure gas annealing [8], eliciting concerns regarding ion implantation, high pressure conditions, and plasma. Very recently, F effects originating from CVD W were investigated on a CTF NAND structure [9]. However, the moderate annealing conditions in that work caused insufficient F diffusion into the memory stack, and the effects of F on the memory device were thereby underestimated. In addition, the F effects on the interface between the single crystal Si wafer and tunnel oxide did not represent the memory stack of the state-of-the-art NAND memory device. In the present work, the CVD W-derived effects of F were investigated on the 3D NAND memory cell of a poly-Si channel, which underwent an elevated annealing temperature of 900 ˚C for 1 sec. In detail, the effects of F on the memory cell device were investigated and compared to those of PVD W memory in terms of drain current (ID), subthreshold swing (SS), field-effect electron mobility (μ), program-erase (P/E) speed, charge-trap density, charge retention, and endurance.
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2. Experimental In this experiment, the CTF memory transistors of a W/TiN/Al2O3/Si3N4/SiO2/poly-Si gate stack were fabricated. The starting substrate was a (100) lightly doped p-type Si wafer. 100-nm thick SiO2 was thermally grown over the Si wafer via wet oxidation. On top of the insulating SiO2 layer, 100-nm thick un-doped poly-Si was deposited via low pressure chemical vapor deposition (LP-CVD) using SiH4 gas at 620˚C for 180 min. To realize an n-channel metal-oxide semiconductor field-effect transistor (nMOSFET), B ion implantation was conducted on the poly-Si channel with a dose of 5x1012 cm-2 and an energy of 6 keV, followed by the dopant activation via rapid thermal annealing (RTA) at 1050˚C for 1 min. After dopant activation, the active channel area was defined via conventional photolithography and a dry-etch process. A gate-last process was adopted to form the memory transistors. Thus, initially, source/drain formation was conducted via As ion implantation with a dose of 5x1015 cm-2 and an energy of 20 keV. To form a memory gate stack, 7-nm thick SiO2 was thermally grown as a tunnel oxide after a standard pre-gate cleaning process. Next, 7.5-nm thick Si3N4 was deposited as a charge-trap layer via LPCVD using a dichlorosilane (DCS) precursor and NH3 reactant gas at 720˚C. As a blocking oxide, 13-nm thick Al2O3 was deposited via thermal atomic layer deposition (ALD) using a trimethylaluminum (TMA) precursor and H2O as a reactant gas at 350˚C. Before CVD W deposition, 10-nm thick TiN was deposited via plasma enhanced ALD (PE-ALD) using a TEMA-Ti precursor with NH3 plasma at 230˚C. This TiN layer served as an adhesion and barrier metal. Finally, 70-nm thick W was deposited via thermal-CVD with a two-step deposition process. W was nucleated using the SiH4 reduction of the WF6, and the bulk W was subsequently deposited via the H2 reduction of the WF6 at 430˚C for 7 min. To compare the Fcontaining CVD W memory device, F-free PVD W memory device was also fabricated. After the memory gate stack was completed, the gate area was defined using dry etching, followed by an annealing process at 900˚C for 1 sec. 100-nm thick Al was deposited on the source and drain regions via the PVD process to improve the electrical contact. Finally, forming gas annealing (FGA) was performed at 410˚C for 30 min. 4
3. Results and discussion
Figure 1. Back-side SIMS profiles of Si, Al, Ti, W, O, N, and F in CTF memory stack with (a) PVD W and (b) CVD W after an annealing process at 900˚C for 1 sec Figure 1 shows the back-side SIMS profiles of Si, Al, Ti, W, O, and N, as well as the residual F in the CTF memory stack with PVD W and CVD W after the annealing process at 900˚C for 1 sec. It was found that the residual F in the CVD W diffused and accumulated in the TiN layer at the as-deposited condition [9]. This F in the TiN and CVD W further diffused into the CTF memory stack and remained to a significant extent in the Al2O3 and Si3N4. Furthermore, the diffused F was also found in the SiO2 and the interface at the poly-Si/SiO2 after annealing at 900˚C for 1 sec. Unlike the CTF memory stack with CVD W, the F concentration in the PVD W memory stack constituted insignificantly low noise levels.
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Figure 2. Cross sectional STEM images of CTF memory stack with (a) PVD W and (b) CVD W after an annealing process at 900˚C for 1 sec. Figure 2 shows a comparison of the STEM images of a CTF memory stack with PVD W and CVD W. The results demonstrate that the thicknesses of the Al2O3 and Si3N4 in the CVD memory were comparable to those of the PVD memory. On the other hand, the SiO2 thickness in the CVD W memory increased by around 10% over that of the PVD W memory. This increase was presumably due to the F incorporation, which was also reported by several groups [10, 11]. These groups proposed that the diffused F atoms reacted with the locally strained Si/SiO2 interface, which broke the Si-O bonds and released the O atoms. These atoms in turn caused the re-oxidization of the Si/SiO2 interface and thereby increased the SiO2 thickness. The increase in SiO2 thickness with the residual F in this work suggested that diffused F atoms reacted with the locally strained interface at the poly-Si/SiO2, and it thereby re-oxidized the poly-Si/SiO2 interface in the CTF memory stack.
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Figure 3. (a) Program/erase speed of CTF memory transistors with PVD W and CVD W metal gates. (b) Energy band diagram of CTF memory device during erase operation. The F effects on the memory stack were further investigated using CTF memory transistors. Figure 3 shows a comparison of the program/erase (P/E) characteristics of the CVD W memory and PVD W memory. The results show that the P/E speed and memory window with the CVD W memory degraded compared to the PVD W memory. Interestingly, the results in the present study, the F remained in the tunneling SiO2 and poly-Si/SiO2 interface, were inconsistent with previous findings where F did not diffused into the tunneling SiO2 and poly-Si/SiO2 interface [9]. It is presumed that the F in the tunneling SiO2 and poly-Si/SiO2 interface caused this discrepancy, as will be discussed with the experimental results below. It was presumed that the increased SiO2 thickness and decreased dielectric constant of Al2O3 by F incorporation led to lower applied filed on the tunnel oxide in the CVD W memory, compared to that in the PVD W memory. Figure 3(a) also showed that erase window in the CVD W memory was significantly degraded compared to the program window, which was related to the erase saturation. In general, an erase saturation phenomenon occurs when the electron back-tunneling current (J1), electron de-trapping current (J2), and hole injection current (J3) reaches dynamic equilibrium (J1=J2+J3), as shown in figure 3(b) [12]. In the present study, when the gate-substrate voltage of -21V was applied to both the 7
CVD W and PVD W memories during the erase operation, the electric field applied to the blocking oxide of the CVD W and PVD W memories were comparable. On the other hand, electric field applied on tunnel oxide was -12.1 (MV/cm) in PVD W memory and -11.3 (MV/cm) in CVD W memory. Smaller applied electric field on tunnel oxide of CVD W memory leads to reduce J2 and J3 than PVD W memory. Eventually, erase saturation is occurred at lower delta VT in CVD W memory because J1 increases as pulse width time increases. The decrease of dielectric constant of Al2O3 will be demonstrated further in figure 6.
Figure 4. (a) Retention characteristics of CTF memory transistors with PVD W and CVD W metal gates. (b) Energy band diagram of CTF memory device during programmed retention state and (c) erased retention state. 8
Figure 4(a) shows the charge-retention characteristics of the CTF memories with PVD W and CVD W in programmed/erased states over time at different temperatures. The results showed that the charge-loss in the CVD W memory was higher than that in the PVD W memory in both the programmed and erased states regardless of measurement temperatures. To understand the charge-loss mechanism in the CVD W memory, several possible electron-loss paths in the programmed state were described and discussed in figure 4(b). Electron de-trapping through tunnel oxide (①) was improbable considering retention result because of greater thickness and lower oxide trap density of SiO2 in CVD W memory. The trap density of the tunnel oxide was further reduced by the F incorporation, which is demonstrated in further detail in figure 9. The hole injection (③, ④) was also neglected due to the large valence band offset. Thus, the poor programmed retention characteristics of the CVD W memory at room temperature (RT) could be explained by the trap-assisted tunneling (②) via the electron trap sites in the blocking of the CVD W memory, as shown in figure 4(b). The electron-trap sites were generated by the F incorporation, which will be demonstrated further in figure 6. This explanation is well supported by previous studies [13, 14], which claimed that the blocking oxide was the main path of the charge-loss instead of the tunnel oxide in the programmed retention of the CTF memory. For elevated temperatures, thermionic emissions (⑤) are dominant charge-loss mechanism that are highly affected by the band offset and trap energy depth of the charge trap layer (Si3N4) [15, 16]. For the present study, this implies that shallow-level electron-trap sites were generated in the Si3N4 due to the incorporation of F, which affected the charge-loss mechanism at the elevated temperature. Figure 4(c) shows the several possible paths of the hole-loss in the erased state. Similar to the programmed state, the charge-loss through the tunnel oxide (①, ③) was negligible, but the electron injection from the gate (②) was possible. The de-trapping of holes through the blocking oxide (④) also contributed to the retention properties in the erased state. These results implied that not only the electrons, but also the holes affected the charge retention properties of the CTF memory, which will be 9
further discussed below.
Figure 5. Charge loss after 104 sec in program- and erase-state retention tests at room temperature
Figure 5 shows a comparison of the delta VT in the programmed and erased states of the PVD W and CVD W memory after 1000 sec at room temperature. While the delta VT values in the PVD memory were indistinguishable in each state, the delta VT values in the erased state were much higher than those in the programmed state in the CVD W memory. This indicated that an additional charge-loss path was involved in the erased state of the CVD W memory, unlike in the P/E retention properties of the PVD W memory. The additional charge-loss was presumably due to the hole-trap sites in the Al2O3, as shown in Figure 4(c). Normally, under elevated temperatures, the thermionic emission (⑤) of the holes will dominate the charge-retention in the erased state. Thus, the poor retention-property of the CVD W memory compared to the PVD W memory could be explained by the generation of the shallow-level hole-trap sites in the Si3N4 caused by the F diffusion in the CVD W memory.
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Figure 6. (a) Capacitance-voltage curves (frequency = 100 kHz). The 27-nm thick Al2O3 was deposited via the thermal ALD, and it was subsequently annealed at 900˚C for 1 sec. (b) Gate leakage current of MOS capacitors with PVD W and CVD W metal gates as a function of the applied electric field on oxide. Negative bias was applied to the gate. To further investigate the charge retention behavior through the blocking oxide at RT, metal-oxidesemiconductor (MOS) capacitors consisting of a W/TiN/27-nm thick Al2O3/p-type Si substrate were fabricated, as shown in the inset of figure 6(a). Figure 6 (a) shows the capacitance-voltage (CV) curves of the CVD W and PVD W capacitors. The results showed that the accumulation value of the CV curve of the CVD W capacitor was smaller than that of the PVD W capacitor. It was inferred that this reduction in the capacitance value in the CVD W capacitor was due to the decreased dielectric constant of the Al2O3 via F incorporation because the AlOxFy could be partially formed in the Al2O3 via the residual F incorporation. Of note, the AlF3 dielectric constant was about 6.0 [17]. The Al2O3 in the PVD W capacitor was extracted to be about 9.58, while that in the CVD W capacitor was about 9.06. Figure 6(b) shows the gate leakage current of the MOS capacitors with the PVD W and CVD W metal gates as functions of the electric field. The CVD W capacitor showed a higher leakage current at the low field region, indicating that the additional charge conduction path was generated due to the F incorporation. The generation of electron traps in the Al2O3 degraded the retention characteristics. The lower leakage current of the CVD W compared to the PVD W at the high field region was caused by the trapped charges that prevented further leakage conduction. 11
Figure 7. The endurance characteristics of the CTF memory transistors with PVD W and CVD W metal gates. Next, the endurance characteristics of the CTF memories with the PVD W and CVD W were compared depending on the number of P/E cycles, as shown in figure 7. In contrast to the P/E speed and data retention behaviors, the CVD W memory showed better endurance characteristics than the PVD W memory. Cycling tests are known to degrade memory performance mainly due to the trap generation in the tunnel oxide and tunnel oxide/channel interface [18, 19]. Thus, it was inferred that the F incorporation in the tunnel oxide reduced the trap generation in the tunnel oxide and tunnel oxide/channel interface, which will be demonstrated further in Figure 8 and 9. Likewise, reductions in interface trap density (Dit) and improvements in the charge to the breakdown (QBD) distribution of the SiO2 via F incorporation have also been reported [10, 11].
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Figure 8. Charge-transfer characteristics of the CTF memory transistors with PVD W and CVD metal gates. (a) Drain current as a function of gate voltage (b) Extracted field effect mobility from transconductance. Figure 8(a) shows the charge-transfer characteristics of the CTF transistor with PVD W and CVD W. The subthreshold swings (SSes) of the PVD W and CVD W transistors were 446 and 384 mV/decade, respectively. The SS distributions of the PVD W and CVD W are shown in the inset of figure 8(a). In addition, the field-effect electron mobility (μ) was also compared, as shown in figure 8(b). The fieldeffect peak mobility of the PVD W and CVD W memory transistors were 8.35 cm2/Vs and 11.09 cm2/Vs, respectively. These results indicated that the CVD W memory showed improved SS and μ values over the PVD W memory, and the CVD W transistor showed reduced trap generation in the tunnel oxide and tunnel oxide/channel interface caused by the F incorporation.
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Figure 9. Depth profile of charge-trap density as a function of energy inside the TO. The interface of the poly-Si channel/TO is position x=0. To correlate the charge-transfer characteristics shown in figure 8, AC-gm measurements were performed, and the trap distributions of the tunnel oxide in terms of energy and depth were extracted [20]. The position of the oxide trap (x) from the interface was expressed via electron trapping and de-trapping along the frequency shown in Eq. (1).
x = λln
( ) 1 ωτ0
(1)
where λ is the tunneling distance, ω is the frequency, and τ0 is the trap time constant when x=0 and ET=EF. Meanwhile, the trap energy from the conduction band of the poly-Si channel was expressed as shown in Eq. (2) where ET is the trap energy level, and x0 is the total thickness of the gate dielectric.
x 𝑥0
ET - EF = (VG,dc - VT)
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(2)
Finally, the trap density was extracted by differentiating the measured AC-gm with the frequency, as shown in Eq. (3). dgm Not(ET,x) ≈
dlnω x W x 1― qλVDμdc x0 L x0
(
)
(3)
By using these equations, tunnel oxide trap density as a function of energy and depth was extracted, as shown in figure 9. The CVD W memory showed a reduced charge-trap density than the PVD W memory. As mentioned, the diffused F in the tunnel oxide in the CVD W reduced the charge-trap density in the tunnel oxide and improved the hot-carrier immunity in the CTF memory transistor.
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4. Conclusion CTF memory stacks with Al2O3/Si3N4/SiO2/poly-Si substrate stacks were systemically compared with PVD W and CVD W. It was found that the residual F in the CVD W diffused into the Al2O3, Si3N4, SiO2, and SiO2/poly-Si interface after the subsequent annealing process at 900˚C for 1 sec. The diffused F in the Al2O3 generated charge-trap sites that became a major charge-loss path during the retention test at room temperature. The residual F in the Si3N4 was responsible for the poor-retention characteristics at the elevated temperature in the CVD W. The SiO2 thickness in the CVD W increased due to the diffused F, which degraded the program and erase speed, and eventually the memory window. The diffused F in the SiO2 also reduced the SiO2 trap density, which was evidenced using an AC-gm analysis. This reduced trap density in the SiO2 caused by the diffused F was responsible for the improved charge-transfer behavior in the CVD W transistor compared to the PVD W transistor.
Acknowledgements This paper was the result of a research project funded by SK Hynix Inc, Icheon-si, Korea.
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Byung Jin Cho (M’97–SM’01) received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 1985 and the M.S. and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1987 and 1991, respectively. From 1991 to 1993, he was with Interuniversity Microelectronics Center, Leuven, Belgium, as a Research Fellow, where he worked on advanced silicon processing. From 1993 to 1997, he joined the Memory Research and Development Division, Hyundai Electronics (currently Hynix Semiconductor), Ichon, Korea, as a Section Manager, where he led a research team for the process development for 256Mb and 1G dynamic random access memory and Flash electrically erasable programmable read-only memory (EEPROM). In 1997, he joined the Department of Electrical and Computer Engineering, National University of Singapore (NUS), as a Faculty Member. Since 2007, he has been with the Department of Electrical Engineering, KAIST, as a Faculty Member. His main research interests are advanced complementary metal–oxide–semiconductor device and front-end process technology, memory devices, graphene-based devices, graphene synthesis and process, thermoelectric generator devices, and flexible electronics. He has published over 456 technical papers. He is the holder of over 33 patents.
Highlights: •
Investigation of Fluorine effects on flash memory characteristics and transfer characteristics.
•
Analysis of Fluorine effects on each gate stack by Secondary Ion Mass Spectroscopy (SIMS), Transmission Electron Microscopy (TEM), and AC-Transconductance method.
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