Microelectronics Reliability 53 (2013) 1450–1455
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Analysis of Schottky gate degradation evolution in AlGaN/GaN HEMTs during HTRB stress L. Brunel a,b,⇑, B. Lambert a, P. Mezenge a, J. Bataille a, D. Floriot a, J. Grünenpütt d, H. Blanck d, D. Carisetti c, Y. Gourdel c, N. Malbert b, A. Curutchet b, N. Labat b a
United Monolithic Semiconductor, 10 Av du Québec, 91140 Villebon-sur-Yvette, France IMS, CNRS UMR 5218 – Université Bordeaux 1 - 351, Cours de la Libération, F-33405 Talence, France Thales R&T, 1 Av Auguste Fresnel, 91767 Palaiseau Cedex, France d United Monolithic Semiconductor, Wihlelm-Runge-Strasse 11, 89081 Ulm, Germany b c
a r t i c l e
i n f o
Article history: Received 5 June 2013 Received in revised form 8 July 2013 Accepted 18 July 2013
a b s t r a c t GaN based technologies are promising in terms of electrical performances for power and high frequencies applications and their reliability assessment remains a burning issue. Thus, a good understanding of their degradation mechanisms is required to warranty their reliability. In this paper, an electrical parasitic effect has been observed on the gate–source diode forward characteristics of a set of devices under HTRB stress carried out at 175 °C up to 4000 h. This parasitic effect has been attributed to lateral surface conduction and correlated with EL signature under diode forward biasing conditions but not under transistor pinch-off biasing conditions. Then, physical analyses have pointed out the formation and growing over time of pits and cracks at the gate edge on the drain side. Ó 2013 Elsevier Ltd. All rights reserved.
1. Introduction GaN based technologies are promising in terms of electrical performances for power and high frequencies applications [1] and their reliability assessment remains a burning issue. After qualifying the first AlGaN/GaN technology in Europe [2], UMS is actually working on the qualification of a second GaN based technology called GH25-10. Thus, a good understanding of their degradation mechanisms is required to warranty its reliability. Several papers report on failure mechanisms in AlGaN/GaN HEMTs that are activated by the electric field in the devices such as the inverse piezoelectric effect [3], percolation traps [4] or TDDB mechanism [5]. All locations of these effects are surrounding the gate area. The defects are either generated (as pits) at the edge of the gate foot or activated (as traps) in the epitaxy by electrical stress, inter-diffusion or mechanical stress voiding at the gate metal/epitaxy interface. Traps located at the passivation/epitaxy interface also affect the HEMT performances as they may induce lagging effect. In the present paper, a HTRB test has been applied to a set of devices. Devices were extracted at different interim aging times to be submitted to electrical measurements and physical analysis. In particular, a soft chemical delayering process was developed to
⇑ Corresponding author at: United Monolithic Semiconductor, 10 Av du Québec, 91140 Villebon-sur-Yvette, France. Tel.: +33 169863235. E-mail address:
[email protected] (L. Brunel). 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.07.095
check possible surface degradation. It aims to correlate electrical degradation with potential physical defect.
2. Technology description The GH25-10 technology is based on an AlGaN/GaN epitaxy on SiC substrate with a Pt/Au gate length of 0.25 lm and a 22 nm AlGaN layer thickness of 22% Al content. This technology intends to cover high power and wide band frequency range applications up to Ku band for telecom and defence markets. Studied AlGaN/GaN HEMTs present a 8 125 lm-finger gate topology, standard ohmic contacts, a silicon nitride passivation and a source terminated field plate.
3. Experimental and sample preparation details AlGaN/GaN HEMTs were stressed in off-state conditions at VGS = 7 V and VDS = 30 V during 4000 h with a base plate temperature of 175 °C to evaluate the Schottky contact stability over time. Electrical interim measurements were performed in DC on both reference and stressed devices at different aging times to follow the evolution of IV characteristics and of the main electrical parameters such as IDSPLS (measured at VGS = 1 V and VDS = 10 V), VTh (measured at IDSS/100 and VDS = 10 V) and the gate leakage current IGLHV (measured at VGS = 7 V and VDS = 30 V). Then, devices with different electrical parameters evolution were removed from the stress test at 600 h, 2000 h, 3000 h and 4000 h to perform com-
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parative analysis by means of emission microscopy (EMMI) and material removal (delayering) for SEM observation of the surface. Electroluminescence analyses in Visible–Near Infrared range (400–1000 nm) were carried out in two operation modes: in off state mode (VGS = 7 V and VDS = 30 V) in order to detect the leakage paths [6] and in diode mode in both forward and reverse conditions to check the Schottky contact integrity. As source terminated fieldplate and source air bridges disturb the front side observation of the whole active area of the HEMTs, these analyses were performed from back side after a sample preparation which consists in package removing and SiC substrate mirror polishing. Then physical analysis has been performed by global delayering of the die to observe pit and groove evolution due to HTRB stress at the surface of the active area [7–13]. The etching procedure employed is carried out as follows: first, the passivation layer is removed up to the field plate using a SF6/O2 plasma and then KCN solution at 60 °C is used for etching electroplated and evaporated gold. Additional solutions like HF at room temperature and Aqua Regia (HCl/HNO3 – 3/1 parts) at 70 °C are employed for dielectrics and metals removal down to the substrate. It is important to note that no oxidizing solution was used to limit delayering artefact such as pits expanding phenomena. Then, the surface of the dies under study is observed with FESEM S4800 Hitachi (Field Effect Scanning Electron Microscope) to locate pits and grooves in the active area, which are easily localizable thanks to the surface roughness of drain and source contacts region. Then defects are carefully located with regard to the edge of ohmic contacts.
IDSPLS drift [%]
0 -5 -10 -15 -20 1
10
100
1000
10000
Time [hours] -3
V Th [V]
-3.1 -3.2 -3.3 -3.4 -3.5 1
10
100
1000
10000
IGLHV [µA/mm]
Time [hours] 0 -20 -40 -60 -80 -100 1
10
100
1000
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Time [hours] Fig. 1. Evolution of IDSPLS, VTh and IGLHV during 4000 h of HTRB test for: reference devices (black), devices presenting after 24 h of aging test, |IGLHV| > 20 lA/mm (red) and |IGLHV| < 20 lA/mm (green). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
4. Failure analysis results 4.1. Electrical measurements Fig. 1 shows the evolution of main electrical parameters over time of stressed devices and reference ones (not stressed). After 4000 h of HTRB stress test, no failure is observed. Indeed, the evolutions of the main electrical parameters such as VTh or IDSPLS are below 20% and |IGLHV| is below 200 lA/mm, which is the failure criteria used at UMS for the reverse leakage current of the HEMT. While |IGLHV| remains below 200 lA/mm, two types of evolution are pointed out at the first interim measurement performed after 24 h of HTRB test: 5 devices exhibit an increase of |IGLHV| above 20 lA/mm after 24 h and then a continuous decrease the rest of the time whereas the other 5 devices only show a slight decrease over the 4000 h aging test. Looking more in detail the electrical characteristics, it appears, for one group of devices (in red), a gate leakage current in excess at low current injection on the Schottky diode forward characteristic (Fig. 2) which is so called ‘‘belly shape’’ (BS). Fig. 2 shows the Schottky diode forward characteristics measured with drain and source shorted to the ground, before and after 4000 h of HTRB stress of a device exhibiting BS and another one
without BS. Note that BS is also observed on both gate–source and gate–drain diodes in forward mode. Even if no failure was observed up to now on devices exhibiting BS, BS is a parasitic effect which origin is unknown and a full comprehension of this phenomenon is necessary to warranty reliability of the technology as it could reveal the presence of critical physical defect in the structure. At this step of the analysis, this Schottky gate diode degradation is supposed to be due either to a double barrier height [8], an ohmic conduction path (metal migration or physical defects) or traps. Then, further investigation is required. Fig. 3 shows the evolution of the Schottky diode forward characteristic of a device presenting BS during the HTRB test. According to Fig. 3, BS appears after only few hours of aging test and the evolution of its magnitude seems to be unpredictable as for example for this particular device: it first increases up to 1000 h then decreases. This suggests that the degradation is induced by a change in the gate metal/epitaxy interface and/or surface states activity over the time. Moreover, BS disappears above VGS = 1 V which is below the value at which the series resistance impacts
1.E-03
1.E-03
1.E-04
1.E-04
1.E-05
IG [A]
IG [A]
5
Before stress
1.E-06 1.E-07 After stress
1.E-08 1.E-09
After stress
1.E-05 Belly shape
1.E-06 1.E-07
Before stress
1.E-08 1.E-09
0
0.5
1
VGS [V]
1.5
0
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1
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VGS [V]
Fig. 2. Schottky diode forward characteristics with drain and source shorted to the ground of a HEMT with (right) and without (left) BS before (blue) and after (red) 4000 h of HTRB stress. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
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1E-09
IG [A]
1.E-04
- ²
1.E-03 After 1000h
1.E-05
After 4000h
1.E-06 1.E-07
After 24h
1.E-08
Before stress
1.E-09
1E-10 1E-11 1E-12 1E-13
0
0.5
1
1.5
10
100
VGS [V] Fig. 3. Evolution of the Schottky diode forward characteristic with drain and source shorted to the ground during the HTRB test.
the diode IV characteristic. Thus, BS could be due to lateral surface leakage currents assisted by surface states in AlGaN [9]. Indeed, the effect of a parallel surface resistance decrease appears at lower current level, leading to a change in the slope of the Schottky diode forward characteristic. This last hypothesis has been verified by comparing the Schottky diode reverse characteristic from 0 to 10 V of a device with BS and another one without BS (Fig. 4). According to Fig. 4, an increase of the gate leakage current is observed on devices with BS at low VGS which would confirm previous assumption. Note that a simple ohmic path is not considered here because the forward characteristic cannot be fitted using only the thermionic emission model and a parallel leakage resistance [10]. By analysing monitored gate current during the HTRB test, the evolution of the gate current of devices presenting BS is found to be noisier than the one of devices without BS. Then, gate current variance versus time has been calculated over 50 h averaging as follows to quantify the gate current fluctuations:
Var½IGS ðtÞ50hrs ¼ hIGS ðtÞ2 i50hrs hIGS ðtÞi250hrs
ð1Þ 2
With t the time elapsed during stress test, hIGS(t) i the average over 50 h of square of gate current and hIGS(t)i2 the square of average gate current over 50 h. Fig. 5 shows the gate current variance evolution during the stress test. In Fig. 5, the gate current variance of devices with BS is roughly 1 decade above the one of the device without BS. 4.2. Vis–NIR electroluminescence measurements
10000
Fig. 5. Gate current variance evolution over time during HTRB test of devices with (red) and without (green) BS. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
spots also visible from the front side (yellow arrows), spots partially hidden by air bridges in front side (red arrows) and an additional spot completely masked by air bridges in front side (purple arrow). Thus, only images obtained from back side analysis are used here to analyze the EL signature of devices after aging test. To compare the EL signature of devices at the same bias conditions, the measurements are made using the same acquisition time (100 s) and the images are displayed with the same level range of intensity. Also, it should be noted that some precautions have to be taken concerning the intensity of each emission light spot as the EL intensity and the electric field do not relate linearly [11]. Thus, we suppose that large and bright emission light spots are rather related to intrinsic crystal defects or local change in electric field [12] and that small ones correspond to leakage current path or defects created during stress test. This hypothesis has been confirmed as large bright spots (such as the ones indicated by red arrows in Fig. 6 appear on fresh devices even if the leakage current is weak. Then, only small emission light spots will be considered for a comparative analysis in this work. The comparative EL analysis of reference and aged devices in pinch-off conditions (Figs. 6–8) show an increase of the number of small emission light spots. This observation is correlated with both an increase of sub-threshold drain current (in off-state conditions) measured during the EL measurement and stress time but not with the evolution of |IGLHV|. Thus, these small spots could reveal the presence of new defects created during the HTRB test. According to Fig. 8, emission light spots are located at the edge of the drain side of the gate foot, i.e. where the electric field is the highest during the stress test, suggesting the presence of defects due to the electrical field [13]. Then EL measurements have been performed in reverse mode on both the gate–source diode (at VGS = 7 V) and the gate–drain diode (at VGD = 30 V) to compare with the leakage paths observed in pinch-off conditions. Fig. 9 shows the back side Vis–NIR EL signature on the gate–drain diode in reverse mode of aged devices. The comparison of EL signatures obtained on gate–drain diode (Fig. 9) and on transistor in pinch-off conditions (Fig. 7) highlights common light emission spots, showing that the EMMI signature
1.E-04
1.E-04
1.E-05
1.E-05
|I G | [A]
|I G | [A]
Front side and back-side electroluminescence (EL) analysis is used to detect the leakage paths that could reveal defects responsible for the occurrence of the belly shape. Because of the transistor topology (fieldplate and air bridges), the complete EL signature of a reference device is obtained from back side through the substrate after sample preparation (Fig. 6). The impact of the back side preparation is verified by comparing back side and front side EL signatures and DC currents at the chosen biasing point. Back side EL signature includes emitted light
After stress 1.E-06 1.E-07
1000
Time [hours]
After stress
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Before stress
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-8
-6
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VGS [V]
-2
0
-10
-8
-6
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0
VGS [V]
Fig. 4. Schottky diode reverse characteristics with drain and source shorted to the ground of a HEMT with (right) and without (left) BS before (blue) and after (red) 4000 h of HTRB stress. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
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Fig. 6. Front side (left) and Back side (right) EL microscopy images of a reference device VDS = 30 V; VGS = 7 V; IDS = 5 lA.
obtained in pinch-off conditions is dominated by the gate–drain diode. On the contrary, the EL signature of the gate–source diode obtained at VGS = 7 V (not shown) presents a low leakage current (<1 lA) and no visible spots considering the camera sensibility and the wavelength range. Then additional tests have been performed on the gate–source diode (Fig. 10) and on the gate–drain diode (Fig. 11) in forward mode to detect potential differences between devices with and without belly shape. It has been found on both gate–source and gate–drain diodes that light emission of a diode without BS is relatively uniform along each gate finger and of similar intensity from a finger to another one, whereas the EL signature of diodes exhibiting BS is very different. Indeed, hot spots and inhomogeneous emission light along the gate fingers were observed in the last case, which could reveal a non uniformity of the Schottky contact along the fingers. In this case, the emission intensity seems to be closely related to current level. Thus, we can suppose here that hot spots allow localizing leakage gate current in excess and so physical defects responsible for the belly shape.
4.3. Front side delayering Physical analysis has been performed by a global delayering of the devices to correlate electrical degradation with potential physical defects. Fig. 12 shows the top view SEM observation of the gate region after removal of SiN dielectrics and metal of a device after 2000 h of HTRB test. The SEM observation reveals a row of pits along the gate edge on its drain side and the presence of a crack between pits.
3000hrs; no BS
3000hrs; BS
4000hrs; no BS
4000hrs; BS
Fig. 7. Back side EL microscopy images of aged devices VDS = 30 V; VGS = 7 V; IDS = 6/9/6/9,5 lA.
Fig. 8. Back side EL microscopy images of a reference (up) and an aged device (down) VDS = 30 V; VGS = 7 V, IDS = 5 lA (reference), IDS = 9 lA (3000 h – BS).
By comparing several SEM images of devices at different aging times (Fig. 13); it has been found that the number of pits increases with the HTRB stress time and that the formation of cracks is progressive during the HTRB stress test. Indeed, pits appear after 600 h on 1 gate finger of one device and after 2000 h on 5 gate fingers of another one. However, no obvious difference has been found between devices with or without BS. So, we assume that the presence of belly shape is not linked with the appearance of pits and cracks along the gate edge. Interestingly, crystal defects have been found below the fieldplate in the gate–drain region after 3000 h of aging test (Fig. 14). The formation of pits and cracks has mainly been attributed in the literature to the inverse piezoelectric effect [3,5,14–16] or to a diffusion process enhanced by the inverse piezoelectric strain [17].
5. Discussions In the present case, the formation and growing over time of pits and cracks along the edge of the gate foot seems to be correlated to the evolution of VTh rather than |IGLHV| or IDSPLS as often reported [3–7] because of their different evolution with aging time. Thus, the following degradation mechanism is proposed. The application of high gate–drain voltage leads to a high electric field at the edge of the gate foot on its drain side. Then pits and cracks appear at the drain side of the gate foot edge due to inverse piezoelectric strain, which leads to a shift of the threshold voltage toward 0 V. Because of the formation of defects, the electric field locally decreases near the gate foot, leading to a decrease of leakage current (|IGLHV|) and to a reduction of mechanical strain in
30000hrs; no BS
30000hrs; BS
40000hrs; no BS
40000hrs; BS
Fig. 9. Back side EL microscopy images of aged devices on Gate-drain diode (source open) in reverse mode VGD = 30 V; IGD = 2.2/9/0,7/5,6 lA.
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3000hrs; no BS
3000hrs; BS
4000hrs; no BS
4000hrs; BS
Fig. 10. Back side EL microscopy images of aged devices on the gate–source diode (drain open) in forward mode; VGS = 1.3 V; IGS = 190/250/65/250 lA.
3000hrs; BS
4000hrs; BS
Fig. 11. Back side EL microscopy images of aged devices on the gate–drain diode (source open) in forward mode; VGD = 1.3 V; IGD = 350/250 lA.
Fig. 14. Top view SEM images of the active area region after dielectrics and metal removal of devices after 3000 h (up) and 4000 h (down) of aging test.
edge of the fieldplate, causing the appearance of crystal defects below the fieldplate. Concerning the evolution of |IGLHV| we suppose that the appearance of the belly shape after 24 h, attributed to lateral surface leakage currents, also leads to an increase of the gate leakage current in pinch-off conditions. Then, it decreases with the reduction of the electrical field near the gate foot because of defect formations. 6. Conclusions
Fig. 12. Top view SEM image of the gate region after dielectrics and metal removal of a sample after 2000 h of HTRB.
0hrs; no BS
600hrs; no BS
2000hrs; no BS
2000hrs; BS
Fig. 13. Detailed top view SEM images of the gate region after dielectrics and metal removal of aged devices for different aging times.
the AlGaN layer. This strain reduction may lead to a change of piezoelectric charges and then shift the electric field peak toward the
As a conclusion, no failure was observed up to 4000 h of HTRB test proving the robustness of the GH25 technology. An electrical parasitic effect, so called belly shape, has been observed on the diode forward characteristics and attributed to lateral surface conduction. The belly shape has been correlated with EL signature under forward diode biasing conditions but not under transistor pinch-off biasing conditions. Thus, TEM lamellas along gate fingers where EL signature presents hot spots have to be performed to conclude on its physical origin. Also, no different time to failure has been observed between device with and without belly shape. Physical analyses have pointed out the formation and growing over time of pits and cracks, attributed to the inverse piezoelectric effect, at the drain side of the gate foot edge. These pits and cracks have been correlated with the VTh degradation but not with the gate leakage current evolution. Also, the comparative EL analysis of reference and aged devices in pinch-off conditions shows an increase of the number of emission light spots at the gate foot edge on the drain side, which can be correlated to the increase of the number of pits during the test. Then, crystal defects have been found after 3000 h of aging test near the edge of the fieldplate in the gate–drain region. However, the appearance of these defects has not been correlated to any electrical failure or degradation up to now.
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Acknowledgements The authors would like to thank the French (DGA) and German (BWB) Ministries of Defence for financial support and ANR for the funding ReAGaN program research. References [1] Floriot D et al. New qualified industrial AlGaN/GaN HEMT process: power performances & reliability figures of merit. EuMWC 2012. [2] Lambert B et al. Reliability data’s of 0.5 lm AlGaN/GaN on SiC technology qualification. Microelectron Reliab 2012;52:2200. [3] del Alamo JA, Joh J. GaN HEMT reliability. Microelectron Reliab 2009:49. [4] Marko P et al. IV, noise and electroluminescence analysis of stress-induced percolation path in AlGaN/GaN high electron mobility transistors. Microelectron Reliab 2012;52:2194. [5] Marcon D et al. Reliability of AlGaN/GaN HEMTs: permanent leakage current increase and output current drop. Microelectron Reliab 2012;52. [6] Baeumler et al. Investigation of leakage current of AlGaN/GaN HEMTs under pinch-off condition by electroluminescence microscopy. J Electron Mater 2010;39. [7] Makaram P et al. Evolution of structural defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors. Appl Phys Lett 2010;96:233509.
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