Analytical drain current and threshold voltage model and device design of short-channel Si nanowire transistors

Solid-State Electronics 86 (2013) 27–31

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Analytical drain current and threshold voltage model and device design of short-channel Si nanowire transistors Chika Tanaka a,⇑, Daisuke Hagishima a, Ken Uchida a,b, Toshinori Numata a a b

Advanced LSI Technology Laboratory, Corporate Research and Development Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan Electrical & Electronics Engineering, Keio University, Japan

a r t i c l e

i n f o

Article history: Received 13 July 2012 Received in revised form 7 January 2013 Accepted 15 April 2013 Available online 13 May 2013 The review of this paper was arranged by Dr. Y. Kuk

a b s t r a c t Device design for cylindrical Si nanowire field-effect-transistors is studied in short channel regime of 22 nm technology generations and beyond. A two-dimensional quasi-analytical model reveals that a critical minimum channel length is 1.5 times as long as a Si nanowire diameter to suppress the short channel effects. The quantum mechanical effect due to the structural carrier confinement in nanowire with narrow diameter deteriorates both the threshold voltage roll-offs and the subthreshold characteristics. Ó 2013 Elsevier Ltd. All rights reserved.

Keywords: Silicon nanowire transistor Threshold voltage Analytical model

1. Introduction Silicon nanowire field-effect-transistors (NW Tr.) have been recognized as a promising device structure in short channel regime. NW Tr. realizes the short channel effects (SCEs) immunity due to the electrostatic gate controllability over the channel, which leads to the excellent scalability and the ideal sub-threshold slope [1,2]. Therefore, further voltage scaling with minimizing off-state leakage current as well as high on current is expected for CMOS circuits with ultra-low power operation [3]. In order to obtain high performance operation in the scaling devices, the device design of NW Tr. needs to be clarified. Several analytical studies have been conducted for the gate-all-around (GAA) NW Tr. [4–6]. These papers discussed on the device-geometric effects on the SCEs-related characteristics, such as the threshold voltage (Vth) roll-offs, the drain induced barrier lowering (DIBL), and subthreshold slope in NW Tr. of Lg down to 30 nm. The nanowire diameter (tsi) is a key parameter for the scaling of NW Tr. as well as the gate insulator thickness (tox). Hence, optimum thickness condition combined with both tsi and tox is important in NW Tr. with Lg shorter than 30 nm. In addition, in the study on the device design of NW Tr. with narrow tsi less than 10 nm, the quantum mechanical effect (QME) needs to be considered. The experimental study on FinFET shows that Vth significantly increases with a decrease in the fin width due to QME [7]. Several analytical models ⇑ Corresponding author. Tel.: +81 45 776 5958; fax: +81 45 776 4013. E-mail address: [email protected] (C. Tanaka). 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2013.04.022

on one-dimensional quantum wires were described by the ballistic or drift–diffusion current transport [8,9]. The electrostatics of Si NW Tr. was calculated by using the coupled Schrödinger–Poisson equations in the cylindrical coordinate [10]. For circuit analysis, compact model of silicon-based nanowire MOSFETs had been conducted [11]. In Ref. [11], the solution for the extensive channel doping concentration had been provided by considering Debye length in 3D Poisson–Boltzmann equation. However, the previous calculating method was not sufficient to provide the simple description of device architectures. Therefore, an analytical model including QME in the cylindrical device structure has been waited to be applicable to the device model for device design to realize a well-controlled subthreshold characteristic in NW Tr. In this paper, we study the Vth shifts due to QME as well as SCEs, and the subthreshold characteristics using quasi-analytical model. A simple expression for device design of nanoscaled NW Tr. is also shown. 2. Analytical models on GAA NWFETs 2.1. Analytical drain current model The analytical drain current model of GAA NW Tr. with cylindrical channel will be shown. In this model, gate-induced carriers in subthreshold or weak-inversion regime and QME are ignored. Fig. 1a and b shows the schematic diagrams of undoped Si GAA NW Tr. along the z- and r-direction, respectively. The electrostatics of the device with non-doped channel is represented by the Laplace equation in the cylindrical coordinate

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C. Tanaka et al. / Solid-State Electronics 86 (2013) 27–31

in this case. On the other hand, in case of Lg/kn  1, the influence of kn on Lg is to be significant due to strong two-dimensional effects. In this study, kn were numerically extracted. Fig. 2 shows Lg dependence on calculation results of DIBL using Eq. (3). DIBL increases as Lg scaling by the influence of potential drop in the drain edge. However, DIBL decreases as tsi scaling by the increase of gate controllability, even in short channel region. The drain current (Id) using drift–diffusion approximation can be written as

A

r

Vg

A-A’ Gate

Gate

tsi

Oxide

tox D

S 0

Lg

tox z Vd

tsi Si

Gate

  2pl 1  ebV ds Id ¼ RL b 0 dz Q 1ðzÞ

A’

(a)

(b)

ð5Þ

i

Fig. 1. Schematic diagrams of GAA Si NWFET. Cross sectional view of (a) z-direction and (b) r-direction.

     1 @ @w @ @w þ ¼0 r eðrÞ eðzÞ r @r @r @z @z

ð1Þ

  w t2si þ t ox ; z ¼ V g ; ð2Þ

where Vg is gate-to-source voltage, Vs is source voltage and Vd is drain-to-source voltage. Using these boundary conditions, we calculate w in channel region. The solution of w is given by the Bessel Functions as

    1 X pr p sinh wðr; zÞ ¼ V g þ An J 0 ½Lg  z kn kn n¼1     1 X pr pz þ sinh Bn J 0 k kn n n¼1

tsi 2

rdrni ebwðr;zÞ

ð6Þ

0

where w is a classical electrostatic potential measured from the Fermi level in the source and e is the permittivity of silicon and oxide material. Assuming that the source and drain are composed of the abrupt p–n junction and that the gate electrode has a midgap work function of silicon, the boundary conditions for w are [12]

wðr; 0Þ ¼ V s ; wðr; Lg Þ ¼ V s þ V d ;

Qi ¼

Z

ð3Þ

An and Bn are expressed as

where l is the low field mobility, ni is the intrinsic carrier density, and b = q/(kBT). The gate oxide is assumed to be SiO2 and the dopant concentration is set to be 1015 cm3. In order to verify the analytical model, the calculated results are compared with three-dimensional device simulation. Fig. 3 shows the calculated results of Lg dependence on Vth shift and S-factor, where Vth is defined as Vg at Id of 102 mA/lm in the subthreshold slope calculated by using Eq. (5). The results by our in-house device simulator are also shown. It is confirmed that our calculated results correspond well with the results of device simulation, meaning that our proposed quasi-analytical model will be applicable to Lg down to 10 nm. 2.2. Analytical threshold voltage model The device design is studied by using analytical Vth model obtained as follows. In the subthreshold regime, since the diffusion current is dominant over the drift current, the barrier height of surface potential usually determines the current level. Vth is defined as the electric potential at the position of minimum surface potential (zmin) [15],

V th 

   pa p J 1 kn V s  V g An ¼

h  i2   ; tsi 2 h  p tsi i2 pLg 1 pa 2 J sinh ð 1  C Þ J þ C a n n 1 1 2 kn 2 kn 2 kn

2/B 

kn a

P1   n¼1 An V s þ Bn ðV s þ V d Þ

P   1 1 n¼1 An þ Bn

ð7Þ

An and Bn are expressed as

   

1 p p sinh Lg  zmin J 0 r ; Dn kn kn     1 p zmin p  J0 sinh r ; Bn ¼ Dn kn kn An ¼

   Vs þ Vd  Vg  Bn ¼

h  i2 t 2 h  p t i2 pLg 1 pa si si 2 J ð 1  C Þ J þ C a sinh ; n n 1 kn 2 1 kn 2 kn 2 pa p J 1 kn

kn a

where

where

J0

p tsi

kn

2

t si 2



t si  ; a  tox þ 2 : þa

60

t ox=4nm 50

kn called a scale length [13,14]. In this study, kn is described from the following equation:

J0



p kn



tox þ

 t si ¼0 þa 2

ð4Þ

The expression of kn in our approach is difference from the other previous report [13,14], because kn is calculated under the boundary conditions including the boundary for both radial and channel length direction. We consider kn to be the normalize factor indicating the two-dimensional effects for Lg. In case of Lg/kn  1, the influence of kn on Lg is almost negligible, so the channel region can be independent of the source and the drain regions. Therefore, the one-dimensional gradual channel approximation is applicable

t si=20nm

DIBL [mV/V]

Cn 

 J 0 kpn  

40

t si=10nm 30

t si=3nm 20 10 0 10

20 30 40

50

60

70 80

90 100

Channel length, Lg [nm] Fig. 2. DIBL against channel length. tox = 4 nm and Vd = 1 V.

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C. Tanaka et al. / Solid-State Electronics 86 (2013) 27–31

80

300

70

tox=4nm tsi=3nm Vd=1.2V

100

60

0

50 0

20

40

60

80

100

Channel length, Lg [nm] Fig. 3. Vth roll-offs and S-factor, where Vth is defined as Vg at Id = 102 mA/lm on the subthreshold slope. tsi = 3 nm, tox = 4 nm and Vd = 1.2 V. Symbols indicate the results obtained from the quasi-analytical our model and lines indicate the results obtained from the device simulation.

 ( 2    1 p Lg tsi p tsi 2 Dn ¼ sinh J1 2 kn 2 kn 2   2  2    !) pa tsi p tsi 2 2 :  J1 þ C n a J1 kn 2 kn 2 The Vth roll-offs obtained by Eq. (7) are also in a good agreement with those obtained by device simulator. 2.3. Device designs for GAA NWFETs Fig. 4 shows Vth roll-offs (|DVth|) for various tsi at high Vd of 0.8 V, where Vth is calculated by using Eq. (7). |DVth| determined from the Vth shift normalized using the long channel Vth. Here, the critical |DVth| is assumed to be 100 mV [16]. For the 22 nm technology generation of Lg = 9 nm, tox = 0.5 nm and Vd = 0.8 V, we found that the maximum nanowire diameter (tsi_max) to suppress SCEs is about 4 nm, in which the nanowire diameter is roughly 1/2 of the gate length. Also, S-factor is slightly degraded at |DVth| = 100 mV of Lg = 15 nm. In Fig. 5, the relation between tsi_max and the critical minimum channel length (Lg_min) are shown. Lg_min/k1, a measure of the two-dimensional effects including SCEs [17], is also shown. The slope of DLg_min/Dtsi_max in the scaled GAA NW Tr. is about 1.5. It is also found that Lg_min/k1 in tsi_max > 4 nm regime are independent of tsi_max, which indicates that the superior gate controllability of Si GAA NW Tr. can be achieved in spite of thick tsi.

min



3 t si 2

ð8Þ

max

Eq. (8) is roughly the same as the result for symmetric doublegate FinFET [18]. It is found that the device design of GAA NT Tr. is only expressed by using Eq. (8), because the effective transistor width is determined by tsi. 3. Influence of quantum mechanical effect on threshold voltage When tsi is shrunk, the increase of Vth due to the carrier energy quantization becomes apparent. Assuming the parabolic band structure, the quantization energy for cylindrical well (Ecyl n ) is approximated to 2

Ecyl n ¼

n2 p2 h J 2n;m

ð9Þ

2mr ðtsi =2Þ2

where jn,m is the mth zero of the nth Bessel function of the first kind and mr is the effective mass along the radial direction. In the planar devices, it is well-known that the quantization energy is proportional to 1=t 2si . In the cylindrical case of this study, the quantization energy is proportional to 1/(tsi/2)2. Therefore, Ecyl n becomes significantly large as tsi decreases and is larger than that of two-dimensional quantum well for the same tsi. The influence of QME in GAA NW Tr. makes a big impact on the Vth shift. According to the model proposed by Trivedi and Fossum [19], the Vth shift due to ðQEÞ QME (DV th ) is expressed as ðQEÞ DV th 

S  factor D/ðQEÞ ð1=bÞlnð10Þ

ð10Þ

where D/(QE) means a compensated term due to QME that is obtained from the difference between the classical potential (/) and the quantum one (/QE). Assuming constant inversion-layer charge density, D/(QE) is written as

D/ðQEÞ ¼ /  /QE ¼

E0 1  ln q b

"pffiffiffiffiffiffiffiffiffiffiffiffi 2gmd qE : phNc Lg 1  expðbE tsi =2Þ

X 1 1 ¼ 1 pffiffiffiffiffi

pffiffiffiffiffi þ : expð½E E0 E n 0  En =kB TÞ n

13 pffiffiffiffiffiffiffiffiffiffi 

 g 0 m0d X 1 C7 ¼ 0 qffiffiffiffiffi exp E0  E0n =kBT A5 þ pffiffiffiffiffiffiffiffiffi gmd n E0

ð11Þ

n

80

300

tox=0.5nm Vd=0.8V

tsi=8nm

200

70 65

tsi=4nm

60

100

tsi=1nm

50

55

0 0

10

20

30

40

50 50

Channel length, Lg [nm]

4

50

t =0.5nm ox

40

V =0.8V

~1.5

d

3

|Δ V |=100mV

30

th

20 2

Lg_min / λ1

150

75

Subthreshold Slope [mV/dec]

tsi=10nm

250

|V th roll-offs| [mV]

Lg

Minimum channel length [nm]

Vth roll-off [mV]

200

Subthreshold slope [mV/dec]

symbols: analytical model lines: device simulation

Fig. 6 shows the relation between Lg_min and tsi_max with the different tox, where Vth = 50 mV and Vd = 0.8 V. Lg_min for each tox can be approximated by

10 1

0 0

5

10

15

20

Maximum nanowire diameter [nm] Fig. 4. Vth roll-offs and S-factor at |DVth| = 100 mV with different tsi for tox = 0.5 nm and Vd = 0.8 V. For Lg = 9 nm, tsi_max is needed for 4 nm.

Fig. 5. tsi_max vs. Lg_min and Lg_min/k1 plots are shown at the same conditions in Fig. 3.

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C. Tanaka et al. / Solid-State Electronics 86 (2013) 27–31

200 Lg=9nm

Vd=0.8V

(QE)

10

~3/2

150

5

tox=0.5nm

<110>

Vd=0.8V

100 Device Simulation

th

15

roll-up [mV]

Vth=50mV

ΔV

Minimum channel length [nm]

20

50 <100>

tox=2.0, 1.5, 1.0nm

0 0

0 0

1

2

3

4

5

6

7

5

8

10

15

Nanowire diameter, tsi [nm]

Maximum nanowire diameter [nm] ðQEÞ

DV ðQEÞ th

Fig. 7 shows the roll-ups for tsi in h1 0 0i- and h1 1 0i-Si ðQEÞ ðQEÞ channel-directions, where DV th roll-ups is defined as the DV th ðQEÞ difference from the DV th on tsi = 20 nm. The analytical results correspond well with the results obtained from the device simulation ðQEÞ including QME based on the density gradient model [20]. DV th shift for h1 0 0i-direction becomes significant below tsi  3.5 nm, ðQEÞ indicating that the critical DV th shift is 100 mV. The result implies that the Vth degradation due to SCEs is compensated by the QME in ðQEÞ narrow tsi regime. Also, it is found that the characteristics of DV th ðQEÞ roll-ups exhibit the channel direction dependence, the DV th shift for h1 1 0i -direction is larger than that for h1 0 0i-direction because of the lighter mr in the lower valley for h1 1 0i-direction (see Table 1). Note that similar behaviors have been obtained by the modeling study of DG MOSFETs [21]. Fig. 8 shows Vth characteristics for both the classical and quantum mechanical calculations in tsi of 3 nm and h1 0 0i-channel direction, where symbols and lines indicate the analytical and the device simulation results, respectively. The results obtained from analytical model are in a good agreement with those obtained from the device simulator, down to Lg of 10 nm. For long channel regime, since the quantized energy levels increases, large Vth is required. On the other hand, for short channel regime below Lg of 10 nm, SCEs increases due to the reduction of the gate electrostatic controllability to the channel, since the charge distribution become apart from the Si surface. Therefore, in the short channel NW Tr,

Table 1 Effective mass for r-direction (mr) and DOS effective mass (md). All effective masses are in units of the free-electron mass (m0 = 9.11E31 kg). mr = mt for g = 2 and mr = (m1 + m2)/2 for g = 4 [11]. Channel-direction

h1 0 0i

Electrons Valley/band Degeneracy md [m0] mr [m0]

Lower 2 0.190 0.916

h1 1 0i Higher 4 0.417 0.553

Lower 4 0.324 0.254

Higher 2 0.417 0.190

Threshold voltage, Vth [mV]

ð12Þ

100

quantum mechanical

0

classical

tsi=3nm

-100

tox=1nm -200

0

10

20

30

40

50

Channel length, Lg [nm] Fig. 8. Vth characteristics for both the classical and quantum mechanical calculations for tsi = 3 nm and h1 0 0i-channel direction, where symbols and lines indicate the results obtained from the quasi-analytical our model and the device simulation, respectively.

300

Lg=9nm <110>

t =3nm 200

<100>

ox

Vg ðesi =eox Þ t ox þ t si =2

symbols: analytical model lines: device simulation

th

E

200

δΔV / δt [mV/nm]

where En (E0n ), g (g0 ) and md (m0d ) are the quantization energy, the valley degeneracy and the density of state effective mass in lower (higher) valley (see Table 1), respectively. In order to calculate D/(QE) using Eq. (11), the first 2 subband of each valley are the most prominent part. E is the transverse electric field and is calculated from the following equation:

Fig. 7. DV th roll-ups for tsi in h1 0 0i- and h1 1 0i-Si channel directions. The shaded part shows the region that is easily influenced by the quantum mechanical effect.

ΔVth variations for oxide thickness,

Fig. 6. tsi_max vs. Lg_min plot calculated by the analytical model. The linear relationship between Lg_min and tsi_max is consistent with the relations illustrated in Fig. 4.

100

0 0

1

2

3

Oxide thickness, tox [nm] Fig. 9. Vth variations for tox. The variations tend to saturate at tox  1 nm, which indicates the excellent gate controllability.

operations near the punch-through regime and S-factor are unfavorable. As is understood from Fig. 9, Vth variations for tox tend to saturate around tox of 1 nm because high gate controllability is achieved using thin oxide thickness. The design space for tsi and tox with Lg = 9 nm devices are shown in Fig. 10. In the shaded part of Fig. 10, easily influenced by QME, the thin oxide thickness is available until the gate tunneling limit in order to improve the Vth roll-offs and subthreshold slope characteristics.

C. Tanaka et al. / Solid-State Electronics 86 (2013) 27–31

scaling of tox, rather than tsi, is effective in improving gate controllability and subthreshold characteristics for short channel devices.

7

SiO2 thickness [nm]

31

6

Lg=9nm

5

|ΔVth| =100mV

Acknowledgement

<100>-direction

This work was partly supported by the New Energy and Industrial Technology Development Organization (NEDO) as part of its Development of Nanoelectronic Device Technology project.

4 3 QME 2

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0 0

1

2

3

4

5

6

7

8

Nanowire diameter [nm] Fig. 10. Design space for tsi and SiO2 thickness with Lg = 9 nm devices under the constant Vth roll-offs.

4. Conclusion We demonstrated quasi-two-dimensional analysis in the cylindrical geometry for Si GAA NW Tr. in order to investigate the device design for future LSI. Applying the Laplace’s equation in cylindrical coordinate with two-dimensional boundary conditions, we calculated the electrostatics of GAA NW Tr. At the 22 nm technology generation, it is found that tsi_max needs to be less than 4 nm and Lg_min nearly equals (3/2)tsi_max for tsi> 4 nm, in order to suppress the degradation of S-factor. The results indicate that Si GAA NW Tr. have superior SCEs immunity and high gate controllability down to Lg of 9 nm within tsi<(2/3)Lg. In addition, we investigated the influence of QME induced by the structural carrier confinement on Vth shift. High Vth roll-ups cannot be negligible below tsi nearly equals 3.5 nm and deterioration of Vth roll-offs and subthreshold characteristics are significant below Lg of 10 nm. Therefore, the