Analytical models of subthreshold current and swing of short-channel strained-Si (s-Si) on Silicon–Germanium-on-Insulator (SGOI) MOSFETs

Superlattices and Microstructures 58 (2013) 1–10

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Analytical models of subthreshold current and swing of short-channel strained-Si (s-Si) on Silicon–Germanium-on-Insulator (SGOI) MOSFETs Mirgender Kumar a, Sarvesh Dubey a, Pramod Kumar Tiwari b,⇑, S. Jit a a b

Department of Electronics Engineering, Indian Institute of Technology (Banaras Hindu University), Varanasi 221 005, India Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela 967 008, India

a r t i c l e

i n f o

Article history: Received 13 December 2012 Accepted 27 February 2013 Available online 14 March 2013 Keywords: Silicon–Germanium-on-Insulator (SGOI) MOSFET SCEs Subthreshold current and swing

a b s t r a c t In this paper, surface potential based analytical models of subthreshold current and subthreshold swing of the strained-Si (s-Si) on Silicon–Germanium-on-Insulator (SGOI) MOSFETs have been presented. The models are based on the solution of the 2D Poisson’s equation in the fully depleted channel region by approximating the potential in vertical direction of the channel. The thus obtained potential distribution function has been employed in deriving the closed form expressions of subthreshold current and subthreshold swing. The subthreshold characteristics have been studied as a function of various device parameters such as Ge mole fraction (x), gate length (Lg), gate oxide thickness (tf) and channel thickness (ts-Si). The proposed analytical model results have been validated by comparing with the simulation data obtained by the 2D device simulator ATLAS™ from Silvaco. Ó 2013 Elsevier Ltd. All rights reserved.

1. Introduction The current-edge IC technology is centering on the high speed CMOS devices [1]. It has been observed that scaling of device channel length at nanoscale failed to produce significant improvement in the drain current because of velocity saturation effects [2]. Moreover, the requirement of higher channel doping and vertical electrical field in order to control the severe short-channel effects (SCEs) deteriorates the carrier mobility which adversely impacts the drive current of the device [3]. One possible way, while addressing the challenge of acquiring ameliorated drive current, is to boost up the ⇑ Corresponding author. Tel.: +91 0661 2622467. E-mail address: [email protected] (P.K. Tiwari). 0749-6036/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.spmi.2013.02.012

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M. Kumar et al. / Superlattices and Microstructures 58 (2013) 1–10

carrier transport in the device channel by exploiting channel engineering. For example, strain applied to silicon film may be used to enhance the carrier mobility significantly and thereby increasing the drive current (>35%) [4–9]. Moreover, strained channel devices have also proved its utility in suppressing SCEs effectively with reduced parasitic capacitance [10,11]. Such procured gain in device performance is encouraging the researchers to explore the strained engineered channel MOSFETs comprehensively while keeping pace with latest CMOS scaling trend. In general, there are two methods of introducing strain in the channel: locally or globally. The global method is more popular because of providing uniform strain, termed as biaxial strain, in the channel. This can be achieved by epitaxial growth of Si directly on Si1xGex providing flexibility to control strain in channel by managing Ge content in Si1xGex [12]. Biaxial tensile strain, generated by lattice mismatching between the lattice constants of Si and SiGe, enhances the carrier mobility significantly by causing the band shifts, splitting and effective mass change of conduction electrons in the channel. Electron mobility enhancement in the strained-Si results from lifting of sixfold degeneracy in the conduction band valleys [13]. The four minima of the conduction band of the strained silicon are raised in directions parallel to the plane of strain thereby leading to a higher population of the other two minima vertical to the plane of strain and movement. Such repopulation of electrons causes more electrons with a lower effective mass and higher mobility available for carrier transport under in-plane biaxial strain of the device [14]. The current transport of the s-Si MOSFETs is also enhanced due to the increase in the hole mobility resulted from the splitting of the heavy and light hole bands in the valence band of the s-silicon material. Moreover, the strain-induced valley degeneracy lifting also suppresses inter-valley phonon scattering and increases the electron low field mobility [15]. Clearly, higher mobility leads to faster movement of electrons thereby increasing the drive current in the strained MOS transistors. Among all the reported strained MOS structures, the strained-silicon (s-Si) on Silicon–Germaniumon-Insulator (SGOI) MOSFETs are found very promising for applications in the high speed CMOS devices as they combine the carrier transport advantages of strained-Si with the silicon-on-insulator (SOI) technology [16,17]. Thus, such devices urgently need accurate modeling in order to get better insight into their device behavior for their integration in VLSI integrated circuits. A number of theoretical works based on surface potential and threshold voltage models have been reported on strained-Si SGOI MOSFETs [18,19]. In addition, a number of drain current models for s-Si on SGOI MOSFET and few fabrication and simulation study have also been reported [20–23]. However, to the best of our knowledge, not a single analytical model is present for the subthreshold current and subthreshold swing of the device. In the present work, we are presenting a fully analytical model of subthreshold current and subthreshold swing for s-Si on SGOI MOSFET. The present model incorporates the effect of all device parameter. Lightly/moderately doped channel has been taken to avoid the degradation of carrier mobility. All the theoretical results are compared with the 2D simulation results obtained by commercially available ATLAS™24 2D device simulator [24]. 2. Device structure A schematic cross sectional view of s-Si on SGOI MOSFET used for 2D simulation is shown in Fig. 1. The silicon epitaxial layer with smaller lattice constant is assumed to be pseudomorphically grown on the relaxed Si1xGex layer so that biaxial strain is introduced in the silicon layer, where x is the Ge mole fraction. The symbols ts-Si and tSiGe represent the thicknesses of the strained-Si and Si1xGex layers respectively. Two different co-ordinate systems have been used in the 2D structure of strained-Si SGOI MOSFET. The x = 0 axis is assumed along the body thickness direction whereas y ¼ 0 and y0 ¼ 0 axes run along the strained-Si/SiO2 and Si1xGex/buried oxide interfaces respectively. 3. Theoretical modeling 3.1. Surface potential formulation To find out the potential distribution (w(x, y)) across strained-Si thin film, the 2D Poisson’s equation has been solved in both s-Si and Si1xGex regions with appropriate boundary conditions [18]:

M. Kumar et al. / Superlattices and Microstructures 58 (2013) 1–10

3

Fig. 1. Cross sectional view of s-Si on SGOI MOSFET.

@ 2 wi ðx; yÞ @ 2 wi ðx; yÞ qN a þ ¼ @x2 @y2 esSi;SiGe

i ¼ 1 and

es  Si for 0 6 x 6 Lg ; 0 6 y 6 tsSi region

i ¼ 2 and

eSiGe for 0 6 x 6 Lg ; 0 6 y 6 tSiGe region

ð1Þ

where q is the electronics charge, Na is the channel doping concentration, es-Si is the permittivity of strained Si layer, eSiGe is the permittivity of Si1xGex layer. Approximating the channel potential in the vertical direction as:

w1 ðx; yÞ ¼ ws ðxÞ þ C 11 ðxÞy þ C 12 ðxÞy2

ð2Þ

w2 ðx; yÞ ¼ wb ðxÞ þ C 21 ðxÞy þ C 22 ðxÞy2

ð3Þ

ws(x) and wb(x) are potential on strained-Si/front oxide interface and Si1xGex/buried oxide interface respectively. The coefficients C11(x), C12(x), C21(x) and C22(x) are functions of x only and can be stated as:

C 11 ðxÞ ¼

C 21 ðxÞ ¼

C ox

esSi Cb

eSiGe

ðws ðxÞ  V 0gs Þ ðwb ðxÞ  V 0sub Þ

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M. Kumar et al. / Superlattices and Microstructures 58 (2013) 1–10

2 ðC V 0 þC V 0 Þ 3 ox GS þC b Þ b sub þ 2CC Siox V 0GS þ wb ðxÞ ð2C SiGe C SiGe C SiGe C SiGe 4 5 C 12 ðxÞ ¼ ð2C þ2ðC ox =C Sige ÞC SiGe þC ox Þ 2ðC Si þ C SiGe Þt2sSi w ðxÞ SiGe s

C SiGe

2

3 b 2ws ðxÞ þ CCoxSi ðws ðxÞ  V 0GS Þ  CCSiGe ðwb ðxÞ  V 0sub Þ  2wb ðxÞ C Si 4 5 C 22 ðxÞ ¼ 2ðC Si þ C SiGe Þt2SiGe  C2CSiGeb ðwb3 ðxÞ  V 0sub Þ sSi SiGe where C ox ¼ etox ; C b ¼ etbox ; C Si ¼ etsSi ; C SiGe ¼ etSiGe ; tf, tb, ts-Si, tSiGe are the front gate oxide capacitance, burf ied oxide capacitance, strained-Si capacitances, relaxed Si1xGex layer capacitance, front gate oxide thickness, buried oxide thickness, Strained-Si layer thickness, relaxed Si1xGex layer thickness respectively.

V 0gs ¼ V gs  ðV FB;f ÞsSi V 0sub ¼ V sub  ðUsub  USiGe Þ Vgs is the gate to source voltage and (VFB,f)s-Si is the front channel flat-band voltage of strained-Si film, Vsub being the substrate voltage and USiGe is the work-function of relaxed Si1xGex layer; Usub is the work-function of the silicon substrate under buried oxide. By substituting w1(x, y) and w2(x, y) in Eq. (1) and rearranging the terms, we get the following second order differential equation for the front surface potential ws(x) as;

@ 2 ws ðxÞ  Pws ðxÞ ¼ Q 1 @x2 P¼

ð4Þ

a1 a2  b1 b2 a1 þ a2

Q1 ¼

a2 c1 þ b1 c2 a1 þ a2

Q2 ¼

a1 c2 þ b2 c1 a1 þ a2

a1 ¼

2C SiGe C sSi þ 2C ox C SiGe þ C ox C sSi C sSi ðC SiGe þ C sSi Þt 2sSi

b1 ¼

2C SiGe þ C b ðC SiGe þ C Si Þt2sSi

c1 ¼

qN a

esSi



ðC ox ð2C SiGe þ C sSi ÞV 0GS  C b C sSi V 0sub Þ C Si ðC SiGe þ C sSi Þt 2sSi

a2 ¼

2C SiGe C sSi þ 2C b C sSi þ C b C SiGe C SiGe ðC SiGe þ C sSi Þt 2SiGe

b2 ¼

2C sSi þ C f ðC SiGe þ C sSi Þt 2SiGe

c2 ¼

qN a

eSiGe



ðC b ð2C sSi þ C SiGe ÞV 0sub  C ox C SiGe V 0GS Þ C SiGe ðC SiGe þ C sSi Þt2SiGe

The solutions of second order non-homogenous differential equation of Eq. (4) with constant coefficients can be written as:

M. Kumar et al. / Superlattices and Microstructures 58 (2013) 1–10

ws ðxÞ ¼ A1 expðkxÞ þ B1 expðkxÞ  r1

r1 ¼

Q1 P

A1 ¼

ðV bi;sSi þ V ds þ r1 Þ  ðV bi;sSi þ r1 Þ expðkLÞ 2 sinhðkLÞ

5

ð5Þ

B1 ¼ V bi;sSi þ r1  A1 The position of the surface potential minima along the channel can be estimated by solving

ð@ws ðxÞ=@xÞx¼xmin ¼ 0 defined in Eq. (5) as

xmin ¼

  1 B1 ln 2a A1

Now the minimum surface potential can be obtained by putting xmin into Eq. (5) as

pffiffiffiffiffiffiffiffiffiffi ws;min ¼ 2 A1 B1  r1

ð6Þ

3.2. Subthreshold current formulation The subthreshold current is mainly dominated by the diffusion phenomenon and proportional to carrier concentration at the minimum channel potential position. By employing the thus obtained 2-D channel potential model and following the methodology as used in [25], the expression of subthreshold current can be written as follows:

Isub ¼

Z

t sSi

J n ðyÞ dy

ð7Þ

0

J n ðyÞ ¼

   qDn nmin ðyÞ V ds 1  exp  Le VT

Dn is diffusion constant, Le is the effective channel length, VT is the thermal voltage and

nmin ðyÞ ¼

  w1;min ðyÞ n2i exp VT Na

is the carrier concentration at the virtual cathode where, ni is the intrinsic carrier concentration in the substrate.

Le ¼ Lg  ðLs þ Ld Þ þ 2LD where Ls, Ld and LD are source channel depletion width, drain channel depletion widths and Debye length, can be stated as below,

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi esSi V T LD ¼ qNa Ls ¼

2ðV bi;sSi  wm Þ @w @x x¼0

Ld ¼

2ðV bi;sSi þ V ds  wm Þ @w @x x¼d

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wm ¼ w1;min ðym Þ ym is obtained by solving ð@w1;min ðyÞ=@yÞy¼ym ¼ 0 [25] and wm is obtained by replacing y to ym and ws(x) to ws,min in Eq. (3) and w1,min(y) can be found by substituting the ws,min from Eq. (6) into Eq. (2).

Isub ¼ K

Z

  w1;min ðyÞ dy VT

t sSi

exp

0

K¼

ð8Þ

   qDn V T n2i V ds 1  exp  Le Na VT

For the analytical solution of Eq. (8), the integral is divided into two parts by a partition point ym along the channel thickness. On applying some needful simplifications, the closed form expression of subthreshold current can be written as;

Isub ¼ K

"Z

ym

exp

0

Isub ¼ kV T



    # Z tsSi w1;min ðyÞ w1;min ðyÞ dy þ dy exp VT VT ym

If Ib þ Ef Eb

ð9Þ

 ð10Þ

If ¼ exp

    w1;min ðy ¼ 0Þ w1;min ðy ¼ ym Þ  exp VT VT

Ib ¼ exp

    w1;min ðy ¼ ym Þ w1;min ðy ¼ t sSi Þ  exp VT VT

Ef ¼ ðw1;min ðy ¼ 0Þ  w1;min ðy ¼ ym ÞÞ=ym Eb ¼ ðw1;min ðy ¼ ym Þ  w1;min ðy ¼ tsSi ÞÞ=ðtsSi  ym Þ 3.3. Subthreshold slope formulation The obtained subthreshold slope expression can be written as [25],

S¼

 1 @ log Isub @V gs

Isub is the subthreshold current, which is mainly due to the diffusion phenomenon, it can be assumed to be proportional to the carrier concentration at the position of minimum surface potential and hence S can be expressed as in term of potential function,

S ¼ V T ðln 10Þ 

S¼

  @w1;min ðyÞ 1 @V gs

V T ðln 10Þ 2

w0s;min þ C 011 deff þ C 012 deff

where deff is effective conduction path effect parameter and is determined like Ref. [25]; and

w0s;min ¼ fðA1 B1 Þ1=2 ðA1 B01 þ A01 B1 Þg  r01

r01 ¼

c02 b1 þ c01 a2 Pða1 þ a2 Þ

ð11Þ

ð12Þ

M. Kumar et al. / Superlattices and Microstructures 58 (2013) 1–10

c01 ¼

2C ox t 2sSi C Si

c02 ¼

C ox t 2SiGe ðC Si þ C SiGe Þ

A01 ¼

7

r01 ð1  expðkLÞÞ 2 sinhðkLÞ

B01 ¼ r01  A01 C 011 ¼ C 012 ¼

C ox

esSi

ðw0s;min  1Þ

  C SiGe C ox 2C ox 2C SiGe þ 3C ox 0 þ  w s;min C Si C SiGe 2ðC Si þ C SiGe Þt 2sSi C SiGe

4. Results and discussion In this section, the obtained analytical results from proposed the model of the subthreshold current (Isub) and subthreshold swing (S) for s-Si on SGOI MOSFETs have been compared with the numerical simulation results. In order to incorporate the effect of strain into the device characteristics, some strain-dependent parameters like band structure, channel flat-band voltage, built-in voltage across the source-body and drain-body junctions of the ATLAS™ device simulator model library have been modified following the previously reported methods [22,26]. Fig. 2 shows the subthreshold current variation against gate to source voltage (Vgs) at different gate lengths Lg keeping all other device parameters constant. It is found that the subthreshold current increases with the decrease in device channel length. A good matching between model result and simulation result may be observed below threshold voltage as only diffusion phenomenon is considered to derive the subthreshold current. Fig. 3 depicts the sound effects of strain (Ge mole fraction in Si1xGex layer) on subthreshold current versus Vgs characteristics. The subthreshold current can be observed increasing with increase

Fig. 2. Subthreshold current versus gate to source voltage for different gate length.

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M. Kumar et al. / Superlattices and Microstructures 58 (2013) 1–10

Fig. 3. Subthreshold current versus gate to source voltage for different Ge mole fraction in SiGe layer.

in strain in Si channel. The increase in leakage current may be attributed to the fact that the built-in potential across source/drain-channel decreases with increasing strain which in turn reduces the channel potential barrier. The subsequent model results deal with the subthreshold swing (S) dependency upon various device parameters. The subthreshold swing (S) variation as a function of device channel length for two different gate oxide thicknesses has been shown in Fig. 4. It can be seen that S increases sharply below the certain gate length because of severe increase in SCEs. Further, as expected, the thinner gate oxide thickness improves the switching characteristics of the device as shown in Fig. 4. Fig. 5 explicates the subthreshold swing (S) versus gate length (Lg) for different Si-film thicknesses. The deterioration of the

Fig. 4. Subthreshold swing versus channel length for different gate oxide thickness.

M. Kumar et al. / Superlattices and Microstructures 58 (2013) 1–10

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Fig. 5. Subthreshold swing versus channel length for different Si layer thickness.

Fig. 6. Subthreshold swing versus Ge mole fraction for different gate lengths.

switching characteristics of the device with increasing Si-channel thickness may be easily observed from the figure. Fig. 6 provides an idea about the effect of strain on S for different Lg. It is found that an increase in Ge mole fraction (x) results in higher S. Moreover, this increment in S increases with decreasing gate length. The estimated increase in the value of S is as follows: for an increase in the Ge mole fraction from 0% to 30%, the S value gets increased by 14.73% for 30 nm gate length, 2.94% for 50 nm gate lengths and 0.8% for 70 nm gate lengths. In other words, it may be inferred that effect of strain over device switching characteristics gets improve with increasing device gate length.

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5. Conclusion In this paper, a surface potential based subthreshold current and subthreshold swing model has been derived for the s-Si on SGOI MOSFETs. The subthreshold current is observed to be increased with decreasing gate length and increasing strain in the channel. It is observed that the switching characteristics of s-Si on SGOI MOSFETs are deteriorated with the increase in the channel thickness, gate oxide thickness and strain in the channel and decrease in channel length. The proposed model is verified by comparing the results with the simulation data obtained by using the commercially available ATLAS device simulation software. The derived analytical models are in good agreement with the results of the two dimensional device simulations. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26]

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