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Si1−xGex MOSFETs
Solid-State Electronics 43 (1999) 2173±2180
Eect of the Ge-molefraction on the subthreshold slope and leakage current of vertical Si/Si1ÿxGex MOSFETs N. Collaert a,*, K. De Meyer a, b a IMEC, Kapeldreef 75, B-3001, Heverlee, Belgium K.U.Leuven, ESAT-INSYS, Kardinaal Mercierlaan 94, B-3001, Heverlee, Belgium
b
Received 22 April 1999; received in revised form 6 July 1999; accepted 7 July 1999
Abstract The eect of the Ge-concentration on the subthreshold behaviour of vertical Si/Si1ÿxGex pMOSFETs and of complementary Si1ÿxGex/Si nMOSFETs is investigated by using an analytical model, which includes thermionic emission across the hetero-barrier. It is shown that inclusion of Si1ÿxGex and strained Si in the source region of the pMOSFET and nMOSFET respectively, suppresses the subthreshold slope roll-up substantially and lowers the leakage current of even the smallest devices with channel lengths down to 50 nm. # 1999 Elsevier Science Ltd. All rights reserved.
1. Introduction Vertical MOSFET technology has gained a lot of interest due to the promising perspective to combine standard optical lithography with the possibility to grow channel lengths with nanometer resolution by MBE or CVD epitaxy [1±4]. However, these vertical transistors still have to overcome the Drain Induced Barrier Lowering (DIBL) and Short Channel Eect (SCE) problem, leading to a threshold voltage roll-o and an increase in subthreshold slope and leakage current when going to smaller channel lengths. Furthermore, unlike its planar counterpart, channel engineering is almost not applicable to these vertical devices. The novel device proposed in [5,6] circumvents this problem by introducing a material dependent barrier between source and drain. For the pMOSFET this
* Corresponding author. Tel.: +32-16-28-16-41; fax: +3216-28-12-14. E-mail address: [email protected] (N. Collaert)
barrier is formed by Si1ÿxGex in the source region and Si in the channel of the vertical transistor [7]. The lowly doped Si1ÿxGex region in the source, nearby the channel region, makes it possible to lower the eective barrier for the holes when the device is put in its onstate. In case of the nMOSFET, this barrier is formed by a strained Si layer on top of a Si1ÿxGex buerlayer. In this case, Si1ÿxGex will be used as channel and drain material [7]. However, the question which remains is how high does this Ge concentration has to be to eectively tackle the problem of DIBL and SCE. The paper focuses on the in¯uence of the Si1ÿxGex/Si barrier on the subthreshold behaviour and more speci®cally the subthreshold slope roll-up and leakage current. In section 2 an analytical model for the current will be derived. The most important feature of this model is the inclusion of thermionic emission as boundary condition at the hetero-interface. The current model is vital to the calculation of the subthreshold slope. Section 3 discusses the results. It will be shown that the in¯uence of the Si1ÿxGex is the most imminent for sub 0.1 mm devices.
0038-1101/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 9 9 ) 0 0 1 8 5 - 9
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N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
Fig. 1. Schematic presentation of the vertical heterojunction (a) pMOSFET and (b) nMOSFET.
2. Model The novel heterojunction pMOSFET and nMOSFET are shown in Fig. 1a and b respectively. Within the drift-diusion model the expression for the current density in case of a pMOSFET is given by
Jx ÿqmVth
@p @c ÿ qmp @x @x
1
For a nMOSFET the drift-diusion equation is given by
Jx qmVth
@n @c ÿ qmn @x @x
2
with c being the electrical potential, p the hole concentration, m the hole or electron mobility and Vth the thermal voltage. We use the continuity equation together with Eq. (1) in case of a pMOSFET and together with Eq. (2) in case of a nMOSFET to get a possible expression for the hole and electron concentration ÿc2 x, y p2 x, y exp Vth " # L 1 c2 t, y A2 B 2 exp dt Vth x mp2
3
c x, y n2 x, y exp 2 Vth " # L 1 ÿc2 t, y C2 D2 exp dt Vth x mn2
4
with L being the channel length, A2, B2, C2 and D2 constants following from the boundary conditions and c2 the potential in the channel. In the remainder of the paper the subscript 2 will refer to the Si channel and subscript 1 to the lowly doped Si1ÿxGex source region in the case of the pMOSFET. For the nMOSFET, the subscript 2 will refer to the Si1ÿxGex channel and subscript 1 to the lowly doped Si source region. Apart from the channel region, in the vertical heterojunction pMOSFET the lowly doped Si1ÿxGex source region plays an important role in the device operation. The in¯uence of the gate potential on this region will lower the barrier seen by the holes and will cause a large current to ¯ow in the on-state. Therefore similar expressions as Eqs. (3) and (4) can be written for the hole and electron concentrations in the Si1ÿxGex region and strained Si region respectively ÿc1 x, y p1 x, y exp Vth " # x 1 c1 t, y A1 B1 dt exp Vth ÿL1 mp1
5
N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
c x, y n1 x, y exp 1 Vth " # x 1 ÿc1 t, y C 1 D1 dt exp Vth ÿL1 mn1
6
with L1 being the thickness of the Si1ÿxGex or in case of a nMOSFET strained Si source region, A1, B1, C1 and D1 constants following from the boundary conditions and c1 the potential in the source. Calculation of the constants can be done by assuming the following boundary conditions: p1 ÿL1 , y NSD and n1 ÿL1 , y NSD
7
p2 L, y NSD and n2 L, y NSD
8
In case of a pMOSFET [8]: JTEp A2p Zp
p2 0, y p1 0, y ÿEB ÿ exp Nv2 Nv1 kT
0 0 11 m ÿEB Zp T 2 B1 ÿ 1 ÿ h1 exp B CC mh2 @ kT mh2 ÿ 1 A A @ mh1
9
10
2175
channel, m h1 and m h2 the eective hole masses in Si1ÿxGex and Si respectively, JDDp the hole drift-diusion current and JTEp the thermionic emission current for holes. In case of the nMOSFET [8]: JTEn
A1n Zn 0
n2 0, y n1 0, y ÿEB ÿ exp Nc2 Nc1 kT
m Zn T B1 ÿ 1 ÿ e2 me1 @ 2
0
11 ÿEB CC expB @ kT me1 ÿ 1 A A me2
JTEn JDDn x 0
ÿVbi1 ÿEB VDS ÿc2 0, y exp ÿ 1 exp exp exp Vth Vth kT Vth 0 1 Jp ÿEB B C L 0 exp A2p Zp ÿc2 0, y @ 1 1 c x, y 1 c x, y kT A 1 dx ÿ dx exp exp 2 exp 1 Vth Nv2 0 mp2 Vth Vth qVth Nv1 ÿL1 mp1
11
where NSD represents the high source/drain doping level, Nv1 and Nv2 the hole density of states in Si1ÿxGex and Si respectively, A 2p the hole Richardson constant of Si, EB the barrier height measured between the source Fermi-level and the valence band in the
Wp
D 0
13
14
where Nc1 and Nc2 represent the electron density of states in Si and Si1ÿxGex respectively, A 2n the electron Richardson constant of Si1ÿxGex, EB the barrier height measured between the source Fermi-level and the conduction band in the channel, JDDn the electron driftdiusion current and JTEn the thermionic emission current for electrons. Combining Eqs. (3), (9) and (11) and using Eqs. (7) and (8) as boundary conditions leads to the following expression for the hole current density
NSD A2p Zp Nv1
JTEp JDDp x 0
12
15
where Vbi1 represents the built-in potential between the lowly and the highly doped source region. Integration over the y- and z-direction gives the expression for the hole current Ip
NSD WA2p Nv1
ÿVbi1 VDS exp ÿ 1 Wp exp Vth Vth
ÿEB ÿc2 0, y Zp exp dy exp Vth kT 0 1 ÿEB L 0 exp C A2p Zp ÿc2 0, y B 1 c x, y 1 c x, y kT @ 1 A 1 exp exp 2 exp 1 dx ÿ dx qVth Nv1 Vth Nv2 0 mp2 Vth m V th ÿL1 p1
16
17
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N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
ÿEB ÿc2 0, y exp a exp Vth kT
with W the transistor width and D the distance between the two oxide layers as shown in Fig. 1a and b. In an analogous way, the electron current for the nMOSFET can be calculated from Eqs. (4), (12) and (14) using Eqs. (7) and (8) as boundary conditions:
@Z Z @ EB Z @ c2 ÿ ÿ 0 0 Vth @ c02 @ c2 kT @ c2
!
NSD ÿVbi1 ÿEB ÿVDS c 0, y exp exp 2 exp 1 ÿ exp Vth Nc1 Vth kT Vth 0 1 Jn ÿEB exp C L 0 A Z c 0, y B 1 ÿc2 x, y 1 ÿc1 x, y @ 1 A kT 1 ÿ 1n n exp 2 dx ÿ dx exp exp qVth Nc1 Vth Nc2 0 mn2 Vth Vth ÿL1 mn1 A1n Zn
NSD ÿVbi1 ÿVDS 1 ÿ exp Wn exp Nc1 Vth Vth 19
Wn
D 0
18
A2p Z ÿc2 0, y b1 exp Vth qVth 0 ÿEB exp B 1 L 1 c x, y kT @ dx ÿ exp 2 Nv2 0 mp2 vth Nv1 1 0 C 1 c x, y A dx 24 exp 1 m V th ÿL1 p1
where Vbi1 represents the built-in potential between the lowly and the highly doped source region. Integration over the y- and z-direction gives the expression for the electron current In WA1n
23
c 0, y dy exp 2 Vth 1 0 ÿEB exp C L 0 A Z ÿc2 0, y B 1 ÿc2 x, y 1 ÿc1 x, y A kT @ 1 1 1n n exp dx ÿ dx exp exp Vth Nc2 0 mn2 Vth Vth qVth Nc1 ÿL1 mn1 ÿEB Zn exp kT
20
The subthreshold slope can be easily calculated from Eqs. (16) and (19): In case of a pMOSFET: S ln 10
@ VGS @ c 02 @ c02 @ ln Ip
21
where c 02=c2(x,y = 0) represents the surface potential in the channel @ ln Ip 1 @W 1 W @ c02 W @ c02 where
D 0
ab ÿ dx dy b2
22
ÿEB ÿc2 0, y d Z exp exp kT Vth ! A2p ÿc2 0, y @Z Z @ c2 x exp ÿ Vth qVth @ c02 Vth @ c02 0
ÿEB exp B 1 L 1 c x, y kT @ dx ÿ exp 2 Nv2 0 mp2 Vth Nv1 1 C 0 1 c x, y A exp 1 dx Vth ÿL1 mp1
25
N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
2177
A2p Z ÿc2 0, y exp qVth Vth 0
B 1 L 1 c x, y @ c2 @ exp 2 dx Nv2 0 mp2 Vth Vth @ c02
ÿEB exp @ EB 0 1 kT kTNv1 @ c02 ÿL1 mp1 1 C c1 x, y ÿc2 0, y A A2p Z dx ÿ exp exp qVth Vth Vth
exp
ÿEB kT Nv1
0 ÿL1
1 c x, y @ c1 exp 1 dx mp1 Vth Vth @ c02 26
The ®rst term can be calculated if the potentials c2 and c1 are known. An extensive description of the potential calculation can be found in [9]. The 0 results @c of this study will be used here to calculate @ VGS2 . In a similar way, the equations for the nMOSFET can be derived. 3. Results and discussion Veri®cation of the analytical models for subthreshold slope and o-state current was done by comparison with 2D numerical simulations [10] and with the experimental results for the pMOSFET taken from [6]. The dependence of subthreshold slope and o-state current on Vds, channel length L, Ge-concentration and channel doping was investigated. As a reference device, a Si-only transistor is used in case of a pMOSFET and a Si1ÿxGex-only transistor is used in case of a nMOSFET. In the latter case the reference device will change with Ge-concentration. The leakage current and subthreshold slope were calculated at both vVdsv=0.1 V and vVdsv=1.5 V. In Figs. 2 and 3, the leakage current at vVdsv=0.1 V is shown as function of the substrate doping concentration. The in¯uence of the Ge-concentration will be most imminent at low substrate doping concentrations since in that case the doping is not high enough to provide a low o-state current. In the high doping range, the built-in potential due to the high channel doping will be dominant, decreasing the in¯uence of the Ge incorporated in the design. In Fig. 4, the dependence on the Ge-molefraction is shown for both pMOS and nMOS devices. The comparison with numerical simulation results is excellent for the pMOS and good for the nMOS. As can be
Fig. 2. Leakage current of the pMOSFET at Vds=ÿ0.1 V as a function of substrate doping: tox=4 nm, L = 100 nm, L1=30 nm and the Si1ÿxGex-region is intrinsic. Three dierent Ge-concentrations are shown: 10, 20 and 30%.
seen from this ®gure, the Ge-concentration eectively decreases the o-state current of the devices over several orders of magnitude until about 75% Ge. Higher Ge-molefractions will not aect the current anymore. Around 75%, the Ge-molefraction will not decrease the bandgap anymore in the case of strained Si1ÿxGex
Fig. 3. Leakage current of the nMOSFET at Vds=0.1 V as a function of substrate doping: tox=4 nm, L = 100 nm, L1=30 nm and the strained Si source region is intrinsic. Three dierent Ge-concentrations are shown: 10, 20 and 30%.
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N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
Fig. 4. Leakage current of the pMOSFET and nMOSFET at vVdsv=0.1 V as a function of Ge-concentration. The strained Si (nMOS) or Si1ÿxGex (pMOS) source region is intrinsic and tox=4 nm, L = 100 nm, L1=30 nm, Nsub=8 1017 cmÿ3 (nMOS) and Nsub=7 1017 cmÿ3 (pMOS).
Fig. 5. Subthreshold slope as function of the channel length for both pMOS and nMOS. The pMOS has tox=4 nm, Nsub=7 1017 cmÿ3, L1=30 nm and an intrinsic Si0.9Ge0.1 source region. In case of the nMOS: tox=4 nm, Nsub=8 1017 cmÿ3, L1=30 nm, an intrinsic Si source region and a Si0.9Ge0.1 channel.
Fig. 6. Comparison of the Ids±Vgs curves of (a) a Si0.8Ge0.2/Si pMOSFET and its Si-only counterpart and (b) a Si/Si0.8Ge0.2 nMOSFET and its Si0.8Ge0.2-only counterpart; Both pMOS and nMOS devices have L = 100 nm, tox=4 nm, Nsub=8 1017 cmÿ3 and L1=30 nm.
N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
2179
Table 1 Comparison of the pMOSFET subthreshold slope and leakage current with experimental results for dierent substrate concentrations and Ge-concentrations Experimental Io (A/mm) L(nm) Vds=ÿ0.1 V 120 70 Vds=ÿ1.5 V 120 70
Analytical Io
Experimental S(mV/dec)
%Ge
Nsub
Average
± 10 10 20 15
1E+18 1E+18 5E+17 5E+17 1E+18
1.3Eÿ17 2Eÿ19 5Eÿ17 8.5Eÿ17 2Eÿ14
1Eÿ17 4Eÿ20 3Eÿ17 4Eÿ17 9Eÿ15
2Eÿ18 2Eÿ20 2.5Eÿ17 1Eÿ16 6Eÿ14
106 102 90 95 114
± 10 10 20 15
1E+18 1E+18 5E+17 5E+17 1E+18
9Eÿ15 3Eÿ17 1.4Eÿ15 5Eÿ15 3Eÿ11
5Eÿ15 1Eÿ17 6Eÿ16 5Eÿ15 2.5Eÿ11
7.00Eÿ15 3.20Eÿ17 1.06Eÿ15 5.25Eÿ15 1.2Eÿ11
121 109 94 103 175
Std dev
source layer (pMOS). In the case of the nMOS, the model for the bandgap discussed in [7] is not valid anymore for Ge concentrations higher than 75%. As is shown in Fig. 4, the in¯uence on the leakage current of the nMOS devices is much more pronounced than the in¯uence of the Ge-molefraction on the leakage current of the pMOS devices. A higher bandoset together with the higher substrate doping can account for this. In Fig. 5, the subthreshold slope of both pMOS and nMOS heterojunction devices is compared with their homojunction counterparts. A substantial decrease in subthreshold slope roll-up can be seen for the smallest channel lengths while the long channel subthreshold slope is unaected by the heterojunction. The Ids±Vgs characteristics of the vertical heterojunction transistor and its Si-only counterpart are shown in Figs. 6a and b. The inset of the ®gures shows the comparison of the analytical model for the heterojunction devices with numerical simulation. For both pMOS and nMOS this comparison is excellent. In all cases, a constant doping dependent mobility was used for the analytical model and the numerical simulations. As can be seen from the Ids ±Vgs curves the heterojunction devices show lower o-state currents, lower subthreshold slopes and better resistance against DIBL. The on-state current is slightly lower than the Si-only devices due to the intrinsically higher threshold voltage. Fig. 7 shows the ratio Ion/Io as a function of the Ge-concentration at Vds=0.1 V and Vds=1.5 V. The o-state current is taken at Vgs=0 V and the on-state current at Vgs=1.5 V. As can be seen from the plot, a maximum can be observed around 20% (Vds=0.1 V) for this particular layer set-up. The maximum is
Average
Analytical S
STD dev 2.5 1 2 2 3 4 2 2 5 16
115 108 97 99 108 138 113 98 103 166
slightly shifted towards lower Ge-concentrations for higher Vds and a decrease in maximum can be observed due to the DIBL eect. So initially the Ge-concentration will aect the ostate current much more than the on-state current (region 1 ). When the Ge-concentration becomes too high, degradation of the on-state current starts to occur (region 2 ). As a consequence, for applications where the ratio Ion/Io (e.g. in DRAMs) is of major importance, one can only use moderate Ge-concentrations to stay as close to this maximum or at least to stay in region 1. Finally, Table 1 shows the comparison of the analytical model with experimental results obtained for the pMOSFET. As it is mentioned in [6], the devices with L = 120 nm use a directly wet oxidised gate dielectric with tox=4 nm on the Si layers. Since the oxidation rate of the Si1ÿxGex layer is much higher, one must take into account the non-uniform SiO2 thickness and the increased interface density of states (Dit) while calculating the potentials [9] and current densities. The oxide thickness on the Si0.9Ge0.1 layer is about four times thicker than on the Si layer and Dit has to be taken around 2 1012 cmÿ2. In case of the 70 nm devices, an alternative oxidation strategy [11,12] has been used and the oxide thickness is more or less uniform with tox=6 nm. The comparison between theory and experiment is very good. 4. Conclusion An analytical model has been derived to investigate the in¯uence of the Ge-concentration on the leakage current and subthreshold slope of vertical heterojunc-
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N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
References
Fig. 7. Ratio Ion/Io as function of the Ge-concentration for the nMOSFET at Vds=0.1 V and Vds=1.5 V: tox=4 nm, L = 100 nm, L1=30 nm and Nsub=7 1017 cmÿ3.
tion MOSFETs. The model shows a good agreement with 2D simulation results. The dependence of Io and S on channel length, substrate concentration and Geconcentration was studied. The heterojunction devices show lower leakage currents and better subthreshold slopes than their Si-only (for the pMOS) and Si1ÿxGex-only (for the nMOS) counterparts. The dierence is quite signi®cant in case of the deep sub 0.1 mm devices. Acknowledgements The authors would like to thank the European Commission for the ®nancial support in the framework of the ESPRIT IV LTR VAHMOS 2000 project no. 22495. Nadine Collaert would like to thank the IWT for granting her a fellowship.
[1] Behammer D, Vescan L, Loo R, Moers J, MuÈck A, LuÈth H, Grabolla T. Selectively grown vertical Si-pMOS transistor with short channel lengths. Electron Lett 1996;32:406±7. [2] Gossner H, Eisele I, Risch L. Vertical Si-metal-oxidesemiconductor ®eld eect transistors with channel lengths of 50 nm by molecular beam epitaxy. Jpn J Appl Phys 1994;33:2423±8. [3] Aeugle T, Risch L, Rosner W, Schulz T, Behammer D. Advanced self aligned SOI concepts for vertical MOS transistors with ultrashort channel lengths. In: Proc. ESSDERC'97, 1997. p. 628±31. [4] Liu KC, Ray SK, Oswal SK, Banerjee SK. A deep submicron Si1ÿxGex vertical PMOSFET fabricated by Ge ion implantation. IEEE Electron Device Lett 1998;19:13± 5. [5] US Provisional Patent Application Number: 60/001,022, July 7th, 1995, C.J.R.P. Augusto, IMEC. [6] De Meyer K, Caymax M, Collaert N, Loo R, Verheyen P. The vertical heterojunction MOSFET. Thin Solid Films 1998;336:299±305. [7] People R, Bean JC. Band alignments of coherently strained GexSi1ÿx/Si heterostructures on h001i GeySi1-y substrates. Appl Phys Lett 1986;48(8):538±40. [8] Grinberg AA, Luryi S. On electron transport across interfaces connecting materials with dierent eective masses. IEEE Trans Electron Devices 1998;45(7):1561±8. [9] Collaert N, De Meyer K. Modeling the short channel threshold voltage of a novel vertical heterojunction pMOSFET. IEEE Trans Electron Devices 1999;46(5):933±9. [10] TMA Medici v4.0 manual, Technology Modeling Associates Inc., October 1997, 2-119±2-122. [11] Loo R, Caymax M, Verheyen P, Conard T, Bender H, Vandervorst W, Collaert N, De Meyer K, Alkemade P, Szendro I. Ultra thin gate oxides for 0.1 mm heterojunction CMOS applications by the use of a sacri®cial Si layer. In: Proc. ESSDERC'98, 1998. p. 608±11. [12] Verheyen P, Collaert N, Caymax M, Loo R, De Meyer K, Van Rossum M. A vertical Si/Si1ÿxGex heterojunction pMOSFET with reduced DIBL sensitivity, using a novel gate dielectric approach. In: Proc. 1999 VLSI-TSA, 1999. p. 19±22.
Eect of the Ge-molefraction on the subthreshold slope and leakage current of vertical Si/Si1ÿxGex MOSFETs N. Collaert a,*, K. De Meyer a, b a IMEC, Kapeldreef 75, B-3001, Heverlee, Belgium K.U.Leuven, ESAT-INSYS, Kardinaal Mercierlaan 94, B-3001, Heverlee, Belgium
b
Received 22 April 1999; received in revised form 6 July 1999; accepted 7 July 1999
Abstract The eect of the Ge-concentration on the subthreshold behaviour of vertical Si/Si1ÿxGex pMOSFETs and of complementary Si1ÿxGex/Si nMOSFETs is investigated by using an analytical model, which includes thermionic emission across the hetero-barrier. It is shown that inclusion of Si1ÿxGex and strained Si in the source region of the pMOSFET and nMOSFET respectively, suppresses the subthreshold slope roll-up substantially and lowers the leakage current of even the smallest devices with channel lengths down to 50 nm. # 1999 Elsevier Science Ltd. All rights reserved.
1. Introduction Vertical MOSFET technology has gained a lot of interest due to the promising perspective to combine standard optical lithography with the possibility to grow channel lengths with nanometer resolution by MBE or CVD epitaxy [1±4]. However, these vertical transistors still have to overcome the Drain Induced Barrier Lowering (DIBL) and Short Channel Eect (SCE) problem, leading to a threshold voltage roll-o and an increase in subthreshold slope and leakage current when going to smaller channel lengths. Furthermore, unlike its planar counterpart, channel engineering is almost not applicable to these vertical devices. The novel device proposed in [5,6] circumvents this problem by introducing a material dependent barrier between source and drain. For the pMOSFET this
* Corresponding author. Tel.: +32-16-28-16-41; fax: +3216-28-12-14. E-mail address: [email protected] (N. Collaert)
barrier is formed by Si1ÿxGex in the source region and Si in the channel of the vertical transistor [7]. The lowly doped Si1ÿxGex region in the source, nearby the channel region, makes it possible to lower the eective barrier for the holes when the device is put in its onstate. In case of the nMOSFET, this barrier is formed by a strained Si layer on top of a Si1ÿxGex buerlayer. In this case, Si1ÿxGex will be used as channel and drain material [7]. However, the question which remains is how high does this Ge concentration has to be to eectively tackle the problem of DIBL and SCE. The paper focuses on the in¯uence of the Si1ÿxGex/Si barrier on the subthreshold behaviour and more speci®cally the subthreshold slope roll-up and leakage current. In section 2 an analytical model for the current will be derived. The most important feature of this model is the inclusion of thermionic emission as boundary condition at the hetero-interface. The current model is vital to the calculation of the subthreshold slope. Section 3 discusses the results. It will be shown that the in¯uence of the Si1ÿxGex is the most imminent for sub 0.1 mm devices.
0038-1101/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 9 9 ) 0 0 1 8 5 - 9
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N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
Fig. 1. Schematic presentation of the vertical heterojunction (a) pMOSFET and (b) nMOSFET.
2. Model The novel heterojunction pMOSFET and nMOSFET are shown in Fig. 1a and b respectively. Within the drift-diusion model the expression for the current density in case of a pMOSFET is given by
Jx ÿqmVth
@p @c ÿ qmp @x @x
1
For a nMOSFET the drift-diusion equation is given by
Jx qmVth
@n @c ÿ qmn @x @x
2
with c being the electrical potential, p the hole concentration, m the hole or electron mobility and Vth the thermal voltage. We use the continuity equation together with Eq. (1) in case of a pMOSFET and together with Eq. (2) in case of a nMOSFET to get a possible expression for the hole and electron concentration ÿc2 x, y p2 x, y exp Vth " # L 1 c2 t, y A2 B 2 exp dt Vth x mp2
3
c x, y n2 x, y exp 2 Vth " # L 1 ÿc2 t, y C2 D2 exp dt Vth x mn2
4
with L being the channel length, A2, B2, C2 and D2 constants following from the boundary conditions and c2 the potential in the channel. In the remainder of the paper the subscript 2 will refer to the Si channel and subscript 1 to the lowly doped Si1ÿxGex source region in the case of the pMOSFET. For the nMOSFET, the subscript 2 will refer to the Si1ÿxGex channel and subscript 1 to the lowly doped Si source region. Apart from the channel region, in the vertical heterojunction pMOSFET the lowly doped Si1ÿxGex source region plays an important role in the device operation. The in¯uence of the gate potential on this region will lower the barrier seen by the holes and will cause a large current to ¯ow in the on-state. Therefore similar expressions as Eqs. (3) and (4) can be written for the hole and electron concentrations in the Si1ÿxGex region and strained Si region respectively ÿc1 x, y p1 x, y exp Vth " # x 1 c1 t, y A1 B1 dt exp Vth ÿL1 mp1
5
N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
c x, y n1 x, y exp 1 Vth " # x 1 ÿc1 t, y C 1 D1 dt exp Vth ÿL1 mn1
6
with L1 being the thickness of the Si1ÿxGex or in case of a nMOSFET strained Si source region, A1, B1, C1 and D1 constants following from the boundary conditions and c1 the potential in the source. Calculation of the constants can be done by assuming the following boundary conditions: p1 ÿL1 , y NSD and n1 ÿL1 , y NSD
7
p2 L, y NSD and n2 L, y NSD
8
In case of a pMOSFET [8]: JTEp A2p Zp
p2 0, y p1 0, y ÿEB ÿ exp Nv2 Nv1 kT
0 0 11 m ÿEB Zp T 2 B1 ÿ 1 ÿ h1 exp B CC mh2 @ kT mh2 ÿ 1 A A @ mh1
9
10
2175
channel, m h1 and m h2 the eective hole masses in Si1ÿxGex and Si respectively, JDDp the hole drift-diusion current and JTEp the thermionic emission current for holes. In case of the nMOSFET [8]: JTEn
A1n Zn 0
n2 0, y n1 0, y ÿEB ÿ exp Nc2 Nc1 kT
m Zn T B1 ÿ 1 ÿ e2 me1 @ 2
0
11 ÿEB CC expB @ kT me1 ÿ 1 A A me2
JTEn JDDn x 0
ÿVbi1 ÿEB VDS ÿc2 0, y exp ÿ 1 exp exp exp Vth Vth kT Vth 0 1 Jp ÿEB B C L 0 exp A2p Zp ÿc2 0, y @ 1 1 c x, y 1 c x, y kT A 1 dx ÿ dx exp exp 2 exp 1 Vth Nv2 0 mp2 Vth Vth qVth Nv1 ÿL1 mp1
11
where NSD represents the high source/drain doping level, Nv1 and Nv2 the hole density of states in Si1ÿxGex and Si respectively, A 2p the hole Richardson constant of Si, EB the barrier height measured between the source Fermi-level and the valence band in the
Wp
D 0
13
14
where Nc1 and Nc2 represent the electron density of states in Si and Si1ÿxGex respectively, A 2n the electron Richardson constant of Si1ÿxGex, EB the barrier height measured between the source Fermi-level and the conduction band in the channel, JDDn the electron driftdiusion current and JTEn the thermionic emission current for electrons. Combining Eqs. (3), (9) and (11) and using Eqs. (7) and (8) as boundary conditions leads to the following expression for the hole current density
NSD A2p Zp Nv1
JTEp JDDp x 0
12
15
where Vbi1 represents the built-in potential between the lowly and the highly doped source region. Integration over the y- and z-direction gives the expression for the hole current Ip
NSD WA2p Nv1
ÿVbi1 VDS exp ÿ 1 Wp exp Vth Vth
ÿEB ÿc2 0, y Zp exp dy exp Vth kT 0 1 ÿEB L 0 exp C A2p Zp ÿc2 0, y B 1 c x, y 1 c x, y kT @ 1 A 1 exp exp 2 exp 1 dx ÿ dx qVth Nv1 Vth Nv2 0 mp2 Vth m V th ÿL1 p1
16
17
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N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
ÿEB ÿc2 0, y exp a exp Vth kT
with W the transistor width and D the distance between the two oxide layers as shown in Fig. 1a and b. In an analogous way, the electron current for the nMOSFET can be calculated from Eqs. (4), (12) and (14) using Eqs. (7) and (8) as boundary conditions:
@Z Z @ EB Z @ c2 ÿ ÿ 0 0 Vth @ c02 @ c2 kT @ c2
!
NSD ÿVbi1 ÿEB ÿVDS c 0, y exp exp 2 exp 1 ÿ exp Vth Nc1 Vth kT Vth 0 1 Jn ÿEB exp C L 0 A Z c 0, y B 1 ÿc2 x, y 1 ÿc1 x, y @ 1 A kT 1 ÿ 1n n exp 2 dx ÿ dx exp exp qVth Nc1 Vth Nc2 0 mn2 Vth Vth ÿL1 mn1 A1n Zn
NSD ÿVbi1 ÿVDS 1 ÿ exp Wn exp Nc1 Vth Vth 19
Wn
D 0
18
A2p Z ÿc2 0, y b1 exp Vth qVth 0 ÿEB exp B 1 L 1 c x, y kT @ dx ÿ exp 2 Nv2 0 mp2 vth Nv1 1 0 C 1 c x, y A dx 24 exp 1 m V th ÿL1 p1
where Vbi1 represents the built-in potential between the lowly and the highly doped source region. Integration over the y- and z-direction gives the expression for the electron current In WA1n
23
c 0, y dy exp 2 Vth 1 0 ÿEB exp C L 0 A Z ÿc2 0, y B 1 ÿc2 x, y 1 ÿc1 x, y A kT @ 1 1 1n n exp dx ÿ dx exp exp Vth Nc2 0 mn2 Vth Vth qVth Nc1 ÿL1 mn1 ÿEB Zn exp kT
20
The subthreshold slope can be easily calculated from Eqs. (16) and (19): In case of a pMOSFET: S ln 10
@ VGS @ c 02 @ c02 @ ln Ip
21
where c 02=c2(x,y = 0) represents the surface potential in the channel @ ln Ip 1 @W 1 W @ c02 W @ c02 where
D 0
ab ÿ dx dy b2
22
ÿEB ÿc2 0, y d Z exp exp kT Vth ! A2p ÿc2 0, y @Z Z @ c2 x exp ÿ Vth qVth @ c02 Vth @ c02 0
ÿEB exp B 1 L 1 c x, y kT @ dx ÿ exp 2 Nv2 0 mp2 Vth Nv1 1 C 0 1 c x, y A exp 1 dx Vth ÿL1 mp1
25
N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
2177
A2p Z ÿc2 0, y exp qVth Vth 0
B 1 L 1 c x, y @ c2 @ exp 2 dx Nv2 0 mp2 Vth Vth @ c02
ÿEB exp @ EB 0 1 kT kTNv1 @ c02 ÿL1 mp1 1 C c1 x, y ÿc2 0, y A A2p Z dx ÿ exp exp qVth Vth Vth
exp
ÿEB kT Nv1
0 ÿL1
1 c x, y @ c1 exp 1 dx mp1 Vth Vth @ c02 26
The ®rst term can be calculated if the potentials c2 and c1 are known. An extensive description of the potential calculation can be found in [9]. The 0 results @c of this study will be used here to calculate @ VGS2 . In a similar way, the equations for the nMOSFET can be derived. 3. Results and discussion Veri®cation of the analytical models for subthreshold slope and o-state current was done by comparison with 2D numerical simulations [10] and with the experimental results for the pMOSFET taken from [6]. The dependence of subthreshold slope and o-state current on Vds, channel length L, Ge-concentration and channel doping was investigated. As a reference device, a Si-only transistor is used in case of a pMOSFET and a Si1ÿxGex-only transistor is used in case of a nMOSFET. In the latter case the reference device will change with Ge-concentration. The leakage current and subthreshold slope were calculated at both vVdsv=0.1 V and vVdsv=1.5 V. In Figs. 2 and 3, the leakage current at vVdsv=0.1 V is shown as function of the substrate doping concentration. The in¯uence of the Ge-concentration will be most imminent at low substrate doping concentrations since in that case the doping is not high enough to provide a low o-state current. In the high doping range, the built-in potential due to the high channel doping will be dominant, decreasing the in¯uence of the Ge incorporated in the design. In Fig. 4, the dependence on the Ge-molefraction is shown for both pMOS and nMOS devices. The comparison with numerical simulation results is excellent for the pMOS and good for the nMOS. As can be
Fig. 2. Leakage current of the pMOSFET at Vds=ÿ0.1 V as a function of substrate doping: tox=4 nm, L = 100 nm, L1=30 nm and the Si1ÿxGex-region is intrinsic. Three dierent Ge-concentrations are shown: 10, 20 and 30%.
seen from this ®gure, the Ge-concentration eectively decreases the o-state current of the devices over several orders of magnitude until about 75% Ge. Higher Ge-molefractions will not aect the current anymore. Around 75%, the Ge-molefraction will not decrease the bandgap anymore in the case of strained Si1ÿxGex
Fig. 3. Leakage current of the nMOSFET at Vds=0.1 V as a function of substrate doping: tox=4 nm, L = 100 nm, L1=30 nm and the strained Si source region is intrinsic. Three dierent Ge-concentrations are shown: 10, 20 and 30%.
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N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
Fig. 4. Leakage current of the pMOSFET and nMOSFET at vVdsv=0.1 V as a function of Ge-concentration. The strained Si (nMOS) or Si1ÿxGex (pMOS) source region is intrinsic and tox=4 nm, L = 100 nm, L1=30 nm, Nsub=8 1017 cmÿ3 (nMOS) and Nsub=7 1017 cmÿ3 (pMOS).
Fig. 5. Subthreshold slope as function of the channel length for both pMOS and nMOS. The pMOS has tox=4 nm, Nsub=7 1017 cmÿ3, L1=30 nm and an intrinsic Si0.9Ge0.1 source region. In case of the nMOS: tox=4 nm, Nsub=8 1017 cmÿ3, L1=30 nm, an intrinsic Si source region and a Si0.9Ge0.1 channel.
Fig. 6. Comparison of the Ids±Vgs curves of (a) a Si0.8Ge0.2/Si pMOSFET and its Si-only counterpart and (b) a Si/Si0.8Ge0.2 nMOSFET and its Si0.8Ge0.2-only counterpart; Both pMOS and nMOS devices have L = 100 nm, tox=4 nm, Nsub=8 1017 cmÿ3 and L1=30 nm.
N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
2179
Table 1 Comparison of the pMOSFET subthreshold slope and leakage current with experimental results for dierent substrate concentrations and Ge-concentrations Experimental Io (A/mm) L(nm) Vds=ÿ0.1 V 120 70 Vds=ÿ1.5 V 120 70
Analytical Io
Experimental S(mV/dec)
%Ge
Nsub
Average
± 10 10 20 15
1E+18 1E+18 5E+17 5E+17 1E+18
1.3Eÿ17 2Eÿ19 5Eÿ17 8.5Eÿ17 2Eÿ14
1Eÿ17 4Eÿ20 3Eÿ17 4Eÿ17 9Eÿ15
2Eÿ18 2Eÿ20 2.5Eÿ17 1Eÿ16 6Eÿ14
106 102 90 95 114
± 10 10 20 15
1E+18 1E+18 5E+17 5E+17 1E+18
9Eÿ15 3Eÿ17 1.4Eÿ15 5Eÿ15 3Eÿ11
5Eÿ15 1Eÿ17 6Eÿ16 5Eÿ15 2.5Eÿ11
7.00Eÿ15 3.20Eÿ17 1.06Eÿ15 5.25Eÿ15 1.2Eÿ11
121 109 94 103 175
Std dev
source layer (pMOS). In the case of the nMOS, the model for the bandgap discussed in [7] is not valid anymore for Ge concentrations higher than 75%. As is shown in Fig. 4, the in¯uence on the leakage current of the nMOS devices is much more pronounced than the in¯uence of the Ge-molefraction on the leakage current of the pMOS devices. A higher bandoset together with the higher substrate doping can account for this. In Fig. 5, the subthreshold slope of both pMOS and nMOS heterojunction devices is compared with their homojunction counterparts. A substantial decrease in subthreshold slope roll-up can be seen for the smallest channel lengths while the long channel subthreshold slope is unaected by the heterojunction. The Ids±Vgs characteristics of the vertical heterojunction transistor and its Si-only counterpart are shown in Figs. 6a and b. The inset of the ®gures shows the comparison of the analytical model for the heterojunction devices with numerical simulation. For both pMOS and nMOS this comparison is excellent. In all cases, a constant doping dependent mobility was used for the analytical model and the numerical simulations. As can be seen from the Ids ±Vgs curves the heterojunction devices show lower o-state currents, lower subthreshold slopes and better resistance against DIBL. The on-state current is slightly lower than the Si-only devices due to the intrinsically higher threshold voltage. Fig. 7 shows the ratio Ion/Io as a function of the Ge-concentration at Vds=0.1 V and Vds=1.5 V. The o-state current is taken at Vgs=0 V and the on-state current at Vgs=1.5 V. As can be seen from the plot, a maximum can be observed around 20% (Vds=0.1 V) for this particular layer set-up. The maximum is
Average
Analytical S
STD dev 2.5 1 2 2 3 4 2 2 5 16
115 108 97 99 108 138 113 98 103 166
slightly shifted towards lower Ge-concentrations for higher Vds and a decrease in maximum can be observed due to the DIBL eect. So initially the Ge-concentration will aect the ostate current much more than the on-state current (region 1 ). When the Ge-concentration becomes too high, degradation of the on-state current starts to occur (region 2 ). As a consequence, for applications where the ratio Ion/Io (e.g. in DRAMs) is of major importance, one can only use moderate Ge-concentrations to stay as close to this maximum or at least to stay in region 1. Finally, Table 1 shows the comparison of the analytical model with experimental results obtained for the pMOSFET. As it is mentioned in [6], the devices with L = 120 nm use a directly wet oxidised gate dielectric with tox=4 nm on the Si layers. Since the oxidation rate of the Si1ÿxGex layer is much higher, one must take into account the non-uniform SiO2 thickness and the increased interface density of states (Dit) while calculating the potentials [9] and current densities. The oxide thickness on the Si0.9Ge0.1 layer is about four times thicker than on the Si layer and Dit has to be taken around 2 1012 cmÿ2. In case of the 70 nm devices, an alternative oxidation strategy [11,12] has been used and the oxide thickness is more or less uniform with tox=6 nm. The comparison between theory and experiment is very good. 4. Conclusion An analytical model has been derived to investigate the in¯uence of the Ge-concentration on the leakage current and subthreshold slope of vertical heterojunc-
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N. Collaert, K. De Meyer / Solid-State Electronics 43 (1999) 2173±2180
References
Fig. 7. Ratio Ion/Io as function of the Ge-concentration for the nMOSFET at Vds=0.1 V and Vds=1.5 V: tox=4 nm, L = 100 nm, L1=30 nm and Nsub=7 1017 cmÿ3.
tion MOSFETs. The model shows a good agreement with 2D simulation results. The dependence of Io and S on channel length, substrate concentration and Geconcentration was studied. The heterojunction devices show lower leakage currents and better subthreshold slopes than their Si-only (for the pMOS) and Si1ÿxGex-only (for the nMOS) counterparts. The dierence is quite signi®cant in case of the deep sub 0.1 mm devices. Acknowledgements The authors would like to thank the European Commission for the ®nancial support in the framework of the ESPRIT IV LTR VAHMOS 2000 project no. 22495. Nadine Collaert would like to thank the IWT for granting her a fellowship.
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