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Anatomy of a clean room robot
World Abstracts on Microelectronics and Reliability ceramic lid with preflow lead-base solder is presented. The lid-sealing processes and the methods to test the hermeticity of the sealed package are identical to those for the Widely used gold-plated metal lid tackwelded with a gold-tin eutectic solder preform. The well known problems of solder bailing and solder bridging associated with the common lead-tin solder in this particular application are addressed, as are several processing parameters and geometric factors affecting their occurrence. The inexpensive ceramic lid with less precious lead-base solder has been used as a one-to-one substitute for gold-plated metal lids with gold-tin eutectic preforms in hermetic IC packages.
Design of a comprehensive process evaluation vehicle for development of small geometry CMOS process. A. BANDYOPADHYAY, e. A. GOVINDACHARYULU and M. J. ZARARI. Microeleetron. Reliab. 24, 905 (1984). The design of a comprehensive process evaluation vehicle for thorough evaluation of a small geometry CMOS process has been discussed in this paper. The process evaluation vehicle includes both parametric and functional test structures and is considered to be particularly useful for the development of a small geometry CMOS process. An alternative approach towards the design of control units. RAJIV JAIN and SURESHRAI. Microelectron. Reliab. 24, 1009 (1984). In this communication the individual advantages of both the hardwired and the microprogrammed control units have been exploited to suggest a hybrid approach for the decoding of instructions. The method is simple and straightforward. It retains the fast speed as well as the flexibility aspects. Furthermore, timing analysis has been carried out to justify the effectiveness of the proposed approach. A simple method of photomask yield optimization by defect inspection. S. N. GUPTA, A. K. BAGCHI,N. N. KUNDU and W. S. KHOKLE. Microelectron. Reliab. 24, 625 (1984). The quality of the photomask set decides to a large extent the quality and quantity of the device that will be produced. In order to ensure the quality of the photomasks, several sophisticated instruments are commercially available. However, in a research type of environment, the cost of such equipment can be prohibitive. In this paper, we propose a simple method of multiple master mask preparation with subsequent matching of defective die locations to optimize the master mask set. The advantage here is that a very good master mask set can be chosen so that minimum number of dies on the photomask set itself contribute to low wafer yield. The method is based on manual inspection of individual dies on photomasks and can be practically used for a complexity of up to 500 components. VLSI multilevel metallization. A. N. SAXENA and D. PRAMANIK.Solid St. Technol. 93 (December 1984). Multilevel metallization is most important in determining chip size, speed performance and yield of all VLSICs. As the technology advances toward Ultra Large Scale Integration and Wafer Scale Integration, the role of multilevel metallization becomes even more crucial. In fact, it becomes the limiting factor of technology enhancement. Multilevel metallization needs careful consideration of both conductors and insulators, and their associated technologies. A terminology for defining various layers, and classifying the materials is given. Present status and limitations are reviewed and future requirements discussed. While aluminum and its alloys will continue to be used widely, significant changes in contact metallurgy, replacement of polysilicon by polycides, strapping of diffused layers by silicides, use of refactory metals, and improved, defect-free insulator films with compressive stress are needed. Associated technologies such as dry etch of polycides, metals, sloped vias and planarization are extremely important. Improved diagnostic and
characterization techniques for defects, electromigration are also very important.
1169 hillocks and
Gas cooling enhancement technology for integrated circuit chips. TOHRU KISHIMOTO, ETSURO SASAKI and KUNIO MORIYA. IEEE Trans. Components Hybrids Mfg Technol. CHMT-7, 286 (1984). New approaches are described for increasing the capability of forced gas convection cooling for integrated circuit chips, using an enhanced heat transfer technique and a higher gas flow velocity in a closed-cycle flow. A turbulence promoting fin with low pressure loss has been developed and enhancement of the heat transfer coefficient using gas flow velocities up to 50m/s is examined using air and helium gas as coolants. By applying these techniques, the cooling capability of a package is investigated through the use of prototype equipment. Cooling of an alumina substrate (75 mm square) mounted with 25 chips (8mm square) can be cooled up to 200W in an air flow of 20 m/s. In helium gas convection cooling, the allowable heat dissipation increases to 300 W or more, and fan input power decreases to about one-fifth of that needed for air convection cooling. This cooling capability is equal to that of indirect water cooling. Photomask defects: causes and solutions. ARTHURC. TITUS. Semiconductor Int. 94 (October 1984). The 'perfect mask' is a result of understanding the problems encountered in photomask fabrication and then formulating a program to anticipate and circumvent these problems. Cast leads for surface attachment. JOHN R, FISHER. IEEE Trans. Components Hybrids Mfy Technol. CHMT-7, 306 (1984). The attachment ofleadless integrated circuit packages to printed circuit (PC) substrates is receiving growing attention as surface mounting technology advances to meet the demands of present and future product designs. The reliability issues associated with surface attachmment of these packages continue to be addressed and characterized with respect to package configuration, material properties, and interconnection methods. A novel technique is introduced for reliable and economical attachment of leadless integrated circuit (IC) packages to circuit substrates. Known as the cast lead process, it is based on a concept for controlling solder joint geometry in order to improve the stress and strain distributions within the joints. The basic sequence of operations established for cast lead fabrication and for surface mounting of processed packages will be presented and results for several reliability studies will be discussed. Practicalcomparison of LEC production methods for SI-GaAs. RICHARD L. LANE. Semiconductor Int. 68 (October 1984). Improvements in GaAs crystal pulling equipment are being forced by the needs for improved yield and quality and reduced production costs. Enhanced magnetron sputtering of planarized silica coatings. PING CHANG. Semiconductor Int. 79 (November 1984). Optimum planarized silica coatings, over many different circuit topographies, can be achieved by properly combining sputter deposition and bias etch rates. B-Si masks for storage ring X-ray lithography. R. E. ACOSTA, J. R, MALDONADO, L. K. TOWART and J. M. WARLAUMONT. Solid St. Technol. 205 (October 1984). The fabrication of masks used in X-ray lithography is described. The masks have a gold absorber layer electroplated over a substrate which consists of a thin boron-doped silicon membrane covered by a layer of polyimide. Measurements of the properties of the materials used in this application are presented.
Anatomy of a clean room robot. TOM PETERSON. Semiconductor Int. 58 (November 1984). Advances in control
1170
World Abstracts on Microelectronics and Reliability
capability and contamination-free design play a major role in the development of robots specifically for clean room fabrication. Lifetime of bonded contacts on thin film metallizations. HARTMANN H1EBER and KARIN PAPE. Proc. IEEE Reliab. Physics Conf. 128 (1984). Gold beams and wires are microwelded to a stable gold/platinum/titanium thin-film sandwich on silicon wafers. The contacts are subjected to simultaneous thermal and mechanical loads. The measured times-to-fracture are analyzed by mechanisms of creep-crack propagation. A creep rupture equation contains the stress exponent and the thermal activation energy of plastic flow as the material-specific parameters. The time-to-fracture is strongly affected by the texture of the beams and wires and by the geometry of the welded contact. The equation can be used for extrapolation in a temperature interval between 300 and 650K. Furnace loading systems review. RON ISCOFF. Semiconductor Int. 82 (August 1984). Non-contact furnace loading systems can reduce quartz particle contamination from process tubes while lowering downtime. Qualifying reduction reticles. PAUL CH1PMAN. Semiconductor Int. 68 (August 1984). Reticle quality has become a production issue that involves a high level of understanding between reticle maker and user. Use of radiant infrared in soldering surface mounted devices to printed circuit boards. STEPHENJ. DOW. Solid St. Technol. l 91
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , An interactive two-dimensional finite element process modelling package for a single user mini-computer. R. S. FERGUSON and J. G. DOHERTY. Solid-St. Electron. 27, 1043 (1984). The algorithms and models of an accurate finite element based simulation of the processing steps of semiconductor wafer fabrication are described. Properties of the latest generation of single user mini-computers allow the process engineer to use the computer package in an interactive mode. The process steps modelled are, implantation, oxidation/diffusion and annealing. Implantation models are based on the well-tested, onedimensional statistical distributions. Interaction between impurity atoms is assumed to be mainly through the built-in field. To obtain an accurate estimate of the built-in field, the non-linear Poisson equation is solved at the same nodes and in the same elements used for the simulation of the diffusion process. On making the assumption that small time steps are taken in the numerical formulation of the diffusion problem, the finite element equation system becomes linear and can be rapidly solved. Each impurity is assumed to diffuse independently in a non-uniform electric field, enhanced by a component due to the other impurities. Coupling between oxidation and diffusion is accounted for by ~ simple algorithm that deforms the solution mesh after the oxidising agent reacts with silicon to create a larger volume of SiO2. Computer-aided design of an eight bit binary counter N-MOS chip for large scale integration (LSI). ASHOK SRIVASTAVA, S. N. GUPTA and CHANDRA SHEKHAR. Micoelectron. Reliab. 24, 885 (1984). An integrated eight bit synchronous binary counter along with input/output circuits: gate protection, two phase clock, pad-out has been designed for MOS LSI. The counter has a master-slave flip-flop and a combinational logic to generate the next state, and outgoing carry outputs from this stage. The combination logic has been implemented using pass transistors and thus acts as a steering type logic. This type of logic is very fast, consumes lesser
(November 1984).The emission characteristics of area type infrared sources make them effective in the solder attachment of surface mounted devices to epoxy/glass and potyimide/glass printed circuit boards. These characteristics are contrasted with those of other types of sources. The operational design of furnace types is discussed relative to process applicability, and it is shown that area source infrared processing can ensure very good conditions for surface mount attachment to printed circuit board materials. Gold contacts to semiconductor devices. JAMES W. MAYER. Solid St. Technol. 149 (July 1984). The electronics revolution led by computers and microprocessors is based on the silicon integrated circuit. Gold contacts play a key role in the fabrication of integrated circuits. For microwave devices and integrated circuits made from compound semiconductors such as gallium arsenide, gold metallization is used for both ohmic and rectifying contacts. Influence of temperature on the potential and field distributions in microresistors and Halltrons for MOS integrated circuits. N. B. VELCHEV and I. R. PETROV. Electron Technol, 15, 35 (1982). The equations for the potential and field distributions along uniformly doped microresistors and Halltrons for MOS integrated circuits are generalized to include the influence of temperature and some additional technological parameters. A numerical analysis over the low temperature range is carried out and some results are presented. A comparison between uniform and nonuniform impurity distributions, corresponding to ion implantation with Gaussian profile, is made in the case of complete ionization.
SYSTEMS
AND
EQUIPMENTS
power and needs significantly less area for its implementation. Latest CAD techniques: interactive Graphics system of Applicon AGS/860 LSI Design Station, MOS circuit simulation program MSINC and Design Rule Check (DRC) program have been used for design and chip layout. The entire chip has been laid out in the area of 3 x 3 m m 2 including test devices and structures for testability analysis. The design is based on LOCOS N-MOS (E-D) technology and 8 micron design rules. The Electromask pattern generation (PG) tape has been prepared from Applicon for making chrome masks. A set of six masks have been used for the fabrication of device and die encapsulated in dual-in line package and tested for its performance. Counter works up to 5 MHz clock frequency as expected from design calculations. From 25 stage ring oscillator frequency measurement the gate delay comes out to be 6 nS. The counter design could easily be substituted as a subsystem/building block or cell in any MOS LSI system where it makes a part of it. A two level metal CMOS process for VLSI circuits. DON BARTON and CRAIG MAZE. Semiconductor Int. 98 (January 1985). A high density two-level metalization process uses an intermetal dielectric planarization technique that makes the process practical for VLSI circuits. Integrated T/R modules employ GaAs ICs. R. S. PENGELLY. Microwaves RF, 77 (February 1985). The design of a transmit/receive module for S-band phased-array radar has emphasized RF components that are compatible with MMIC construction. Thermal stress-free package for flip-chip devices. MASANOBU KOHARA, MUNEOHATTA, HIDEKI GENJYO, HIROSHISHIBATA and HIDEFUMINAKATA. IEEE Trans. Components Hybrids
Design of a comprehensive process evaluation vehicle for development of small geometry CMOS process. A. BANDYOPADHYAY, e. A. GOVINDACHARYULU and M. J. ZARARI. Microeleetron. Reliab. 24, 905 (1984). The design of a comprehensive process evaluation vehicle for thorough evaluation of a small geometry CMOS process has been discussed in this paper. The process evaluation vehicle includes both parametric and functional test structures and is considered to be particularly useful for the development of a small geometry CMOS process. An alternative approach towards the design of control units. RAJIV JAIN and SURESHRAI. Microelectron. Reliab. 24, 1009 (1984). In this communication the individual advantages of both the hardwired and the microprogrammed control units have been exploited to suggest a hybrid approach for the decoding of instructions. The method is simple and straightforward. It retains the fast speed as well as the flexibility aspects. Furthermore, timing analysis has been carried out to justify the effectiveness of the proposed approach. A simple method of photomask yield optimization by defect inspection. S. N. GUPTA, A. K. BAGCHI,N. N. KUNDU and W. S. KHOKLE. Microelectron. Reliab. 24, 625 (1984). The quality of the photomask set decides to a large extent the quality and quantity of the device that will be produced. In order to ensure the quality of the photomasks, several sophisticated instruments are commercially available. However, in a research type of environment, the cost of such equipment can be prohibitive. In this paper, we propose a simple method of multiple master mask preparation with subsequent matching of defective die locations to optimize the master mask set. The advantage here is that a very good master mask set can be chosen so that minimum number of dies on the photomask set itself contribute to low wafer yield. The method is based on manual inspection of individual dies on photomasks and can be practically used for a complexity of up to 500 components. VLSI multilevel metallization. A. N. SAXENA and D. PRAMANIK.Solid St. Technol. 93 (December 1984). Multilevel metallization is most important in determining chip size, speed performance and yield of all VLSICs. As the technology advances toward Ultra Large Scale Integration and Wafer Scale Integration, the role of multilevel metallization becomes even more crucial. In fact, it becomes the limiting factor of technology enhancement. Multilevel metallization needs careful consideration of both conductors and insulators, and their associated technologies. A terminology for defining various layers, and classifying the materials is given. Present status and limitations are reviewed and future requirements discussed. While aluminum and its alloys will continue to be used widely, significant changes in contact metallurgy, replacement of polysilicon by polycides, strapping of diffused layers by silicides, use of refactory metals, and improved, defect-free insulator films with compressive stress are needed. Associated technologies such as dry etch of polycides, metals, sloped vias and planarization are extremely important. Improved diagnostic and
characterization techniques for defects, electromigration are also very important.
1169 hillocks and
Gas cooling enhancement technology for integrated circuit chips. TOHRU KISHIMOTO, ETSURO SASAKI and KUNIO MORIYA. IEEE Trans. Components Hybrids Mfg Technol. CHMT-7, 286 (1984). New approaches are described for increasing the capability of forced gas convection cooling for integrated circuit chips, using an enhanced heat transfer technique and a higher gas flow velocity in a closed-cycle flow. A turbulence promoting fin with low pressure loss has been developed and enhancement of the heat transfer coefficient using gas flow velocities up to 50m/s is examined using air and helium gas as coolants. By applying these techniques, the cooling capability of a package is investigated through the use of prototype equipment. Cooling of an alumina substrate (75 mm square) mounted with 25 chips (8mm square) can be cooled up to 200W in an air flow of 20 m/s. In helium gas convection cooling, the allowable heat dissipation increases to 300 W or more, and fan input power decreases to about one-fifth of that needed for air convection cooling. This cooling capability is equal to that of indirect water cooling. Photomask defects: causes and solutions. ARTHURC. TITUS. Semiconductor Int. 94 (October 1984). The 'perfect mask' is a result of understanding the problems encountered in photomask fabrication and then formulating a program to anticipate and circumvent these problems. Cast leads for surface attachment. JOHN R, FISHER. IEEE Trans. Components Hybrids Mfy Technol. CHMT-7, 306 (1984). The attachment ofleadless integrated circuit packages to printed circuit (PC) substrates is receiving growing attention as surface mounting technology advances to meet the demands of present and future product designs. The reliability issues associated with surface attachmment of these packages continue to be addressed and characterized with respect to package configuration, material properties, and interconnection methods. A novel technique is introduced for reliable and economical attachment of leadless integrated circuit (IC) packages to circuit substrates. Known as the cast lead process, it is based on a concept for controlling solder joint geometry in order to improve the stress and strain distributions within the joints. The basic sequence of operations established for cast lead fabrication and for surface mounting of processed packages will be presented and results for several reliability studies will be discussed. Practicalcomparison of LEC production methods for SI-GaAs. RICHARD L. LANE. Semiconductor Int. 68 (October 1984). Improvements in GaAs crystal pulling equipment are being forced by the needs for improved yield and quality and reduced production costs. Enhanced magnetron sputtering of planarized silica coatings. PING CHANG. Semiconductor Int. 79 (November 1984). Optimum planarized silica coatings, over many different circuit topographies, can be achieved by properly combining sputter deposition and bias etch rates. B-Si masks for storage ring X-ray lithography. R. E. ACOSTA, J. R, MALDONADO, L. K. TOWART and J. M. WARLAUMONT. Solid St. Technol. 205 (October 1984). The fabrication of masks used in X-ray lithography is described. The masks have a gold absorber layer electroplated over a substrate which consists of a thin boron-doped silicon membrane covered by a layer of polyimide. Measurements of the properties of the materials used in this application are presented.
Anatomy of a clean room robot. TOM PETERSON. Semiconductor Int. 58 (November 1984). Advances in control
1170
World Abstracts on Microelectronics and Reliability
capability and contamination-free design play a major role in the development of robots specifically for clean room fabrication. Lifetime of bonded contacts on thin film metallizations. HARTMANN H1EBER and KARIN PAPE. Proc. IEEE Reliab. Physics Conf. 128 (1984). Gold beams and wires are microwelded to a stable gold/platinum/titanium thin-film sandwich on silicon wafers. The contacts are subjected to simultaneous thermal and mechanical loads. The measured times-to-fracture are analyzed by mechanisms of creep-crack propagation. A creep rupture equation contains the stress exponent and the thermal activation energy of plastic flow as the material-specific parameters. The time-to-fracture is strongly affected by the texture of the beams and wires and by the geometry of the welded contact. The equation can be used for extrapolation in a temperature interval between 300 and 650K. Furnace loading systems review. RON ISCOFF. Semiconductor Int. 82 (August 1984). Non-contact furnace loading systems can reduce quartz particle contamination from process tubes while lowering downtime. Qualifying reduction reticles. PAUL CH1PMAN. Semiconductor Int. 68 (August 1984). Reticle quality has become a production issue that involves a high level of understanding between reticle maker and user. Use of radiant infrared in soldering surface mounted devices to printed circuit boards. STEPHENJ. DOW. Solid St. Technol. l 91
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , An interactive two-dimensional finite element process modelling package for a single user mini-computer. R. S. FERGUSON and J. G. DOHERTY. Solid-St. Electron. 27, 1043 (1984). The algorithms and models of an accurate finite element based simulation of the processing steps of semiconductor wafer fabrication are described. Properties of the latest generation of single user mini-computers allow the process engineer to use the computer package in an interactive mode. The process steps modelled are, implantation, oxidation/diffusion and annealing. Implantation models are based on the well-tested, onedimensional statistical distributions. Interaction between impurity atoms is assumed to be mainly through the built-in field. To obtain an accurate estimate of the built-in field, the non-linear Poisson equation is solved at the same nodes and in the same elements used for the simulation of the diffusion process. On making the assumption that small time steps are taken in the numerical formulation of the diffusion problem, the finite element equation system becomes linear and can be rapidly solved. Each impurity is assumed to diffuse independently in a non-uniform electric field, enhanced by a component due to the other impurities. Coupling between oxidation and diffusion is accounted for by ~ simple algorithm that deforms the solution mesh after the oxidising agent reacts with silicon to create a larger volume of SiO2. Computer-aided design of an eight bit binary counter N-MOS chip for large scale integration (LSI). ASHOK SRIVASTAVA, S. N. GUPTA and CHANDRA SHEKHAR. Micoelectron. Reliab. 24, 885 (1984). An integrated eight bit synchronous binary counter along with input/output circuits: gate protection, two phase clock, pad-out has been designed for MOS LSI. The counter has a master-slave flip-flop and a combinational logic to generate the next state, and outgoing carry outputs from this stage. The combination logic has been implemented using pass transistors and thus acts as a steering type logic. This type of logic is very fast, consumes lesser
(November 1984).The emission characteristics of area type infrared sources make them effective in the solder attachment of surface mounted devices to epoxy/glass and potyimide/glass printed circuit boards. These characteristics are contrasted with those of other types of sources. The operational design of furnace types is discussed relative to process applicability, and it is shown that area source infrared processing can ensure very good conditions for surface mount attachment to printed circuit board materials. Gold contacts to semiconductor devices. JAMES W. MAYER. Solid St. Technol. 149 (July 1984). The electronics revolution led by computers and microprocessors is based on the silicon integrated circuit. Gold contacts play a key role in the fabrication of integrated circuits. For microwave devices and integrated circuits made from compound semiconductors such as gallium arsenide, gold metallization is used for both ohmic and rectifying contacts. Influence of temperature on the potential and field distributions in microresistors and Halltrons for MOS integrated circuits. N. B. VELCHEV and I. R. PETROV. Electron Technol, 15, 35 (1982). The equations for the potential and field distributions along uniformly doped microresistors and Halltrons for MOS integrated circuits are generalized to include the influence of temperature and some additional technological parameters. A numerical analysis over the low temperature range is carried out and some results are presented. A comparison between uniform and nonuniform impurity distributions, corresponding to ion implantation with Gaussian profile, is made in the case of complete ionization.
SYSTEMS
AND
EQUIPMENTS
power and needs significantly less area for its implementation. Latest CAD techniques: interactive Graphics system of Applicon AGS/860 LSI Design Station, MOS circuit simulation program MSINC and Design Rule Check (DRC) program have been used for design and chip layout. The entire chip has been laid out in the area of 3 x 3 m m 2 including test devices and structures for testability analysis. The design is based on LOCOS N-MOS (E-D) technology and 8 micron design rules. The Electromask pattern generation (PG) tape has been prepared from Applicon for making chrome masks. A set of six masks have been used for the fabrication of device and die encapsulated in dual-in line package and tested for its performance. Counter works up to 5 MHz clock frequency as expected from design calculations. From 25 stage ring oscillator frequency measurement the gate delay comes out to be 6 nS. The counter design could easily be substituted as a subsystem/building block or cell in any MOS LSI system where it makes a part of it. A two level metal CMOS process for VLSI circuits. DON BARTON and CRAIG MAZE. Semiconductor Int. 98 (January 1985). A high density two-level metalization process uses an intermetal dielectric planarization technique that makes the process practical for VLSI circuits. Integrated T/R modules employ GaAs ICs. R. S. PENGELLY. Microwaves RF, 77 (February 1985). The design of a transmit/receive module for S-band phased-array radar has emphasized RF components that are compatible with MMIC construction. Thermal stress-free package for flip-chip devices. MASANOBU KOHARA, MUNEOHATTA, HIDEKI GENJYO, HIROSHISHIBATA and HIDEFUMINAKATA. IEEE Trans. Components Hybrids