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Applications of the scanning electron microscope EBIC mode to semiconductor device evaluation and failure analysis
Applications of the scanning electron microscope EBIC mode to semiconductor device evaluation and failure analysis by R. H. Sorensen, I. Thomson and L. Adams t
This paper shows how the Electron Beam Induced Current (EBIC) mode of operation finds routine application in the failure analysis and evaluation of semiconductor devices for space application. . Most of the previously published work on EBIC has been of a theoretical nature and has concentrated on the quantitative aspect such as the measurement of minority carrier lifetime. The EBIC mode, however, also lends itself to the qualitative evaluation and analysis of comparatively complex semiconductor devices and in particular the study of diffusion spikes and similar effects. The routine application of the EBIC mode to practical device analysis is described and illustrated by case histories of device problems. Improvements in experimental techniques are proposed based on the work presented.
1. Introduction Most laboratories concerned with the manufacture or in-depth technical evaluation of semiconductor devices rely on the scanning electron microscope (SEM) for detailed physical analysis at chip level. Although the SEM has several useful modes of operation, the majority of users depend largely on topographical or elemental analysis using back-scattered and secondary electrons or secondary X-rays respectively. Thornton and co-workers pioneered the use of the SEM to reveal p-n junctions by monitoring the electrical current induced by the electron beam in an external circuit'. A recent review- shows that, in the last decade, a large number of applications have been found for this mode of operation which is generally called 'electron beam induced current' (or 'conductivity') i.e. 'EBIC', 'barrier electron voltaic effect' etc., but the most widely used term is EBIC. Most modern SEMs have the required instrumentation and display system incorporated in the equipment and, although this has brought the possibility of using EBIC from the research laboratory to most SEM users, it appears that only a small percentage of SEM users employ EBIC on a routine basis. In general EBIC has remained a research tool as is reflected in some of the work which has been published since the aforementioned review". This new work was concerned with theoretical calculations", measurement of basic t European Space Agency, European Space Research and Technology Centre, The Netherlands.
material parameters, e.g. minority carrier lifetime", new conductivity effects in GaAs MESFETss, observations of dislocations in pn junctions", and junction depth measurement in planar junctions". There is clearly a need to continually advance the theoretical aspects of this mode to reach quantitative physical understanding of the experimental effects as shown by Flat and Milnes for examples. On the other nand, the EBIC mode lends itself to the qualitative evaluation and analysis of comparatively complex semiconductor devices. This paper describes the routine application of the EBIC mode to everyday practical analysis. It is intended to show semiconductor components engineers and SEM users alike how EBIC can be applied to advantage outside the research laboratory. A number of different case histories which have arisen in the course of normal device work in a high reliability laboratory are presented to illustrate the range of problems which can be solv~ u~ing thistechnique. It is felt that few past papers have gtven newcomers to the field enough practical information to enable them to start practical work. Sufficient practical detail is therefore given so that other device analysts can apply the technique and know its limitations.
2. Experimental techniques 2.1 Instrumentation Figure 1 shows the simplest experimental arrangement by which the open circuit EBIC mode may be realised in
MICROELECTRONICS JOURNAL Vol. 11 No.1 © 1980 Mackintosh Publications Ltd.• Luton .
19
Applications of the scanning electron microscope EBIC mode etc continued from page 19
practice together with typical results. The device used for illustration is a PNPN Shockley diode switch with a locally shorted emitter structure at the cathode as shown in section and plane views in Fig. l(a) and (b) respectively. The incident beam generates electron-hole pairs in the semiconductor material and, wherever there is a potential difference, these pairs are separated. In the p quasi-static conditions with slow beam scan rates, we can simplify the semiconductor impedance to a resistor R, in a) parallel with a current source. If the input impedance of (a) Experimental arrangement for EBIC imaging and crossthe amplifier circuit is R, then the short-circuit EBIC section of P-N-P-N Shockley diode switch taken at line indicated on (b). signal will be detected if R,«;
b)
20
1
20kV. Figure Id shows the same line scan with R j = l O lI , 109 and 107 ohm corresponding the current ranges of to-II, to- 9and 10- 7A respectively, for the same beam voltage. As R, decreases, the mode ofoperation changes from open circuit induced voltage toward short-circuit induced current. In the current range of 10- 7A, the device operates closer to a true EBIC mode since the device impedance R, is in the megohm region. In most applications using a standard EBIC amplifier, the gain would be adjusted so that it operated in the 10-7 A range so that all the signals would remain out of saturation (P+N insulation diffusion signal is saturated at all other levels) and, as a consequence, the centre juction would not be detected. It is quite clear from the foregoing, that with any device structure it is necessary to vary the incident beam voltage and amplifier impedance to obtain optimum results. If the device structure IS not known in detail beforehand, then secondary electron images can help considerably in interpreting the detail found in the EBIC current and voltage signals. In most device work it is almost essential to use line scan signals together with Z modulated display. Other useful points regarding optimisation of signal detection and interpretation will be given in later sections on individual case histories. 2.2 Sample preparation In general, completed devices without lids can be examined directly in a simple holder and even chips can be mounted with a special probe unit if necessary. In the case where a cross-section of the component is required to determine details of junction position, uniformity or failure sites, it is necessary to follow certain procedures to prepare the sample. As far as we know, the only published work on EBIC of sections perpendicular to the plane of the junction have dealt with fractured samples'< H. Since routine EBIC work on polished cross-sections is more useful than on fractured sections, . especially in failure analysis, some experimental details on the techniques developed for this work are given here. The first thing to consider before preparing a component for EBIC cross-section examination in the SEM is to be sure of contacts to leads, e.g. a transistor's collector, base and emitter. If necessary, the leads should be extended before potting for external signal connections. Normal non-conductive transparent .potting compound can be used. The advantage of the transparent potting is the possibility of optical inspection of component during cross-section. The cross-section should be started from a side where it is possible to stop before any lead or chip wire can be broken. Standard grinding and polishing procedures can be followed but care should be taken with the use of ultrasonic cleaning especially when halfway through a lead, wire or chip. In cases of potting components with inner cavities (e.g. glass diodes), to avoid chip damage the inner cavity should be repotted as soon as the glass seal is broken. All examples ofEBIC on cross-sectioned components described later in this paper have been prepared after normal routine procedures with special attention only to avoid breakage of lead or wire connections. Dealing with non-conductive materials in the SEM also requires some special adjustments of the instruments but the amount of adjustments depends on the individual component charging. No standard procedures can be
given but normal careful operation of the SEM will be sufficient for EBIC investigation of polished crosssections.
3. Examples of EBIC applications In order to illustrate the range of problems which can be solved with EBIC techniques, a number of case histories are detailed in this section. It is intended to show how device construction and failure analysis problems may be approached using scanning in both the commonly used plane mode as shown in Fig. I and in the less commonly used cross-section mode. All examples discussed are taken from a range of problems from a simple diode construction analysis to a complex transistor failure analysis. 3.1 Construction analysis of diodes It is already been stated that it is more common to apply EBIC to planar structures but there are many instances where the determination ofPN junction positions in cross-section is necessary. Figure 2a illustrates the simplest example of this type of application for a P+N silicon planar diode where the metallisation completely conceals the junction from normal view. In order to confirm the junction position with another technique, another diode from the same lot was sectioned in the same way and etched for 5 minutes at room temperature in the Sirtl dislocation etch (1 part HF to 1 part of a solution of 50gm chromic acid in looml H 2 0 ). There is very good agreement between the results but the etching technique needs special care since slight over-etching can lead to erroneous results. The etched junction of Fig. 2b is deeper than shown by EBIC in Fig. 2a as a result of some over-etching. It should be noted that the apparent loss of EBIC signal in Fig. 2a at the P+N junction/oxide interface is
..1 )
:.>J
Fig.::! Identification of P+N junction position. (a) EBIC of cross-sectioned Si planar diode with a 30 KeV electron beam. (b) Secondary image of similar cross-sectioned diode after Sirtl dislocation etch. 21
Applications of the scanning electron microscope EBIC mode etc continued from page 21
purely a matter of presentation. This is due to the use of a line scan perpendicular to the plane of the bulk junction with a relatively fast frame scan. Scanning at right angles to this direction results in an EBIC signal for the 'lost' junction but the majority of the previously imaged junction is then 'lost'.
4.
Failure analysis of diodes
It was found during the 'bum-in' of a batch of high-
reliability optocouplers that the transfer characteristic reduced catastrophically. Detailed analysis of the devices showed that the cause of failure was a drastic reduction in light output from the infra-red GaAs LEOs during bum-in. The growth of dark line defects (DLDs) was the failure mode and, although this is a well known failure mode in GaAs LEDs I5 , there is little known about the exact failure mechanism. In the specificcase of DLDs in high radiance diodes, there is good evidence for a correlation with precipitates which penetrate the PN junction"; In the 'present case some failed LEOs were crosssectioned to locate the DLOs and also to attempt to find their cause. The GaAs AB etch 16 was used to reveal crystal defects and it was also found that it preferentially etched N material and the PN junction was thus delineated. This junction, which was stochiometrically grown using Si doped liquid phase epitaxy on <100> oriented N-type substrates, is extremely non-uniform compared with normal diffused junctions. EBIC was used on a polished section of the same device in order to confirm the non-uniformities and as seen in Figs. 3a and 3b, the agreement between EBIC and etching is excellent. A correlation was not found between junction non-uniformity and DLDs but further etching showed that there was a correlation between dislocation density andDLDs. p
N
Fig.4
Combined secondary electron and EBIC image of intact GaAs LED showing location of non-uniform P-N junction.
It is interesting to note that, under the right conditions, not only the PN junctions but the NN+ interface can be determined using EBIC or voltage modes. Figure 5 shows both junctions simultaneously and since the NN+ signal is about one-tenth that of the junction, it can easily be missed. Since the NN+ signal has the same polarity a_s that of the junction, it is known that it is due to a resistivity change and not a type of change. It is important to determine the signal polarity in a case like this since the junction could be misinterpreted and thought to be a weak 'ghost' PN junction. From line scans it is known that the diffusion lengths are much shorter than the N region width so there is no interference between the P+N and NN+ EBIC signals. If the base width to diffusion length ratio is not high, then the weaker junction signal (NN+ in this case) may be totally lost in the 'tail' of the PN junction signal.
?
• P+
) Fig. 3
SEM images of polished cross-sectioned LED showing the PN junctions non-uniformity using EBIC mode (a) and preferential etched techniques (b).
Since this junction non-uniformity could have other detrimental effects, the degree of non-uniformity was measured on a larger number of GaAs LEOs. It was found that EBIC could be applied successfully and nondestructively to intact LEOs. Figure 4 shows an example of this application where, not only is the junction position and non-uniformity evident, but also its relationship to other defects (e.g. chip-out) which are not normally easily seen. 22
Fig.5
~N":I
I
N+
7.5 KeV EBIC mode line scan showing P+N junction and NN+ interface of cross-sectioned GaAs LED of type shown in Fig. 4.
4.1 Transistor failure analysis There have been a number of failures in space equipment involving 2N3810 dual PNP transistors and an investigation was made into the failed devices. Electrical measurements always gave the same indications viz. an emitter-collector resistive short and when a collector-base bias was applied, good emitterbase diode characteristic resulted. These characteristics indicated that the failure was due to a bulk short circuit, possibly a molten plug of P type material. Normal topographical analysis of these failures indicates a surface melt as shown in Fig. 6 but there is no indication why such a short-circuit should take place. It was
b)
(a)
SEM 30 KeV secondary electron plane viewof surface melt close to emitter metallisation.
(b) SEM 10 KeV secondary electron/EBIC image of crosssectioned failed transistor indicating junction positions with diffusion spike in base junction and short circuit plug of AI under emitter ball bond.
(c) SEM 5 KeV secondary electronjEBIC image of cross-sectioned non-failed 2N3810 transistor indicating base junction with diffusion spikes and areas with lost EBIC signal. Inset shows missing EBIC signal recovered by altered SEM settings. e tw:Jr k
l
Base
p
(d)
SEM 5 KeV secondary electron image of the samechip after Sirtl etch. Note metallurgical PN junctions, PP+ interface and dislocation network with respect to EBIC signal information . Fig. 6
Failure analysis of 2N3810PNP transistor with emitter-collector resistiveshort.
therefore necessary to section the device and the EBIC mode was used to determine the junction position. The emitter-collector short-circuit region was located underneath the AI metallisatiori, as shown in Fig. 6b . In addition to the short circuit, a plug of AI was found which was obviously a localised melt which was only partially visible from the surface features of Fig. 6a. Another gross feature worthy of mention to Fig. 6b is the apparent diffusion 'spike' in the base junction to the left of the short-circuit. At first sight it would appear as if this diffusion 'spike' is directly related to the failure. Other (non-failed) 2N38 10 transistors showed similar features. Further examinations of these features have been carried out and Fig. 6c shows EBIC mode signals on a cross-section of a non-failed 2N381O transistor chip. There are diffusion 'spikes' and also areas where the
EBIC signal is lost. The inset half way along the chip shows the same area as above under different conditions where the EBIC signal was, in fact, complete. Not only are non-uniformities apparent, but also new features such as a single line are revealed. Fig. 6d shows exactly the same chip after a 2 minute Sirtl etch which revealed the metallurgical PN junctions, PP+ interface and dislocation networks. There is a correspondence between loss of EBIC signal at the junction and dislocation networks crossing the junction. Diffusion 'spikes' on the other hand, do not appear on the metallurgical junction, but show as faintly etched . triangular defects which are most likely to be stacking faults in the epitaxial layer. It cannot be conclusively stated that the base junction had diffusion 'spikes' but it is quite obvious that it did contain a considerable 23
Applications of the scanning electron microscope EBIC mode etc continued from page 23
number of crystal defects. This example illustrates the need for care when interpreting EBIC mode signals since crystal defects which cross or closely approach the junction can either enhance or degrade the EBIC signal. Since this does not occur in apredictable manner it is advisable to use a combination of EBIC and etching techniques to solve this type of problem. It is important to note that normal device quality material does not show these anomalous contrasts. Other transistor structures such as phototransistors microwave bipolar transistors, MaS FETs and JFETs have been examined in the normal planar mode with no difficulty. The technique previously described in detail for a PNPN switching diode can be applied equally well to a wide range of device structures as long as the same precautions are taken, 4.2 Integrated circuit failure analysis Application of EBIC to integrated circuits is generally quite complex since it is much more difficult to predict the signal". It is', therefore, more difficult to determine wh~re the failure has occurred unless a comparison can Demade with either a non-failed device of exactly the same type or another non-failed element on the same device. Figures 7a and 7b shows the example of the detection of a failed input TTL transistor compared with a good transistor, The two emitters of the failed transistor are clearly short-circuited to the base and there is a larger damage region visible between the emitter contact metallisations than can be seen from a topographical examination. In this case, the EBIC mode confirms the measured electrical performance. Further analysis could be carried out by sectioning as in the previous examples for diodes and transistors since there is very little more information which can be obtained from planar EBIC analysis. Gate A
r-
t.e 3
The accelerating voltage of the SEM must be optimised for depth of penetration, having due regard for intervening layers such as glassivation and metaIIisation, as well as junction depths. A too low accelerating voltage may result in a loss of junction signal due to the beam being stopped in intervening layers, a too high accelerating voltage may result in the loss of information from shallow junctions. Both effects are illustrated in Fig. 1. Resolution is also degraded by beam spreading, the carrier generation volume is typically 1.5JLm in diameter at lOkV9 • The impedance of the device under analysis with respect to the input impedance of the specimen current amplifier has a profound effect on the EBIC signal and in certain cases, as illustrated in this paper, it may be advantageous to image the open circuit voltage of the device rather than the 'true' EBIC signal. The device underanalysis may impose limitations, primarily due to carrier diffusion lengths compared with junction separation. As the diffusion length becomes comparable with junction separation the detection of a junction becomes more difficult. Figure 5 shows that with a comparatively small diffusion length the junction signal is easily detectable. Anomalous effects which may be encountered are a time dependence of the EBIC signal and its enhancement or extinction at some considerable distance from the junction. These effects are particularly noticeable on cross-sectioned samples. The time dependence may be a function of specimen charging if cross-sectioned samples are embedded in an insulating potting compound or possibly electron beam polymerisation of hydrocarbons. Time dependent effects were observed by Thornton! and attributed to surface charging, however, we have seen these effects only in devices exhibiting other anomalies generally attributed to poor quality starting material as evidenced by etching techniques. It may be that the time dependence of the EBIC signal is itself significant although we do not have an adequate explanation of this. In conclusion we have shown in this paper that the EBIC mode of operation is applicable in a routine qualitative manner to a variety of device analyses. The preparation of samples requires no special techniques other than the normal degree of care required in normal failure analysis. It is to be hoped that this paper will encourage other workers in the field to apply EBIC techniques on a routine basis.
6. References J
a)
Fig.7
5.
hI EBIC plane of view of a failed TIL integrated circuit showing one good and one failed transistor. Experimental conditions were the same for both transistors.
Conclusion
For successful EBIC operation it is important to recognise the effect of SEM operating parameters and the inherent limitations of the technique imposed by device technology and instrumentation. Anomalous effects may be encountered in the application of EBIC, examples of this have been presented in this paper and at this present time we can only speculate as to their origin. 24
[1] Thornton, P. R., "Scanning Electron Microscopy". Pub. Chapman & Hall, 1968. [2] Leedy, K. 0., "A Bibliography on Electron Beam Induced Current Analysis of Semiconductor Devices", Solid State Tech., p.45-48, February 1977. [3] van Roos, 0., "Determination ofBulk Diffusion Lengths for Angle Lapped Material via the SEM. A Theoretical Analysis". JPL Publication p.78-47, May 1978. [4] Possin, G. E., Adler, M. S.~ and Baliga, B. J., "Lifetime Profile Measurements in Heavily Doped Emitter Structures using Electron Beams", 1978Internation Electron Devices Meeting, Technical Digest. p.324-327. [5] May, J. L., Bellier, S. P., and Haythomthwaite, R. E, "A Novel Electron Beam Technique for Studying GaAs FETs", Proc. Advanced Techniques on Failure Analysis, p.1l4-120,1977. [6] Holt, D. B., and Ogden, R., "Observations of Dislocations in a Silicon Phototransistor by Scanning
Electron Microscopy using the Barrier Electron Voltaic Effect", Solid-State Electron. 19, p.37-40, 1976. [7] Chi, Jin-Yong, and Gatos, H . C., " Non-Destructive Determination of the Depth ofPlanarPN Junctions by Scanning Electron Microscopy", IEEE Trans. Electron Devices, ED 24(12), p.1366-1368, December 1977. [8] Hat, A., and Milnes, A . G., " Interpretation of Scanning Electron Microscope Measurements of Minority Carrier Diffusion Lengths in Semiconductors", INT. J. Electronics, 44(6), p.629-639, 1978. [9] Holt, D . B., Chap. 8 in "Q uantitative Scanning Electron Microscopy", edited byD. B. Holt, M. D. Muir, P. R. Grant and I. M. Boswarva, Academic Press, London, 1974. [10] Oroshnik, J., and Many, A ., Solid-State Electronics, 1, p.46,1960. [11] Baev, I. A., and Valyashko, E . c., "Study of the Homogeneity of Semiconductor Crystals with the Use of a Moving Light Probe", Soviet Phys.
Phenomena on Semiconductor Devices by a Light Spot Scanning Method", Solid-State Electron, 10, p.235-239,1967. [13] Wendell, K., and Taylor, R., " Rapid Evaluation of Proce ssing Geometries by the Examination of Cleaved Samples in the SEM". Proc. Advanced Techniques in Failure Analysis Symposium, September 1977. [14] Child, M. R., Ranasinghe, D . W., and White, D., "Applications of the Scanning Electron Microscope in the Development of Microtechnology". Ibid . [15] O'Hara, S., Hutchinson, P. W., Davis, R., and Dobson, P. S., "Defect-Induced Degradation in HighRadiance Lamps", Proc. Sixth International Symposium on Gallium Arsenide and Related Compounds, Edinburgh Conference, p.379-387, September 1976. [16] Stirland, D. J., "The AB Etch: A Reappraisal", ibid, p.150-157. [17] Galloway, K. F., Leedy, K. 0., and Keery, W. J., "Electron-Beam-Induced Currents in Simple Device Structures", IEEE Trans. PHP-12, p.231-236, September 1976.
First presented at the A TFA - 79 Symposium in Los Angeles, California, USA.
25
This paper shows how the Electron Beam Induced Current (EBIC) mode of operation finds routine application in the failure analysis and evaluation of semiconductor devices for space application. . Most of the previously published work on EBIC has been of a theoretical nature and has concentrated on the quantitative aspect such as the measurement of minority carrier lifetime. The EBIC mode, however, also lends itself to the qualitative evaluation and analysis of comparatively complex semiconductor devices and in particular the study of diffusion spikes and similar effects. The routine application of the EBIC mode to practical device analysis is described and illustrated by case histories of device problems. Improvements in experimental techniques are proposed based on the work presented.
1. Introduction Most laboratories concerned with the manufacture or in-depth technical evaluation of semiconductor devices rely on the scanning electron microscope (SEM) for detailed physical analysis at chip level. Although the SEM has several useful modes of operation, the majority of users depend largely on topographical or elemental analysis using back-scattered and secondary electrons or secondary X-rays respectively. Thornton and co-workers pioneered the use of the SEM to reveal p-n junctions by monitoring the electrical current induced by the electron beam in an external circuit'. A recent review- shows that, in the last decade, a large number of applications have been found for this mode of operation which is generally called 'electron beam induced current' (or 'conductivity') i.e. 'EBIC', 'barrier electron voltaic effect' etc., but the most widely used term is EBIC. Most modern SEMs have the required instrumentation and display system incorporated in the equipment and, although this has brought the possibility of using EBIC from the research laboratory to most SEM users, it appears that only a small percentage of SEM users employ EBIC on a routine basis. In general EBIC has remained a research tool as is reflected in some of the work which has been published since the aforementioned review". This new work was concerned with theoretical calculations", measurement of basic t European Space Agency, European Space Research and Technology Centre, The Netherlands.
material parameters, e.g. minority carrier lifetime", new conductivity effects in GaAs MESFETss, observations of dislocations in pn junctions", and junction depth measurement in planar junctions". There is clearly a need to continually advance the theoretical aspects of this mode to reach quantitative physical understanding of the experimental effects as shown by Flat and Milnes for examples. On the other nand, the EBIC mode lends itself to the qualitative evaluation and analysis of comparatively complex semiconductor devices. This paper describes the routine application of the EBIC mode to everyday practical analysis. It is intended to show semiconductor components engineers and SEM users alike how EBIC can be applied to advantage outside the research laboratory. A number of different case histories which have arisen in the course of normal device work in a high reliability laboratory are presented to illustrate the range of problems which can be solv~ u~ing thistechnique. It is felt that few past papers have gtven newcomers to the field enough practical information to enable them to start practical work. Sufficient practical detail is therefore given so that other device analysts can apply the technique and know its limitations.
2. Experimental techniques 2.1 Instrumentation Figure 1 shows the simplest experimental arrangement by which the open circuit EBIC mode may be realised in
MICROELECTRONICS JOURNAL Vol. 11 No.1 © 1980 Mackintosh Publications Ltd.• Luton .
19
Applications of the scanning electron microscope EBIC mode etc continued from page 19
practice together with typical results. The device used for illustration is a PNPN Shockley diode switch with a locally shorted emitter structure at the cathode as shown in section and plane views in Fig. l(a) and (b) respectively. The incident beam generates electron-hole pairs in the semiconductor material and, wherever there is a potential difference, these pairs are separated. In the p quasi-static conditions with slow beam scan rates, we can simplify the semiconductor impedance to a resistor R, in a) parallel with a current source. If the input impedance of (a) Experimental arrangement for EBIC imaging and crossthe amplifier circuit is R, then the short-circuit EBIC section of P-N-P-N Shockley diode switch taken at line indicated on (b). signal will be detected if R,«;
b)
20
1
20kV. Figure Id shows the same line scan with R j = l O lI , 109 and 107 ohm corresponding the current ranges of to-II, to- 9and 10- 7A respectively, for the same beam voltage. As R, decreases, the mode ofoperation changes from open circuit induced voltage toward short-circuit induced current. In the current range of 10- 7A, the device operates closer to a true EBIC mode since the device impedance R, is in the megohm region. In most applications using a standard EBIC amplifier, the gain would be adjusted so that it operated in the 10-7 A range so that all the signals would remain out of saturation (P+N insulation diffusion signal is saturated at all other levels) and, as a consequence, the centre juction would not be detected. It is quite clear from the foregoing, that with any device structure it is necessary to vary the incident beam voltage and amplifier impedance to obtain optimum results. If the device structure IS not known in detail beforehand, then secondary electron images can help considerably in interpreting the detail found in the EBIC current and voltage signals. In most device work it is almost essential to use line scan signals together with Z modulated display. Other useful points regarding optimisation of signal detection and interpretation will be given in later sections on individual case histories. 2.2 Sample preparation In general, completed devices without lids can be examined directly in a simple holder and even chips can be mounted with a special probe unit if necessary. In the case where a cross-section of the component is required to determine details of junction position, uniformity or failure sites, it is necessary to follow certain procedures to prepare the sample. As far as we know, the only published work on EBIC of sections perpendicular to the plane of the junction have dealt with fractured samples'< H. Since routine EBIC work on polished cross-sections is more useful than on fractured sections, . especially in failure analysis, some experimental details on the techniques developed for this work are given here. The first thing to consider before preparing a component for EBIC cross-section examination in the SEM is to be sure of contacts to leads, e.g. a transistor's collector, base and emitter. If necessary, the leads should be extended before potting for external signal connections. Normal non-conductive transparent .potting compound can be used. The advantage of the transparent potting is the possibility of optical inspection of component during cross-section. The cross-section should be started from a side where it is possible to stop before any lead or chip wire can be broken. Standard grinding and polishing procedures can be followed but care should be taken with the use of ultrasonic cleaning especially when halfway through a lead, wire or chip. In cases of potting components with inner cavities (e.g. glass diodes), to avoid chip damage the inner cavity should be repotted as soon as the glass seal is broken. All examples ofEBIC on cross-sectioned components described later in this paper have been prepared after normal routine procedures with special attention only to avoid breakage of lead or wire connections. Dealing with non-conductive materials in the SEM also requires some special adjustments of the instruments but the amount of adjustments depends on the individual component charging. No standard procedures can be
given but normal careful operation of the SEM will be sufficient for EBIC investigation of polished crosssections.
3. Examples of EBIC applications In order to illustrate the range of problems which can be solved with EBIC techniques, a number of case histories are detailed in this section. It is intended to show how device construction and failure analysis problems may be approached using scanning in both the commonly used plane mode as shown in Fig. I and in the less commonly used cross-section mode. All examples discussed are taken from a range of problems from a simple diode construction analysis to a complex transistor failure analysis. 3.1 Construction analysis of diodes It is already been stated that it is more common to apply EBIC to planar structures but there are many instances where the determination ofPN junction positions in cross-section is necessary. Figure 2a illustrates the simplest example of this type of application for a P+N silicon planar diode where the metallisation completely conceals the junction from normal view. In order to confirm the junction position with another technique, another diode from the same lot was sectioned in the same way and etched for 5 minutes at room temperature in the Sirtl dislocation etch (1 part HF to 1 part of a solution of 50gm chromic acid in looml H 2 0 ). There is very good agreement between the results but the etching technique needs special care since slight over-etching can lead to erroneous results. The etched junction of Fig. 2b is deeper than shown by EBIC in Fig. 2a as a result of some over-etching. It should be noted that the apparent loss of EBIC signal in Fig. 2a at the P+N junction/oxide interface is
..1 )
:.>J
Fig.::! Identification of P+N junction position. (a) EBIC of cross-sectioned Si planar diode with a 30 KeV electron beam. (b) Secondary image of similar cross-sectioned diode after Sirtl dislocation etch. 21
Applications of the scanning electron microscope EBIC mode etc continued from page 21
purely a matter of presentation. This is due to the use of a line scan perpendicular to the plane of the bulk junction with a relatively fast frame scan. Scanning at right angles to this direction results in an EBIC signal for the 'lost' junction but the majority of the previously imaged junction is then 'lost'.
4.
Failure analysis of diodes
It was found during the 'bum-in' of a batch of high-
reliability optocouplers that the transfer characteristic reduced catastrophically. Detailed analysis of the devices showed that the cause of failure was a drastic reduction in light output from the infra-red GaAs LEOs during bum-in. The growth of dark line defects (DLDs) was the failure mode and, although this is a well known failure mode in GaAs LEDs I5 , there is little known about the exact failure mechanism. In the specificcase of DLDs in high radiance diodes, there is good evidence for a correlation with precipitates which penetrate the PN junction"; In the 'present case some failed LEOs were crosssectioned to locate the DLOs and also to attempt to find their cause. The GaAs AB etch 16 was used to reveal crystal defects and it was also found that it preferentially etched N material and the PN junction was thus delineated. This junction, which was stochiometrically grown using Si doped liquid phase epitaxy on <100> oriented N-type substrates, is extremely non-uniform compared with normal diffused junctions. EBIC was used on a polished section of the same device in order to confirm the non-uniformities and as seen in Figs. 3a and 3b, the agreement between EBIC and etching is excellent. A correlation was not found between junction non-uniformity and DLDs but further etching showed that there was a correlation between dislocation density andDLDs. p
N
Fig.4
Combined secondary electron and EBIC image of intact GaAs LED showing location of non-uniform P-N junction.
It is interesting to note that, under the right conditions, not only the PN junctions but the NN+ interface can be determined using EBIC or voltage modes. Figure 5 shows both junctions simultaneously and since the NN+ signal is about one-tenth that of the junction, it can easily be missed. Since the NN+ signal has the same polarity a_s that of the junction, it is known that it is due to a resistivity change and not a type of change. It is important to determine the signal polarity in a case like this since the junction could be misinterpreted and thought to be a weak 'ghost' PN junction. From line scans it is known that the diffusion lengths are much shorter than the N region width so there is no interference between the P+N and NN+ EBIC signals. If the base width to diffusion length ratio is not high, then the weaker junction signal (NN+ in this case) may be totally lost in the 'tail' of the PN junction signal.
?
• P+
) Fig. 3
SEM images of polished cross-sectioned LED showing the PN junctions non-uniformity using EBIC mode (a) and preferential etched techniques (b).
Since this junction non-uniformity could have other detrimental effects, the degree of non-uniformity was measured on a larger number of GaAs LEOs. It was found that EBIC could be applied successfully and nondestructively to intact LEOs. Figure 4 shows an example of this application where, not only is the junction position and non-uniformity evident, but also its relationship to other defects (e.g. chip-out) which are not normally easily seen. 22
Fig.5
~N":I
I
N+
7.5 KeV EBIC mode line scan showing P+N junction and NN+ interface of cross-sectioned GaAs LED of type shown in Fig. 4.
4.1 Transistor failure analysis There have been a number of failures in space equipment involving 2N3810 dual PNP transistors and an investigation was made into the failed devices. Electrical measurements always gave the same indications viz. an emitter-collector resistive short and when a collector-base bias was applied, good emitterbase diode characteristic resulted. These characteristics indicated that the failure was due to a bulk short circuit, possibly a molten plug of P type material. Normal topographical analysis of these failures indicates a surface melt as shown in Fig. 6 but there is no indication why such a short-circuit should take place. It was
b)
(a)
SEM 30 KeV secondary electron plane viewof surface melt close to emitter metallisation.
(b) SEM 10 KeV secondary electron/EBIC image of crosssectioned failed transistor indicating junction positions with diffusion spike in base junction and short circuit plug of AI under emitter ball bond.
(c) SEM 5 KeV secondary electronjEBIC image of cross-sectioned non-failed 2N3810 transistor indicating base junction with diffusion spikes and areas with lost EBIC signal. Inset shows missing EBIC signal recovered by altered SEM settings. e tw:Jr k
l
Base
p
(d)
SEM 5 KeV secondary electron image of the samechip after Sirtl etch. Note metallurgical PN junctions, PP+ interface and dislocation network with respect to EBIC signal information . Fig. 6
Failure analysis of 2N3810PNP transistor with emitter-collector resistiveshort.
therefore necessary to section the device and the EBIC mode was used to determine the junction position. The emitter-collector short-circuit region was located underneath the AI metallisatiori, as shown in Fig. 6b . In addition to the short circuit, a plug of AI was found which was obviously a localised melt which was only partially visible from the surface features of Fig. 6a. Another gross feature worthy of mention to Fig. 6b is the apparent diffusion 'spike' in the base junction to the left of the short-circuit. At first sight it would appear as if this diffusion 'spike' is directly related to the failure. Other (non-failed) 2N38 10 transistors showed similar features. Further examinations of these features have been carried out and Fig. 6c shows EBIC mode signals on a cross-section of a non-failed 2N381O transistor chip. There are diffusion 'spikes' and also areas where the
EBIC signal is lost. The inset half way along the chip shows the same area as above under different conditions where the EBIC signal was, in fact, complete. Not only are non-uniformities apparent, but also new features such as a single line are revealed. Fig. 6d shows exactly the same chip after a 2 minute Sirtl etch which revealed the metallurgical PN junctions, PP+ interface and dislocation networks. There is a correspondence between loss of EBIC signal at the junction and dislocation networks crossing the junction. Diffusion 'spikes' on the other hand, do not appear on the metallurgical junction, but show as faintly etched . triangular defects which are most likely to be stacking faults in the epitaxial layer. It cannot be conclusively stated that the base junction had diffusion 'spikes' but it is quite obvious that it did contain a considerable 23
Applications of the scanning electron microscope EBIC mode etc continued from page 23
number of crystal defects. This example illustrates the need for care when interpreting EBIC mode signals since crystal defects which cross or closely approach the junction can either enhance or degrade the EBIC signal. Since this does not occur in apredictable manner it is advisable to use a combination of EBIC and etching techniques to solve this type of problem. It is important to note that normal device quality material does not show these anomalous contrasts. Other transistor structures such as phototransistors microwave bipolar transistors, MaS FETs and JFETs have been examined in the normal planar mode with no difficulty. The technique previously described in detail for a PNPN switching diode can be applied equally well to a wide range of device structures as long as the same precautions are taken, 4.2 Integrated circuit failure analysis Application of EBIC to integrated circuits is generally quite complex since it is much more difficult to predict the signal". It is', therefore, more difficult to determine wh~re the failure has occurred unless a comparison can Demade with either a non-failed device of exactly the same type or another non-failed element on the same device. Figures 7a and 7b shows the example of the detection of a failed input TTL transistor compared with a good transistor, The two emitters of the failed transistor are clearly short-circuited to the base and there is a larger damage region visible between the emitter contact metallisations than can be seen from a topographical examination. In this case, the EBIC mode confirms the measured electrical performance. Further analysis could be carried out by sectioning as in the previous examples for diodes and transistors since there is very little more information which can be obtained from planar EBIC analysis. Gate A
r-
t.e 3
The accelerating voltage of the SEM must be optimised for depth of penetration, having due regard for intervening layers such as glassivation and metaIIisation, as well as junction depths. A too low accelerating voltage may result in a loss of junction signal due to the beam being stopped in intervening layers, a too high accelerating voltage may result in the loss of information from shallow junctions. Both effects are illustrated in Fig. 1. Resolution is also degraded by beam spreading, the carrier generation volume is typically 1.5JLm in diameter at lOkV9 • The impedance of the device under analysis with respect to the input impedance of the specimen current amplifier has a profound effect on the EBIC signal and in certain cases, as illustrated in this paper, it may be advantageous to image the open circuit voltage of the device rather than the 'true' EBIC signal. The device underanalysis may impose limitations, primarily due to carrier diffusion lengths compared with junction separation. As the diffusion length becomes comparable with junction separation the detection of a junction becomes more difficult. Figure 5 shows that with a comparatively small diffusion length the junction signal is easily detectable. Anomalous effects which may be encountered are a time dependence of the EBIC signal and its enhancement or extinction at some considerable distance from the junction. These effects are particularly noticeable on cross-sectioned samples. The time dependence may be a function of specimen charging if cross-sectioned samples are embedded in an insulating potting compound or possibly electron beam polymerisation of hydrocarbons. Time dependent effects were observed by Thornton! and attributed to surface charging, however, we have seen these effects only in devices exhibiting other anomalies generally attributed to poor quality starting material as evidenced by etching techniques. It may be that the time dependence of the EBIC signal is itself significant although we do not have an adequate explanation of this. In conclusion we have shown in this paper that the EBIC mode of operation is applicable in a routine qualitative manner to a variety of device analyses. The preparation of samples requires no special techniques other than the normal degree of care required in normal failure analysis. It is to be hoped that this paper will encourage other workers in the field to apply EBIC techniques on a routine basis.
6. References J
a)
Fig.7
5.
hI EBIC plane of view of a failed TIL integrated circuit showing one good and one failed transistor. Experimental conditions were the same for both transistors.
Conclusion
For successful EBIC operation it is important to recognise the effect of SEM operating parameters and the inherent limitations of the technique imposed by device technology and instrumentation. Anomalous effects may be encountered in the application of EBIC, examples of this have been presented in this paper and at this present time we can only speculate as to their origin. 24
[1] Thornton, P. R., "Scanning Electron Microscopy". Pub. Chapman & Hall, 1968. [2] Leedy, K. 0., "A Bibliography on Electron Beam Induced Current Analysis of Semiconductor Devices", Solid State Tech., p.45-48, February 1977. [3] van Roos, 0., "Determination ofBulk Diffusion Lengths for Angle Lapped Material via the SEM. A Theoretical Analysis". JPL Publication p.78-47, May 1978. [4] Possin, G. E., Adler, M. S.~ and Baliga, B. J., "Lifetime Profile Measurements in Heavily Doped Emitter Structures using Electron Beams", 1978Internation Electron Devices Meeting, Technical Digest. p.324-327. [5] May, J. L., Bellier, S. P., and Haythomthwaite, R. E, "A Novel Electron Beam Technique for Studying GaAs FETs", Proc. Advanced Techniques on Failure Analysis, p.1l4-120,1977. [6] Holt, D. B., and Ogden, R., "Observations of Dislocations in a Silicon Phototransistor by Scanning
Electron Microscopy using the Barrier Electron Voltaic Effect", Solid-State Electron. 19, p.37-40, 1976. [7] Chi, Jin-Yong, and Gatos, H . C., " Non-Destructive Determination of the Depth ofPlanarPN Junctions by Scanning Electron Microscopy", IEEE Trans. Electron Devices, ED 24(12), p.1366-1368, December 1977. [8] Hat, A., and Milnes, A . G., " Interpretation of Scanning Electron Microscope Measurements of Minority Carrier Diffusion Lengths in Semiconductors", INT. J. Electronics, 44(6), p.629-639, 1978. [9] Holt, D . B., Chap. 8 in "Q uantitative Scanning Electron Microscopy", edited byD. B. Holt, M. D. Muir, P. R. Grant and I. M. Boswarva, Academic Press, London, 1974. [10] Oroshnik, J., and Many, A ., Solid-State Electronics, 1, p.46,1960. [11] Baev, I. A., and Valyashko, E . c., "Study of the Homogeneity of Semiconductor Crystals with the Use of a Moving Light Probe", Soviet Phys.
Phenomena on Semiconductor Devices by a Light Spot Scanning Method", Solid-State Electron, 10, p.235-239,1967. [13] Wendell, K., and Taylor, R., " Rapid Evaluation of Proce ssing Geometries by the Examination of Cleaved Samples in the SEM". Proc. Advanced Techniques in Failure Analysis Symposium, September 1977. [14] Child, M. R., Ranasinghe, D . W., and White, D., "Applications of the Scanning Electron Microscope in the Development of Microtechnology". Ibid . [15] O'Hara, S., Hutchinson, P. W., Davis, R., and Dobson, P. S., "Defect-Induced Degradation in HighRadiance Lamps", Proc. Sixth International Symposium on Gallium Arsenide and Related Compounds, Edinburgh Conference, p.379-387, September 1976. [16] Stirland, D. J., "The AB Etch: A Reappraisal", ibid, p.150-157. [17] Galloway, K. F., Leedy, K. 0., and Keery, W. J., "Electron-Beam-Induced Currents in Simple Device Structures", IEEE Trans. PHP-12, p.231-236, September 1976.
First presented at the A TFA - 79 Symposium in Los Angeles, California, USA.
25