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Asymmetrically doped stacked channel strained SOI FinFET
Superlattices and Microstructures 102 (2017) 74e78
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Asymmetrically doped stacked channel strained SOI FinFET Shashank Dubey*, Pravin N. Kondekar Discipline of Electronics and Communication Engineering, PDPM-Indian Institute of Information Technology, Design & Manufacturing, Jabalpur, MP, 482005 India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 15 November 2016 Received in revised form 13 December 2016 Accepted 16 December 2016 Available online 19 December 2016
Strained SOI (SSOI) n-channel trigate FinFET is designed with asymmetrically doped stacked channels along the fin height. The OFF current is reduced with respect to lightly doped uniform SSOI FinFET because of band gap modification, originated between highly doped uniaxial strained and lightly doped Si fin. Through TCAD simulation it is observed that for the stacked devices the OFF current is reduced by more than 47%. The performances are also compared with highly doped uniform SSOI FinFETs and the results indicated that these devices have lesser random dopant variation at a moderate cost of ON and OFF current. © 2016 Elsevier Ltd. All rights reserved.
Keywords: Asymmetric doping SSOI Threshold voltage OFF current Stack
1. Introduction FinFETs are proved as a leading successor of conventional planar CMOS for nanoscale regime having better short channel effects and excellent electrostatic control [1]. Tri gate FinFETs on fully depleted SOI (FDSOI), further improves the characteristics in terms of lesser variability, better channel controlling [2]. However, for sub 25 nm technology node due to reduced dimensions problem like lower driving and higher leakage are dominating. For higher ON current the mobility enhancement techniques are the key technology now a day [1,3e6]. Demonstration of strained silicon on insulator (SSOI) for n-channel FinFETs have been shown improvement in electron mobility and driving current in <110> channel direction, by many authors [3e6]. Furthermore, there is still a need to improve the short channel effects (SCEs) of the devices. One of the possible solutions of is through increased channel doping [2] but at the cost of random dopant fluctuations and higher channel resistance. Another, way to improve the driving current and the channel electrostatics is using stacked channels. Stacking of Si and SiGe fins improves the device performance by introduction of valance band offset for the p-FinFETs [7,8]. In this paper, we introduce a technique to reduce the OFF current of SSOI n-channel FinFET using stacking of asymmetrically doped channels. A lightly doped (Nch1 ¼ 1 1015 cm3) relaxed Si channel is stacked on heavy doped (Nch1 ¼ 1 1018 cm3) uniaxial tensile strained SOI (Si/SSOI). The device performance is evaluated for variable thickness of heavy doped strained fin. We also compare the device characteristics with uniform SSOI FinFET having channel doping of 1 1015 and 1 1018 cm3. All the analysis is done using TCAD simulation setup.
* Corresponding author. E-mail addresses: [email protected] (S. Dubey), [email protected] (P.N. Kondekar). http://dx.doi.org/10.1016/j.spmi.2016.12.029 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
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Fig. 1. (a) 3D structure of SSOI FinFET used in the simulation. (b) Corresponding strained SOI (SSOI) fin cross section along X-X0 at the middle of fin.
2. Simulation methodology 3D process and device simulation of Sentaurus TCAD suit is used for design and analysis of SSOI FinFETs [9,10]. At the starting of simulation a uniform tensile stress of 1.3 GPa [5] is consider for n-channel SSOI FinFETs. All the FinFETs have (100) Si substrate and the channel direction is <110>. The fabrication steps for designing of uniform channel SSOI has been followed form [5] and having two devices with channel doping of 1 1015 and 1 1018 cm3. However, for asymmetrically channel devices initially a highly doped (1 1018 cm3) strained layer with thickness equal to fin height is deposited over BOX. The SSOI layer with thickness equal to Hfin-TS is etched away using SOI thinning for the deposition of lightly doped (1 1015 cm3) Si layer. Afterward, a Si layer is epitaxially grown on the top of SSOI layer having in-situ doping of Boron. Fin patterning is completed through etching the Si and SSOI layers to get fin top and bottom width of 6 and 12 nm, respectively. Triangular fins have advantage of lower off current as discussed in Ref. [11], and the etching process for such type of fins are well defined in Ref. [12] using reactive ion etching. After rounding the fin corners using Oxinitride mask, the gate oxide are formed with oxide deposition of interfacial SiO2 and HfO2 layers, with thickness such that the effective oxide thickness (EOT) is 0.85 nm. Than a dummy poly gate, for gate last flow [13] and spacer of length 8 nm is deposited. The source/drain (S/D) of Si are selective epitaxially grown over the etched area after spacer formation. For work function adjustment the metal gate of TiN is deposited by process of poly gate removal and deposition. The final device structure and fin topologies are shown in Fig. 1 and the dimensions are given in Table 1. First the device simulation models are calibrated for uniform SSOI FinFET (Nch ¼ 1 1015 cm3). Further these models are incorporated for the analysis of all the devices. The drift diffusion model with quantum correction (QC) and density gradient, is properly calibrated using velocity saturation to get the get the ON current of [5] (1.1 mA/mm @ 100 nA/mm). Masetti and Canali mobility model are used to consider impurity scattering and high filed saturation. Lombardi high-K model is used to capture the mobility degradation at the interface. The stress effects are taken into account using band gap deformation, density of states and k.p band models. 3. Results and discussion Uniaxial tensile and compressive strain affect the band gap of the channel. While compressive strain is responsible for change hole valley in valence band, tensile strain is caused offset in D2 and D4 valleys of conduction band [14]. As shown in Table 1 Device parameters for Si/SSOI FinFET. Parameter Fin height (nm) Top Fin width (nm) Bottom Fin width (nm) Fin pitch (nm) Spacer (nm) Gate length (nm) SSOI Fin thickness (nm) Eq. oxide thickness (nm) Supply Voltage (V)
Values Hfin Wtop Wbot FP Lsp Lg TS EOT VDD
30 6 12 48 8 20 5 to 25 0.85 0.8
76
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Fig. 2. (a) Conduction band variation along the channel height (X-X0 ) for various values of Ts. (b) Band gap modification along the channel height for different Ts.
Fig. 3. (a) Doping concentration for different highly doped SSOI region (TS) in Si/SSOI FinFETs along the fin height (X-X0 ). (b) Threshold voltage (VTH) variation as a function of TS. Inset: (a) Lightly and highly doped SSOI VTH. (b) % change in VTH for different TS with respect to lightly doped SSOI.
Fig. 4. ID Vs VGS in saturation region for all FinFETs. All the currents are normalize for Weff ¼ Wfin þ 2*Hfin.
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Fig. 5. (a) ON and OFF current variation as a function of TS for Si/SSOI. (b) Variation in ON and OFF current of Si/SSOI FinFET for different TS. The values are normalized for lightly doped and highly doped SSOI FinFETs.
Fig. 2 (a) as TS increased the conduction band offset shifted for and results in varying density of states along the channel height. The offset is introduced between the interface of highly doped tensile strain Si and lightly doped Si layer. Band gap modification along the fin height due to interfacing of sSi and Si is shown in Fig. 2 (b). Due to uniaxial tensile strain the band gap lowered at the boundary. As TS increased, higher doping region in the channel dominating and the outcome of that is stronger charge density [Fig. 3(a)]. For Si/SSOI devices threshold voltage (VTH) is increased due to highly doped channel (TS) region and band offset between the strained and relaxed layer. As illustrates in Fig. 3 (b), VTH for Si/SSOI have 14%e27% improvement with change in TS from 5 nm to 25 nm as compared to lightly doped SSOI. At a supply voltage of 0.8 V the lightly doped SSOI exhibits 147 mV VTH and as the channel doping increased the threshold voltage (VTH) increases by 27%. The orientation for electron transport for all the FinFETs is in <110> direction and the substrate is in (100) plane. As [4] shown that using strained Si on SOI the electron mobility is improved by ~40% with respect to conventional SOI for <110> channel direction. As shown in Fig. 4 the ON current (ION) for lightly doped uniform SSOI is 1.1 mA/mm at OFF current IOFF of 100 nA/mm. However, as the channel doping increased the driving current is degraded by 16% and OFF current improved by
Fig. 6. Scatter plots of VTH with correlation between lightly and highly doped SSOI and Si/SSOI with different SSOI heights. Inset: Statistical distribution of ION and log IOFF for random dopant variability source.
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62%. In case of Si/SSOI the driving current at TS ¼ 5 nm is 0.7 mA/mm @ 52 nA/mm. For higher values of TS ION became grater from 7% to 24% and IOFF lowered by 13%e27% [Fig. 5 (a)]. Fig. 5 (b) shown that driving current degradation in Si/SSOI is substantially higher with respect to lightly doped SSOI (36%e20% for TS ¼ 5e25 nm) as compared to highly doped SSOI (24%e 5% for TS ¼ 5e25 nm). Moreover, from the perspective of IOFF, it is improved by 1.89 e2.61 with respect to lightly doped SSOI. The difference in IOFF is significantly small between Si/SSOI and highly doped SSOI. Although SOI devices are less affected by variability sources like random dopant fluctuations (RDF) [2], but as the channel doping increases the probability of dopant randomization increases for smaller dimensions [15]. Here, we have compared VTH variation for Si/SSOI FinFET with increased value of TS. The statistical variability analysis on SSOI considered from Ref. [16], however the source is RDF in this simulation. Fig. 6 shows the variation in VTH for all devices with variable doping profile across the channel. It is observed that maximum standard deviation in VTH (sVTH) is for SSOI with Nch ¼ 1 1018 cm3. The RDF variability for Si/SSOI FinFETs is lowered with respect to highly doped SSOI for all the values of TS. The ION and IOFF variability are significantly improved with dominating value of TS in Si/SSOI. Increase in TS from 5 to 25 nm caused increment in sION and sIOFF by 23%e85% and 16%e62%, respectively. However, as compared to highly doped SSOI the variability is lowered up to TS ¼ 20 nm while approximately equal at TS ¼ 25 nm. 4. Conclusion Performances of asymmetrically doped SSOI (Si/SSOI) FinFETs have been compared with uniform SSOI channels with light and heavy doping. With the simulation analysis it is observed that with respect to lightly doped SSOI, Si/SSOI outperforms in terms of OFF current. The OFF current is reduced from 1.89 to 2.61 for varying height of SSOI layer. There is improvement in ON and OFF current with increasing height of strained channel. The comparative analysis is also carried out between highly doped SSOI and stack FinFETs. It is observed that with increased stack channel height the difference in OFF current is reduced from 39% to 1.5%. The variability in device performance is also dominating for highly doped uniform SSOI layer. From the forgoing analysis it can be concluded that the OFF current of SSOI FinFETs can be reduced by proper optimization in height of SSOI layer and channel doping at nominal cost of driving current. References [1] J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, R. Chau, Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering, in: 2006 Symposium on VLSI Technology, 2006, pp. 50e51. Digest of Technical Papers, 2006. [2] C.H. Lin, R. Kambhampati, R.J. Miller, T.B. Hook, A. Bryant, W. Haensch, P. Oldiges, I. Lauer, T. Yamashita, V. Basker, T. Standaert, K. Rim, E. Leobandung, H. Bu, M. Khare, Channel doping impact on FinFETs for 22nm and beyond, in: VLSI Technology (VLSIT), 2012, pp. 15e16. Symposium on, 2012. [3] A. Khakifirooz, R. Sreenivasan, B.N. Taber, F. Allibert, P. Hashemi, W. Chern, N. Xu, E.C. Wall, S. Mochizuki, J. Li, Y. Yin, N. Loubet, A. Reznicek, S.M. Mignot, D. Lu, H. He, T. Yamashita, P. Morin, G. Tsutsui, C.Y. Chen, V.S. Basker, T.E. Standaert, K. Cheng, T. Levin, B.Y. Nguyen, T.S.K. Liu, D. Guo, H. Bu, K. Rim, B. Doris, Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs, in: 2013 IEEE SOI-3D-subthreshold Microelectronics Technology Unified Conference (S3S), 2013, pp. 1e2. [4] N. Collaert, R. Rooyackers, F. Clemente, P. Zimmerman, I. Cayrefourcq, B. Ghyselen, K. San, B. Eyckens, M. Jurczak, S. Biesemans, Performance enhancement of MUGFET devices using super critical strained-SOI (SC-SSOI) and CESL, in: 2006 Symposium on VLSI Technology, 2006, pp. 52e53. Digest of Technical Papers, 2006. [5] K. Maitra, A. Khakifirooz, P. Kulkarni, V.S. Basker, J. Faltermeier, H. Jagannathan, H. Adhikari, C.C. Yeh, N.R. Klymko, K. Saenger, T. Standaert, R.J. Miller, B. Doris, V.K. Paruchuri, D. McHerron, J. O'Neil, E. Leobundung, H. Bu, Aggressively scaled strained-silicon-on-insulator undoped-body high-k metalgate nfinfets for high-performance logic applications, IEEE Electron Device Lett. 32 (6) (2011) 713e715. [6] W. Xiong, C.R. Cleavelin, P. Kohli, C. Huffman, T. Schulz, K. Schruefer, G. Gebara, K. Mathews, P. Patruno, Y.M.L. Vaillant, I. Cayrefourcq, M. Kennard, C. Mazure, K. Shin, T.J.K. Liu, Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility, IEEE Electron Device Lett. 27 (7) (2006) 612e614. [7] I. Ok, K. Akarvardar, S. Lin, M. Baykan, C.D. Young, P.Y. Hung, M.P. Rodgers, S. Bennett, H.O. Stamper, D.L. Franca, J. Yum, J.P. Nadeau, C. Hobbs, P. Kirsch, P. Majhi, R. Jammy, Strained SiGe and Si FinFETs for high performance logic with SiGe/Si stack on SOI, in: Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 34.2.1e34.2.4. [8] C. Hobbs, C. Smith, H. Adhikari, S. Lin, I. Ok, K. Akarvardar, S.-H. Lee, B. Coss, C. Young, M. Cruz, et al., High mobility SiGe channel nonplanar devices, ECS Trans. 28 (5) (2010) 137e142. [9] Sentaurus Device User Guide, Version I-2013.12, Synopsys Co., Mountain View, CA. [10] Sentaurus Process User Guide, Version I-2013.12, Synopsys Co., Mountain View, CA. [11] S. Dubey, P.N. Kondekar, Performance comparison of conventional and strained FinFET inverters, Microelectron. J. 55 (2016) 108e115. [12] N. Lindert, L. Chang, Y.-K. Choi, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor, C. Hu, Sub-60-nm quasi-planar FinFETs fabricated using a simplified process, Electron Device Lett. IEEE 22 (10) (2001) 487e489. [13] C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, et al., 45nm High-kþ metal gate strainenhanced transistors, in: 2008 Symposium on VLSI Technology, IEEE, 2008, pp. 128e129. [14] E. Ungersboeck, S. Dhar, G. Karlowatz, V. Sverdlov, H. Kosina, S. Selberherr, The effect of general strain on the band structure and electron mobility of silicon, IEEE Trans. Electron Devices 54 (9) (2007) 2183e2190. [15] X. Wang, A.R. Brown, B. Cheng, A. Asenov, Statistical variability and reliability in nanoscale FinFETs, in: Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 5.4.1e5.4.4. [16] S. Dubey, P.N. Kondekar, Fin shape dependent variability for strained SOI FinFETs, Microelectron. Eng. 162 (2016) 63e68.
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Asymmetrically doped stacked channel strained SOI FinFET Shashank Dubey*, Pravin N. Kondekar Discipline of Electronics and Communication Engineering, PDPM-Indian Institute of Information Technology, Design & Manufacturing, Jabalpur, MP, 482005 India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 15 November 2016 Received in revised form 13 December 2016 Accepted 16 December 2016 Available online 19 December 2016
Strained SOI (SSOI) n-channel trigate FinFET is designed with asymmetrically doped stacked channels along the fin height. The OFF current is reduced with respect to lightly doped uniform SSOI FinFET because of band gap modification, originated between highly doped uniaxial strained and lightly doped Si fin. Through TCAD simulation it is observed that for the stacked devices the OFF current is reduced by more than 47%. The performances are also compared with highly doped uniform SSOI FinFETs and the results indicated that these devices have lesser random dopant variation at a moderate cost of ON and OFF current. © 2016 Elsevier Ltd. All rights reserved.
Keywords: Asymmetric doping SSOI Threshold voltage OFF current Stack
1. Introduction FinFETs are proved as a leading successor of conventional planar CMOS for nanoscale regime having better short channel effects and excellent electrostatic control [1]. Tri gate FinFETs on fully depleted SOI (FDSOI), further improves the characteristics in terms of lesser variability, better channel controlling [2]. However, for sub 25 nm technology node due to reduced dimensions problem like lower driving and higher leakage are dominating. For higher ON current the mobility enhancement techniques are the key technology now a day [1,3e6]. Demonstration of strained silicon on insulator (SSOI) for n-channel FinFETs have been shown improvement in electron mobility and driving current in <110> channel direction, by many authors [3e6]. Furthermore, there is still a need to improve the short channel effects (SCEs) of the devices. One of the possible solutions of is through increased channel doping [2] but at the cost of random dopant fluctuations and higher channel resistance. Another, way to improve the driving current and the channel electrostatics is using stacked channels. Stacking of Si and SiGe fins improves the device performance by introduction of valance band offset for the p-FinFETs [7,8]. In this paper, we introduce a technique to reduce the OFF current of SSOI n-channel FinFET using stacking of asymmetrically doped channels. A lightly doped (Nch1 ¼ 1 1015 cm3) relaxed Si channel is stacked on heavy doped (Nch1 ¼ 1 1018 cm3) uniaxial tensile strained SOI (Si/SSOI). The device performance is evaluated for variable thickness of heavy doped strained fin. We also compare the device characteristics with uniform SSOI FinFET having channel doping of 1 1015 and 1 1018 cm3. All the analysis is done using TCAD simulation setup.
* Corresponding author. E-mail addresses: [email protected] (S. Dubey), [email protected] (P.N. Kondekar). http://dx.doi.org/10.1016/j.spmi.2016.12.029 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
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Fig. 1. (a) 3D structure of SSOI FinFET used in the simulation. (b) Corresponding strained SOI (SSOI) fin cross section along X-X0 at the middle of fin.
2. Simulation methodology 3D process and device simulation of Sentaurus TCAD suit is used for design and analysis of SSOI FinFETs [9,10]. At the starting of simulation a uniform tensile stress of 1.3 GPa [5] is consider for n-channel SSOI FinFETs. All the FinFETs have (100) Si substrate and the channel direction is <110>. The fabrication steps for designing of uniform channel SSOI has been followed form [5] and having two devices with channel doping of 1 1015 and 1 1018 cm3. However, for asymmetrically channel devices initially a highly doped (1 1018 cm3) strained layer with thickness equal to fin height is deposited over BOX. The SSOI layer with thickness equal to Hfin-TS is etched away using SOI thinning for the deposition of lightly doped (1 1015 cm3) Si layer. Afterward, a Si layer is epitaxially grown on the top of SSOI layer having in-situ doping of Boron. Fin patterning is completed through etching the Si and SSOI layers to get fin top and bottom width of 6 and 12 nm, respectively. Triangular fins have advantage of lower off current as discussed in Ref. [11], and the etching process for such type of fins are well defined in Ref. [12] using reactive ion etching. After rounding the fin corners using Oxinitride mask, the gate oxide are formed with oxide deposition of interfacial SiO2 and HfO2 layers, with thickness such that the effective oxide thickness (EOT) is 0.85 nm. Than a dummy poly gate, for gate last flow [13] and spacer of length 8 nm is deposited. The source/drain (S/D) of Si are selective epitaxially grown over the etched area after spacer formation. For work function adjustment the metal gate of TiN is deposited by process of poly gate removal and deposition. The final device structure and fin topologies are shown in Fig. 1 and the dimensions are given in Table 1. First the device simulation models are calibrated for uniform SSOI FinFET (Nch ¼ 1 1015 cm3). Further these models are incorporated for the analysis of all the devices. The drift diffusion model with quantum correction (QC) and density gradient, is properly calibrated using velocity saturation to get the get the ON current of [5] (1.1 mA/mm @ 100 nA/mm). Masetti and Canali mobility model are used to consider impurity scattering and high filed saturation. Lombardi high-K model is used to capture the mobility degradation at the interface. The stress effects are taken into account using band gap deformation, density of states and k.p band models. 3. Results and discussion Uniaxial tensile and compressive strain affect the band gap of the channel. While compressive strain is responsible for change hole valley in valence band, tensile strain is caused offset in D2 and D4 valleys of conduction band [14]. As shown in Table 1 Device parameters for Si/SSOI FinFET. Parameter Fin height (nm) Top Fin width (nm) Bottom Fin width (nm) Fin pitch (nm) Spacer (nm) Gate length (nm) SSOI Fin thickness (nm) Eq. oxide thickness (nm) Supply Voltage (V)
Values Hfin Wtop Wbot FP Lsp Lg TS EOT VDD
30 6 12 48 8 20 5 to 25 0.85 0.8
76
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Fig. 2. (a) Conduction band variation along the channel height (X-X0 ) for various values of Ts. (b) Band gap modification along the channel height for different Ts.
Fig. 3. (a) Doping concentration for different highly doped SSOI region (TS) in Si/SSOI FinFETs along the fin height (X-X0 ). (b) Threshold voltage (VTH) variation as a function of TS. Inset: (a) Lightly and highly doped SSOI VTH. (b) % change in VTH for different TS with respect to lightly doped SSOI.
Fig. 4. ID Vs VGS in saturation region for all FinFETs. All the currents are normalize for Weff ¼ Wfin þ 2*Hfin.
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Fig. 5. (a) ON and OFF current variation as a function of TS for Si/SSOI. (b) Variation in ON and OFF current of Si/SSOI FinFET for different TS. The values are normalized for lightly doped and highly doped SSOI FinFETs.
Fig. 2 (a) as TS increased the conduction band offset shifted for and results in varying density of states along the channel height. The offset is introduced between the interface of highly doped tensile strain Si and lightly doped Si layer. Band gap modification along the fin height due to interfacing of sSi and Si is shown in Fig. 2 (b). Due to uniaxial tensile strain the band gap lowered at the boundary. As TS increased, higher doping region in the channel dominating and the outcome of that is stronger charge density [Fig. 3(a)]. For Si/SSOI devices threshold voltage (VTH) is increased due to highly doped channel (TS) region and band offset between the strained and relaxed layer. As illustrates in Fig. 3 (b), VTH for Si/SSOI have 14%e27% improvement with change in TS from 5 nm to 25 nm as compared to lightly doped SSOI. At a supply voltage of 0.8 V the lightly doped SSOI exhibits 147 mV VTH and as the channel doping increased the threshold voltage (VTH) increases by 27%. The orientation for electron transport for all the FinFETs is in <110> direction and the substrate is in (100) plane. As [4] shown that using strained Si on SOI the electron mobility is improved by ~40% with respect to conventional SOI for <110> channel direction. As shown in Fig. 4 the ON current (ION) for lightly doped uniform SSOI is 1.1 mA/mm at OFF current IOFF of 100 nA/mm. However, as the channel doping increased the driving current is degraded by 16% and OFF current improved by
Fig. 6. Scatter plots of VTH with correlation between lightly and highly doped SSOI and Si/SSOI with different SSOI heights. Inset: Statistical distribution of ION and log IOFF for random dopant variability source.
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62%. In case of Si/SSOI the driving current at TS ¼ 5 nm is 0.7 mA/mm @ 52 nA/mm. For higher values of TS ION became grater from 7% to 24% and IOFF lowered by 13%e27% [Fig. 5 (a)]. Fig. 5 (b) shown that driving current degradation in Si/SSOI is substantially higher with respect to lightly doped SSOI (36%e20% for TS ¼ 5e25 nm) as compared to highly doped SSOI (24%e 5% for TS ¼ 5e25 nm). Moreover, from the perspective of IOFF, it is improved by 1.89 e2.61 with respect to lightly doped SSOI. The difference in IOFF is significantly small between Si/SSOI and highly doped SSOI. Although SOI devices are less affected by variability sources like random dopant fluctuations (RDF) [2], but as the channel doping increases the probability of dopant randomization increases for smaller dimensions [15]. Here, we have compared VTH variation for Si/SSOI FinFET with increased value of TS. The statistical variability analysis on SSOI considered from Ref. [16], however the source is RDF in this simulation. Fig. 6 shows the variation in VTH for all devices with variable doping profile across the channel. It is observed that maximum standard deviation in VTH (sVTH) is for SSOI with Nch ¼ 1 1018 cm3. The RDF variability for Si/SSOI FinFETs is lowered with respect to highly doped SSOI for all the values of TS. The ION and IOFF variability are significantly improved with dominating value of TS in Si/SSOI. Increase in TS from 5 to 25 nm caused increment in sION and sIOFF by 23%e85% and 16%e62%, respectively. However, as compared to highly doped SSOI the variability is lowered up to TS ¼ 20 nm while approximately equal at TS ¼ 25 nm. 4. Conclusion Performances of asymmetrically doped SSOI (Si/SSOI) FinFETs have been compared with uniform SSOI channels with light and heavy doping. With the simulation analysis it is observed that with respect to lightly doped SSOI, Si/SSOI outperforms in terms of OFF current. The OFF current is reduced from 1.89 to 2.61 for varying height of SSOI layer. There is improvement in ON and OFF current with increasing height of strained channel. The comparative analysis is also carried out between highly doped SSOI and stack FinFETs. It is observed that with increased stack channel height the difference in OFF current is reduced from 39% to 1.5%. The variability in device performance is also dominating for highly doped uniform SSOI layer. From the forgoing analysis it can be concluded that the OFF current of SSOI FinFETs can be reduced by proper optimization in height of SSOI layer and channel doping at nominal cost of driving current. References [1] J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, R. Chau, Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering, in: 2006 Symposium on VLSI Technology, 2006, pp. 50e51. Digest of Technical Papers, 2006. [2] C.H. Lin, R. Kambhampati, R.J. Miller, T.B. Hook, A. Bryant, W. Haensch, P. Oldiges, I. Lauer, T. Yamashita, V. Basker, T. Standaert, K. Rim, E. Leobandung, H. Bu, M. Khare, Channel doping impact on FinFETs for 22nm and beyond, in: VLSI Technology (VLSIT), 2012, pp. 15e16. Symposium on, 2012. [3] A. Khakifirooz, R. Sreenivasan, B.N. Taber, F. Allibert, P. Hashemi, W. Chern, N. Xu, E.C. Wall, S. Mochizuki, J. Li, Y. Yin, N. Loubet, A. Reznicek, S.M. Mignot, D. Lu, H. He, T. Yamashita, P. Morin, G. Tsutsui, C.Y. Chen, V.S. Basker, T.E. Standaert, K. Cheng, T. Levin, B.Y. Nguyen, T.S.K. Liu, D. Guo, H. Bu, K. Rim, B. Doris, Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs, in: 2013 IEEE SOI-3D-subthreshold Microelectronics Technology Unified Conference (S3S), 2013, pp. 1e2. [4] N. Collaert, R. Rooyackers, F. Clemente, P. Zimmerman, I. Cayrefourcq, B. Ghyselen, K. San, B. Eyckens, M. Jurczak, S. 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