Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET

Microelectronics Journal 62 (2017) 30–37

Contents lists available at ScienceDirect

Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET

MARK

⁎

Azzedin Es-Sakhi , Masud Chowdhury Computer Science and Electrical Engineering, University of Missouri-Kansas City, Kansas City, MO 64110, USA

A R T I C L E I N F O

A B S T R A C T

Keywords: Silicon-on-insulator (SOI) technology Sub-threshold swing Ultra-low-power circuit SOI-FinFET and Bulk FinFET

This paper presents a study of the structure and the characteristics of the emerging device - SOI-FinFET. Close form models are developed to estimate the values of the device capacitances. Using these capacitance models, an expression for subthreshold swing of the SOI-FinFET is derived. These models have been used to investigate the behavior of SOI-FinFET in the subthreshold region, the I-V characteristics, and the drain induced barrier lowering (DIBL). These approximations are based on the structure and the internal capacitive coupling of SOIFinFET. The effects of doping attenuation in the channel, charge trapping in the insulator, and some other factors are not taken into consideration, because the focus of this paper is to investigate the impact of the geometric dimensions and related factors on the behavior and the operation of SOI-FinFET. The channel of SOI-FinFET is either undoped or lightly doped. In addition to analyzing the impact of various geometric parameters on the behavior of the device, the developed models and the presented analysis would be of great importance for future CAD tool development and design automation. It is observed that by optimizing these dimensional factors, a subthreshold swing (S) value very close to 60 mV/decade can be achieved for SOI-FinFET.

1. Introduction Over the last several decades, making the MOSFET channel length shorter has been the key to improve performance and power efficiency. However, aggressive scaling has led to severe short-channel-effects (SCEs) that include a significant increase of the off-state current and standby power. In addition, the scaling of the channel length leads to inferior control of the gate over the channel behavior. One way to improve gate control is to add a second gate to aid the existing gate and/or placing the device on an insulator so that the body can act as a bottom gate. Both options have demonstrated better performance in the scaled down conventional MOSFET devices. Merging SOI structure and device channel scaling of the MOSFETs has enhanced the speed of the device in addition to on-state current. SOI reduces the capacitance at the source and the drain junctions significantly by excluding the depletion regions extending into the substrate. SOI substrate leads to a dielectric isolation of the devices to lower the influence of the parasitic effects experienced in bulk devices. Majumdar et al. indicated that using back-gated, extremely thin silicon-on-insulator (ETSOI) device with thin buried oxide (BOX) will also lower the threshold voltage and allows for lower voltage operation [1]. Mahabadi proposed a new structure of LDMOSFET called upper drift region double step partial silicon on insulator (UDDS-PSOI) to adjust the electric field near

⁎

the drain and hence to boost the breakdown voltage (BV) [2]. Imani et al. improved the static and dynamic power in new FinFET based SRAM architecture. Exploiting FinFET technology back-gate basing to increase SRAM efficiently, reliability and stability, and to improve write/read operation [3]. Saremi and co-authors studied three SOI structures from which they concluded that the ground plane in the substrate (SOI-GPS) structure was more resistant against the process variations in comparison to SOI with ground plane in buried oxide (SOIGPB) and SOI without ground plane (SOI-WGP) [4]. The ground plane technique is also proposed in FinFET structure in [5] to reduce the drain-induced barrier lowering (DIBL). GP-FinFET increases the Ion / Ioff ratio and reduces the subthreshold-swing. 3D FET devices are being explored to extend Moore's Law and reduce the power consumption compared to planar MOSFET. To predict the transfer characteristics of the CMOS devices, a charge-based compact model for TG FinFETs was proposed by Fasarakis et al. [6]. Likewise, multi-gate FET compact model was developed by Dunga et al. based on surface-potential. This model includes the effect of finite body doping on the electrical behavior of multi-gate structure. The proposed model permits to analyze the short channel effects of the device [7]. Modeling and evaluation of the extrinsic and intrinsic capacitance components in different CMOS devices is presented in Ref. [8]. In Ref. [9], a model to describe the characteristics of a four-gate transistor (G4-

Corresponding author. E-mail addresses: [email protected] (A. Es-Sakhi), [email protected], [email protected] (M. Chowdhury).

http://dx.doi.org/10.1016/j.mejo.2017.02.005 Received 17 February 2016; Received in revised form 7 January 2017; Accepted 11 February 2017 0026-2692/ © 2017 Elsevier Ltd. All rights reserved.

Microelectronics Journal 62 (2017) 30–37

A. Es-Sakhi, M. Chowdhury

Fig. 1. FinFET illustrations: a) 3D schematic view of SOI-FinFET, b) horizontal cross-section along transistor gate, and c) vertical cross-section along transistor gate. Hfin and Wfin represent Fin height and width, respectively, L is the gate length, and tox is gate oxide thickness.

In this paper, we focus on the analysis of the internal device structure and the relevant capacitances inside SOI-FinFET. Based on this analysis, we developed a close form expression for the subthreshold swing of SOI-FinFET. The subthreshold behavior of the SOI-FinFET appears to be very suitable for ultra-low-power circuit designs. The rest of this paper is organized as follows. Section 2 presents an analytical approach to estimate the internal device capacitances and subthreshold swing of SOI-FinFET. Section 3 presents the simulation results and analysis based on intrinsic capacitance modeling. In Section 4, we investigate the current-voltage (I-V) characteristics and drain induced barrier lowering (DIBL) in SOI-FinFET. Finally, Section 5 concludes the paper.

FET) was presented in order to perform circuit simulations on this structure based circuit. G4-FET, known as gate-all-around FET, are still in the early research stages. Whereas, FinFET was introduced due to lesser process complexity and its compatibility with the CMOS fabrication process flow. The fin shape leads to a gate structure that surrounds the channel from three sides [10]. This structure offers a better control over the short-channel-effect. Therefore, the effective switching capacitance, as well as the dynamic power dissipation, can be reduced [11]. The Tri-gate/FinFET structure improves the gate electrostatic control over the channel, leading to a higher performance. Consequently, this new device has emerged as a promising alternative to the conventional MOSFET due to its future scalability to continue Moore's Law and compatibility with the existing silicon fabrication process. A cross-sectional view of the SOI-FinFET's internal structure is shown in Fig. 1(b and c). In this device, the gate is fabricated and the source and drain are implants. Since the channel is undoped, the device does not experience coulomb scattering due to impurities and excessive random dopant fluctuations (RDF). As a result, the mobility of the charge carriers in FinFET is higher in comparison to the planar MOSFET [12,13]. The ON/OFF states of FinFET are controlled by this surrounding gate leading to a higher Ion / Ioff ratio compared to MOSFET. Designs with an undoped or lightly doped channel report a high Ion / Ioff ratio [14] and a lower subthreshold swing (S). However, these types of designs require different gate material to fully control the channel [15– 17]. An undoped or lightly doped channel is also accredited due to the concern of significant device-to-device threshold voltage variations. FinFET geometry ensures a much higher gate capacitance for the same oxide thickness compared to the planar MOSFET [18]. SOI-FinFET has several advantages: (i) it operates with a lower supply voltage and its threshold voltage is less sensitive to gate length that makes it suitable for low standby power (LSTP) applications [19], (ii) it provides higher Ion and lower Ioff , (iii) its subthreshold swing is lower, and (iv) its SCEs and leakage levels are lower than those of the bulk FinFET [20]. The gate geometry plays a key role in controlling the performance of the FinFETs. The ‘Fin width’ (Wfin ), as shown in Fig. 1, has a major impact on the performance of the device. Smaller Wfin is required for better gate control over the channel. Smaller Wfin also leads to a smaller subthreshold swing (steeper subthreshold slope) and lower draininduced-barrier-lowering (DIBL) [21]. In Ref. [22], various Fin aspect ratios (AR = Fin-height/Fin-width) have been studied, since this geometric ratio has a significant effect on the controllability of the channel, short-channel-effects (SCE), on-state current (Ion ), and buriedinsulator-induced barrier lowering (BIIBL). DIBL and S would increase if AR goes below 1.5 [23]. The vertical architecture of FinFET makes it very compact compared to the conventional MOSFET. However, design reality dictates that fin-width should be around half the channel length. Therefore, maintaining an optimum AR presents a significant challenge for process control and design flexibility [23,24].

2. Internal device parameters and the subthreshold behavior of SOI-FinFET 2.1. Significance of subthreshold swing in device operation The parameter that determines the Ion / Ioff current ratio and the transition from the ON to OFF state of a transistor is called the subthreshold swing (S), which is the inverse of the slope of the voltage-current characteristics, in the subthreshold region. This critical parameter defines the behavior of the transistor in the subthreshold region. S indicates the amount of change in VGS needed to change the current ID by one decade. In other words, S is the amount of change in VGS required to produce a 10×change in ID . A smaller value of S indicates that the device can be turned ON/OFF faster. The subthreshold swing (S) for a planar MOSFET is defined as in (1) and (2).

S=

dVg d (logID )

= ln(10).

dVg dψS . . ID dψS dID

(1) (2)

S = ln(10)η.kT / q Here

dψS dID

× ID = kT / q and

∂VG ∂ψs

is called the body factor and is denoted by

η . VG is the gate voltage, ID is the drain current, and ψs is the surface potential. VG is related to ψS by a capacitive voltage divider and ‘S′ could be expressed as in (3). S = ln(10)

KT ⎛ Cdep ⎞ ⎜1+ ⎟ q ⎝ Cox ⎠

Where Cdep is the depletion region capacitance and Cox = oxide capacitance per unit area.

(3) εox tox

is the gate

2.2. The internal capacitance of SOI-FinFET We first analyzed the internal device capacitances of SOI-FinFET and then we presented a step-by-step analytical approach to model and 31

Microelectronics Journal 62 (2017) 30–37

A. Es-Sakhi, M. Chowdhury

2Wfin

Cox−fb = εox t

BOX

⎛ ln⎜1 + ⎝

Fig. 2. Illustration of how to calculate capacitance in between two parallel conducting plates. Here 2 h is the distance between the two plates; W, L and t are the width, length, and thickness of the top plate, respectively.

⎡ ⎛ ⎞⎤ w ⎢ 2h ⎛ πw ⎞ 2h ⎜ 2t t t2 1+ ln⎜ ln⎜1+ + 2 + 2 ⎟⎟⎥ ⎟+ h ⎢⎣ πw ⎝ h ⎠ πw ⎝ h h h ⎠⎥⎦

Cgf−vl = εox

Cgf−top = εox

⎡

2Wfin L⎢1 t ox

⎛ ln⎜1 + ⎝

⎣

+

⎛ 2πW ⎞ t ox ln⎜ fin ⎟ πWfin ⎝ t ox ⎠

4(Hfin − t ox) t ox

+2

2Hfin t ox

+ +

⎞⎤ ⎟⎥ ⎟⎥ ⎠⎦

t ox 2

⎞⎤ ⎟⎥ ⎠⎥⎦

2Hfin tBOX

+

4Hfin 2 tBOX 2

⎞⎤ ⎟⎥ ⎠⎥⎦

(7)

(9)

Cox−fb × CSi (Cgf−top + 2 × Cgf−vr ) × (Cox−fb + CSi +2Cox−gb) + 2 × Cox−fb ×Cox−gb

Cox−fb × CSi Cgf × (Cox + CSi) + Cox−fb (Cox −Cox−fb)

WFinHFinμn LgateVT

DIBL =

qni exp((Vgs − Vfb )/ nVT )[1−exp(−Vds / VT )]

Vth(VDS = 0. 5) − Vth(VDS = 25mV ) VDS (=0. 5V ) − VDS (=25mV )

(10)

(11)

(12)

(13)

The gate geometry of SOI-FinFET and the corresponding internal capacitances are illustrated in Fig. 3a. Since the ‘Fin’ is surrounded by the gate from three sides, there will be three capacitive components between the gate and the device channel (Fin). These are Cgf − top, Cgf − vl , and Cgf − vr that represent the capacitances of the top, vertical-left, and vertical-right plates of the gate respectively formed with the ‘Fin’ (see Fig. 3b for details). The fin will also form a capacitance (Cox − fb ) with the body (bulk) of the device. These four components of the ‘Fin’ capacitances can be approximated by using Yang's formula as in Eq. (4). For uniformly dispersed gate-shape, the two capacitances Cgf − vl and Cgf − vr are assumed to be equal. The formation of the four components of the fin (channel) capacitance of SOI-FinFET is illustrated in Fig. 3b. Each of these components can be calculated by the model presented in Eq. (4). Eqs. (5), (6), and (7) present the models for Cgf − vl,(Cgf − vr ), Cgf − top, and Cox − fb derived using Yang's formula (4). The total gate-fin (channel) capacitance (Cgf ) of the SOI-FinFET is given in Eq. (8), where the components can be calculated by the developed models (5) and (6). Model (7) gives the capacitance between the fin and the body across the buried oxide. In addition to this capacitance Cox − fb , there will be two more capacitances (Cox − gb ) between the two narrow edges of the gate and the body (bulk) on the two sides of the device. The total capacitance (Cox ) across the buried insulating oxide (BOX) can be given by Eq. (9). This represents the total capacitance formed in between the working area of the device and the silicon substrate. The capacitance Cox − gb is the oxide film capacitance, which can be approxi-

(4)

(5)

t ox πWfin 4Hfin 2

+2

tBOX πWfin

Cox = 2Cox−gb + Cox−fb

Ids =

⎛ 2πH fin ⎞ t t 2H fin ⎡ L ⎢1 + ox ln⎜ ⎟ + ox πH fin t ox ⎢⎣ πH fin ⎝ t ox ⎠

⎛ 4Wfin 2 2Wfin 2Wfin + +2 ln⎜⎜1 + t t t ox 2 ox ox ⎝

4(Hfin − t ox) tBOX

+

(8)

η=1+

2.3. Modeling of SOI-FinFET capacitances

C=ε

tBOX ⎛ 2πWfin ⎞ ln⎜ ⎟ πWSi ⎝ tBOX ⎠

Cgf = Cgf−top + Cgf−vl + Cgf−vr

η=1+

estimate the subthreshold swing of SOI-FinFET. The approximation is based on the coupling capacitance of the device. Doping attenuation of the channel is not considered because the channel is undoped or very lightly doped in this capacitance approximation of SOI-FinFET [17]. In this approach, we did not consider charge trapping inside the insulator and a few other factors, because our focus is to investigate the impact of geometric and structural factors. The capacitance model shown in Eq. (4) is based on Fig. 2, which provides a pictorial view of how each individual component of fin capacitance is established. The model expresses the capacitance per unit length. The capacitance between two electrical conducting plates (as shown in Fig. 2) will have parallel plate components as well as fringing capacitances. Therefore, the models derived from (4) [25–27] include all the relevant electrostatic effects as well as the fringing fields between the gate and the fin.

⎡ L⎢1 + ⎣

(6)

Fig. 3. (a) SOI-FinFET cross section and internal capacitances.Hfin is the fin height, Wfin is the channel width, tBOX is the buried oxide thickness, L is the channel length, and tox is the gate channel insulator thickness; ( b) Formation of the components of the total capacitance of the fin (channel) of SOI-FinFET. Here Cgf − vl = Cgf − vr .

32

Microelectronics Journal 62 (2017) 30–37

A. Es-Sakhi, M. Chowdhury

Fig. 4. a) SOI-FinFET internal capacitive network model and b) a simplified equivalent model of the capacitive network.

⎛ ε ⎞ mated by the parallel plate assumption ⎜Cox − gb = t ox ⎟, where εox is the BOX ⎠ ⎝ permittivity and tBOX is the buried oxide thickness. The silicon film capacitance (CSi ) can be estimated by parallel plate assumption ⎛ ε ⎞ ⎜CSi = tSi ⎟, where εSi is the permittivity and tSi is the bulk silicon Si ⎠ ⎝ thickness. 2.4. Subthreshold Swing Approximation of the SOI-FinFET The subthreshold swing of the device is approximated based on the device's internal capacitances derived in the previous subsection. Fig. 4(a) and (b) illustrate the internal capacitive network of the SOIFinFET device and the simplified capacitive network model of the device. In deriving the short-channel model for the subthreshold swing of the SOI-FinFET, we considered voltage doping transformation (VDT) as in Refs. [28,29] and linearly varying potential (LVP) approximation as in Refs. [30,31]. The derived model for the body-factor (η ) of the SOI-FinFET is given in Eq. (10). For brevity, the detail steps of deriving the model for the body factor are shown in the appendix. The model presented in Eq. (10) can be simplified as in Eq. (11) by the replacements using Eqs. (8) and (9). Therefore, the body factor (η ) of the SOI-FinFET can be estimated by either (10) or (11). Now, replacing η in Eq. (2) by the expression (10) or (11), the subthreshold swing of SOI-FinFET can be calculated. Due to the unique arrangement and the relative dimensions of the internal components of SOI-FinFET, the device offers near-ideal coupling that ensures a value of η close to unity. However, the subthreshold swing depends on several parameters such as buried oxide thickness (tBOX ), channel dimensions (fin height, fin width and channel length), gate oxide thickness (tox ) and the silicon bulk thickness (tsi ). To the best of our knowledge, the presented models of the body factor and the subthreshold swing in this paper are the first comprehensive approaches to characterize the subthreshold behavior of SOI-FinFET correctly and efficiently.

Fig. 5. a) Variation of subthreshold swing with the thicknesses of the substrate (tsi ) and buried oxide film (tBOX ). Hfin = 14nm , Wfin = 7nm , tox = 1nm , L = 14nm b) Subthreshold swing for various values of fin height and fin width.

3. Simulation and analysis

tion through the BOX. A thinner BOX also lowers the depletion layer that reduces the parasitic capacitance, leading to higher speed and lower power consumption. However, a thinner BOX will increase the parasitic coupling capacitance with the substrate [32]. Fig. 5a shows the dependence of the subthreshold swing (S) on the thickness of the substrate (tsi ) and the buried oxide film (tBOX ). It illustrates how a desired value of S can be achieved by selecting suitable values of tsi , tBOX , and/or the ratio tsi / tBOX . The results show that the values of S can be significantly improved by increasing ratio tsi / tBOX . Therefore, SOIFinFET on a thin BOX and thicker substrate gives a better subthreshold swing. Fig. 5b shows the dependency of the subthreshold swing on the geometrical parameters: fin-width and fin-height. We observed that the

From the derived models of the internal capacitances and the body factor, the subthreshold behavior and subthreshold swing of SOIFinFET can be examined. The analysis of this section provides a clear picture of how to optimize SOI-FinFET characteristics of a certain design goal by selecting appropriate geometric dimensions. Through the proposed modeling and analysis, various structural factors to evaluate and improve the subthreshold swing of SOI-FinFET have been identified. We observed the variation of the intrinsic capacitances and subthreshold swing for different aspect ratios, substrate thickness, and buried oxide BOX (Fig. 5). The thickness of the buried oxide provides a tradeoff between the thermal and the electrical properties of the device. A thinner BOX helps better heat dissipation and electric field penetra33

Microelectronics Journal 62 (2017) 30–37

A. Es-Sakhi, M. Chowdhury

smaller width and larger height of the fin give a reduced value of subthreshold swing leading to a better performance in the subthreshold region. It is important to note that the fin aspect ratio (AR = Finheight/Fin-width) is a very critical performance parameter. Therefore, neither the width nor the height should be changed independently. This geometric ratio has a significant effect on the controllability of the channel, short-channel-effects (SCE), on-current (Ion ), buried-insulatorinduced barrier lowering (BIIBL), drain induced barrier lowering (DIBL), and other correlated parameters. Therefore, it would be more relevant to observe the behavior of the SOI-FinFET for different fin aspect ratios. It is clear that the aspect ratio Hfin / Wfin must be much larger to reduce the subthreshold swing. However, technology scaling, fabrication process and variation may restrict the use of such a large ratio. This provides a way to select a reasonable AR to obtain a lower value of S. The subthreshold swing of ~67mV / decade has been evaluated for Hfin = 90nm , Wfin = 10nm , tSi = 70nm , tBOX = 60nm , tox = 1nm , and L = 14nm .

(a)

4. ID vs. VGS Characteristic SOI-FinFET design requires a dimension analysis to limit shortchannel-effects by controlling the subthreshold slope and the draininduced barrier lowering (DIBL). This can be achieved by selecting a proper range of the aspect ratio ,Hfin / Wfin . In this section, we investigated the (I-V) characteristics and the DIBL of the SOI-FinFET in the subthreshold region. The drain current of the SOI-FinFET at the subthreshold region is dominated by a diffusion current. This region illustrates how fast the device switches ON and OFF. For low power applications, leakage has to be well managed. The drain current for fully depleted SOI-FinFET at the subthreshold region is given by (12) [26]. Where VT = kT / q , μn is electronic mobility, ni is the intrinsic carrier concentration, Vds is the drain-to-source applied voltage, and Vgsr = Vgsl = Vgs is the gate voltage (same voltage applied to both left r l = V fb = Vfb = and right gates). V fb

∅m −(χ +

Eg + ∅b ) 2

q

−

KBT ⎛ NC ⎞ ln⎜ N ⎟ 2q ⎝ V⎠

(b)

is the flat-

band voltage (both left and right are equal due to the symmetry of the device). χ is the electron affinity. Here ∅m is the potential difference between the Fermi level of the intrinsic silicon and the p-type silicon and is given by ∅m = VT ln(NA / ni ). Eg is the silicon band-gap at room temperature (300 K), and q is the elementary charge. Fig. 6 presents the (I-V) characteristic of the SOI-FinFET for different aspect ratios ( AR = Hfin / Wfin ). It is shown that the leakage current decreases as AR increases. This provides a way to select a reasonable AR to obtain a lower value of S and low leakage. We also studied the impact of the SOI-FinFET aspect ratio (Hfin / Wfin ) on the Drain Induced Barrier Lowering (DIBL). The DIBL is defined as

Fig.

6. Id − Vgs

characteristic

of

SOI-FinFET

device,

L = 14 , Wfin = 7nm

Fig. 7. a) I-V characteristics of SOI-FinFET showing the effect of the drain-source voltage VDS , b) DIBL dependency on the aspect ratio Hfin /Wfin.

the difference in the threshold voltage extracted at VDS = 25mV and VDS = 0. 5V and normalized by this difference of drain voltage. DIBL is calculated using (13), where Vth is the threshold voltage for each geometric aspect ratio. Fig. 7.a shows DIBL of ~ 64mV / V at AR~1.5. This value can be reduced by increasing the aspect ratio (AR). From Fig. 7.b, it is observed that by lowering AR, the DIBL effect can be reduced. Engineering the structure of the SOI-FinFET by optimizing the finheight, fin-thickness, oxide thickness, and channel length is a key factor to increase the on-current and to reduce the leakage current. This can be achieved by having superior electrostatic and excellent control over the channel. Our results indicate that the aspect ratio Hfin / Wfin can be modified for high–performance and ultra-low-power subthreshold applications. For an aspect ratio greater than 2 ( AR > 2 ), the transistor effective area increases, and therefore, the driving capability enhances due to superior electrostatic integrity and a large vertical channel. This capacitance and geometrical analysis demonstrate that increasing the aspect ratio Hfin / Wfin from 2 to 3 can improve device conductivity levels and lower DIBL giving an excellent subthreshold performance. This corresponds to a wide channel closer to the vertical gates improving the electrostatic of the device. Therefore, a high aspect ratio will give a lower DIBL and lower subthreshold swing. Hence, a device with FinFET structure (AR > 2) exhibits better characteristics owing to more uniform potential distribution inside the channel. The concept of tall and narrow fins has been proven in several publications [33,34]. These conclusions also agree with A. Kranti et al. in Ref. [35] and J.-P. Colinge in [36] that tall fins reduce short-channel-

and

Hfin = 10. 5nm−28nm at Vds = 0. 7V .

34

Microelectronics Journal 62 (2017) 30–37

A. Es-Sakhi, M. Chowdhury

analytical model to approximate the subthreshold swing based on the capacitive coupling model in the subthreshold regime. We have also demonstrated the impact of the silicon bulk thickness, the buried oxide thickness (BOX), and the aspect ratio Fin-height/Fin-width on the subthreshold swing and DIBL. The analysis has led to several critical observations: the ratio tSi / tBOX has a significant effect on the subthreshold swing and the device behavior, a thinner BOX and a thicker substrate would provide a better subthreshold swing (steeper slope) leading to a higher Ion / Ioff ratio, a fin-width much smaller than the finheight, and a smaller buried oxide film thickness (tox ) will be needed to accomplish lower S. The substrate thickness is another parameter that can be considered to achieve a lower value of S. Devices with the higher aspect ratio Hfin / Wfin exhibit improved ‘S′ and drain-induced barrier lowering (DIBL). Our analysis shows that a subthreshold swing of ~70mV / decade and DIBL of ~24mV / V can be achieved for AR ≈ 3 or higher. There are many BSIM, PSP, and other standard device models for conventional and emerging devices like FDSOI, bulk FinFET, triple-gate FET, UTB-SOI, and UTBB-SOI. Developing these models requires complete characterization of all the physical and electrical parameters of the devices. Since there is no publicly available SPICE or Verilog-A model for tri-gate SOI-FinFET, we must rely on mathematical modeling to analyze the internal device capacitances of SOI-FinFET. This analysis will have future utility in developing complete device models once other device parameters are analyzed and understood clearly. This preliminary analysis will also help analyze the suitability of the device for ultra-low-power circuit designs. By determining the optimum values of thecapacitive parameters, excellent device performance such as low switching voltage can be accomplished.

effects and lead to better performance. B. Yu et al. conclude that FinFET electrostatics could be further enhanced by reducing the fin width [37]. M. Rodwell and D. Elias in Ref. [38] reported that tall and narrow fins exhibit excellent subthreshold performance with a nearly ideal subthreshold slope and DIBL. In Ref. [33], high aspect ratio of tri-gate FinFETs are fabricated with fin widths down to 5 nm and a record aspect ratio of 13. The device demonstrates excellent performance, manifested in reduced off-state leakage due to the improved electrostatic control of the gate over the channel. The aspect ratio tuning and tradeoffs can be summarized in the area or layout efficiency, manufacturing complexity (fins with uniform and narrow width), and design efficiency (short-channel-effect). FinFETs with a high aspect ratio have superior layout efficiency and less area penalty [39]. This result is established by Anil et al. who concluded that a higher fin aspect ratio is required for FinFET to have layout efficiency comparable to that of planar MOSFET [40]. Narrow width and a large aspect ratio provide better channel control, and hence, lower leakage (Wfin is scaled to prevent short-channel-effects). However, wider transistors (large Wfin ) provide more current per Fin. Wfin must be smaller to effectively suppress off-state leakage current. FinFET efficiency can be increased by integrating various effective channels in multi-parallel fin fusion, in addition to increasing the fin height for a larger current per layout area. 5. Conclusion The internal device structure and capacitances of SOI-FinFET have been studied thoroughly and closed form models for the SOI-FinFET intrensic capacitances have been developed. We have studied the subthreshold behavior of an SOI-FinFET device and proposed an Appendix A. Estimation of the Body Factor (η) of SOI FinFET

In this calculation we used the following notation of the internal device capacitances of SOI-FinFET as presented in Fig. 4b.

C1 = Cgf − top + 2Cgf − vr

(A1)

C2 = Cox − fb

(A2)

C3 = CSi

(A3)

C4 = 2Cox − gb

(A4)

Here C1 and C2 are in series and their equivalent capacitance can be given by (A5). And the equivalent capacitance Ceq can be given by (A6).

Co = C1C2 /(C1 + C2)

(A5)

Ceq = (Co + C4)C3/(Co + C3 + C4)

(A6)

The total charges distributed in the capacitive network can be written as: q=VGCeq . VG is the total voltage applied at the network (gate voltage). Since C1 and C2 are in series, thus, share the same charge. Similarly, C1, C2, C4 shared the same charges with C3. By considering the same ideologies of a current flow past a given point (if Vi is the voltage across the capacitor Ci, the charges is defined by the relation Qi = CiVi ). The total charges can be expressed as shown in the equations below:

q=C1V1 + C4V4

(A7)

q=C2V2 + C4V4

(A8)

q=C3V3

(A9)

q=CeqVG

(A10)

Furthermore, since C1 and C2 share the same charges and V1 and V2 are the voltages across each of them, we have: C1V1 = C2V2 hence V1 = C2V2 /C1 From Kirchhoff's Loop Rule: V1 + V2 = V4 (Fig. 4b) shows the loop). Substitute for V1 its equivalent expression to get:

V4 = V2(C1 + C2)/C1

(A11)

By equating (A9) and (A10) we get the expression (A12).

V3 = CeqVG /C3

(A12)

Substituting (A11) into (A8) to get:

35

Microelectronics Journal 62 (2017) 30–37

A. Es-Sakhi, M. Chowdhury

⎡ C ⎤ q = ⎢C2 + (C2 + C1) 4 ⎥V2 C1 ⎦ ⎣

(A13)

Equating the Eqs. (A10) and (A13) and solve for V2 to get:

V2 =

CeqVG C

C2 + (C2 + C1) C4

(A14)

1

We have:

ψS = V2 + V3

(A15)

Replacing (A12) and (A14) into (A15) to get:

⎡ C C + C C + (C + C )C ⎤ 1 3 2 1 4 ⎥ ψS = CeqVG⎢ 1 2 ⎣ {C1C2 + (C1 + C2)C4}C3 ⎦

(A16)

Solving for VG to get:

VG =

1 {C1C2 + (C1 + C2)C4}C3 ψ Ceq C1C2 + C2C3 + (C2 + C1)C4 S

(A17)

The body factor η can be evaluated as:

η=

1 {C1C2 + (C1 + C2)C4}C3 Ceq C1C2 + C2C3 + (C2 + C1)C4

(A18)

The Eq. (A18) simplified to:

η=1+

C 2C 3 C1(C2 + C3 + C4)+C2C4

(A19)

Replacing Ceq , C1, C2 , C3, and C4 with their values ((A1), (A2), (A3), and (A4)) to get (A20)

η=1+

Cox−fb × CSi (Cgf−top + 2 × Cgf−vr ) × (Cox−fb + CSi +2Cox − gb) + 2 × Cox−fb ×Cox − gb

(A20)

References [15] [1] A. Majumdar, Z. Ren, S.J. Koester, W. Haensch, Undoped-body extremely thin SOI MOSFETs With back gates (Oct.), IEEE Trans. Electron Devices 56 (10) (2009) 2270–2276 (Oct.). [2] S.E. Jamali Mahabadi, Upper drift region double step partial SOI LDMOSFET: a novel device for enhancing breakdown voltage and output characteristics (Jan.), Superlattices Microstruct. 89 (2016) 345–354 (Jan.). [3] M. Imani, S. Patil, T.S. Rosing, Hierarchical design of robust and low data dependent FinFET based SRAM array, Proc. 2015 IEEE/ACM Int. Symp. Nanoscale Archit. (NANOARCH¿¿15) (2015) 63–68. [4] M. Saremi, B. Ebrahimi, A. Afzali-Kusha, Ground plane SOI MOSFET based SRAM with consideration of process variation, in 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), pp. 1–4, 2010. [5] M. Saremi, A. Afzali-Kusha, S. Mohammadi, Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits (Jul.), Microelectron. Eng. 95 (2012) 74–82 (Jul.). [6] N. Fasarakis, et al., Compact Capacitance Model of Undoped or Lightly Doped UltraScaled Triple-Gate FinFETs (Dec.), IEEE Trans. Electron Devices 59 (12) (2012) 3306–3312 (Dec.). [7] M.V. Dunga, et al., BSIM-MG: a versatile multi-gate FET model for mixed-signal design (2007), IEEE Symp. VLSI Technol. (2007) 60–61. [8] J. Lacord, G. Ghibaudo, F. Boeuf, Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures (May), IEEE Trans. Electron Devices 59 (5) (2012) 1332–1344 (May). [9] H. Aghababa, B. Ebrahimi, M. Saremi, V. Moalemi, B. Forouzandeh, G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems, IEICE Electron. Express 0 (2012). [10] V. Subramanian, et al., Planar bulk MOSFETs versus FinFETs: an analog/RF perspective (Dec.), IEEE Trans. Electron Devices 53 (12) (2006) 3071–3079 (Dec.). [11] A. Datta, A. Goel, R.T. Cakici, H. Mahmoodi, D. Lekshmanan, K. Roy, Modeling and circuit Synthesis for independently controlled double gate FinFET devices (Nov.), IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 26 (11) (2007) 1957–1966 (Nov.). [12] M.M. Chowdhury, J.G. Fossum, Physical insights on electron mobility in contemporary FinFETs (Jun.), IEEE Electron Device Lett. 27 (6) (2006) 482–485 (Jun.). [13] T. Rudenko, N. Collaert, S. De Gendt, V. Kilchytska, M. Jurczak, D. Flandre, Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode (Jun.), Microelectron. Eng. 80 (2005) 386–389 (Jun.). [14] Z. Jakšić, R. Canal, Enhancing 6T SRAM cell stability by back gate biasing techniques for10nm SOI FinFETs under process and environmental variations, in

[16]

[17]

[18]

[19] [20] [21] [22]

[23]

[24] [25]

[26] [27]

[28]

[29] [30]

[31]

36

Mixed Design of Integrated Circuits and Systems (MIXDES), 2012 in: Proceedings of the 19th International Conference, pp. 103–108, 2012. F. El Mamouni, Single-event-transient effects in sub-70 nm bulk and SOI FINFETS, Vanderbilt University, Nashville, Tennessee, 2012. M. Rostami, K. Mohanram, Novel dual-Vth independent-gate FinFET circuits, in 2010 in: Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 867–872, 2010. S. Nuttinck, B. Parvais, G. Curatola, A. Mercha, Double-Gate finFETs as a CMOS Technology Downscaling Option: an RF Perspective (Feb.), IEEE Trans. Electron Devices 54 (2) (2007) 279–283 (Feb.). P. Feng, P. Ghosh, Comparison of silicon-on-insulator and Body-on-insulator FinFET based digital circuits with consideration on self-heating effects, Semicond. Device Res. Symp. (ISDRS), 2011 Int. (2011) 1–2. K. Bailey, K.S. Gurumurthy, 3D device modeling and assessment of Triple gate SOI FinFET for LSTP applications, Int. J. Comput. Theory Eng. 4 (5) (2012) 831. C. Hu, FinFET 3D Transistor and the Concept Behind it, University of california Berkeley. S.L. Tripathi, R. Mishra, N. Vadthiya, R.A. Mishra, Optimization of pie-gate bulk FinFET structure, Int. J. Comput. Appl. 59 (2) (2012). H.-W. Cheng, C.H. Hwang, Y. Li, Propagation delay dependence on channel fins and geometry aspect ratio of 16-nm multi-gate MOSFET inverter, 1st Asia Symp. Qual. Electron. Des., 2009. ASQED 2009 (2009) 122–125. Y. Omura, H. Konishi, K. Yoshimoto, Impact of fin aspect ratio on short-channel control and Drivability of multiple-gate SOI MOSFET's, JSTS:J. Semicond. Technol. Sci. 8 (4) (2008) 302–310. S. Xin, Nanoscale Bulk MOSFET Design and Process Technology for Reduced Variability, University of California, Berkeley, Berkeley, California, 2010. H.B. Palmer, The capacitance of a parallel-plate Capacitor by the SchwartzChristoffel transformation (Mar.), Trans. Am. Inst. Electr. Eng. 56 (3) (1937) 363–366 (Mar.). H. Yang, Microgyroscope and microdynamics, Ph.D. dissertation, 200AD. M. Hosseini, G. Zhu, Y.-A. Peter, A new formulation of fringing capacitance and its application to the control of parallel-plate electrostatic micro actuators (Oct.), Analog Integr. Circuits Signal Process. 53 (2–3) (2007) 119–128 (Oct.). V. Jovanović, T. Suligoj, J. Schulze, I. Eisele, G. Jernigan, P.E. Thompson, Characteristics of 30 nm Long Vertical Silicon-on-Nothing (SON) MOSFET, presented at the MIPRO 2005 International Conference, 2005. S.K. Hadia, R.R. Patel, D. Yogesh, P. Kosta, FinFET Archit. Anal. Fabr. Mech. (2014). B. Sviličić, V. Jovanović, T. Suligoj, Vertical silicon-on-nothing FET: subthreshold slope calculation using compact capacitance model, Inf. MIDEM J. Micro. Electron Compon. Mater. 38 (2008) 1–4. F. Balestra, Analysis of the dependence of the subthreshold swing and the threshold

Microelectronics Journal 62 (2017) 30–37

A. Es-Sakhi, M. Chowdhury

[32] [33]

[34]

[35]

gate FinFETs, Semicond. Sci. Technol. 21 (4) (2006) 409. [36] J.-P. Colinge (Ed.), FinFETs and Other Multi-Gate Transistors, Springer US, Boston, MA, 2008. [37] B. Yu, et al., FinFET scaling to 10 nm gate length, in Electron Devices Meeting, 2002. IEDM ’02. International, pp. 251–254, 2002. [38] M. Rodwell, D. Elias, Prospects for high-aspect-ratio FinFETs in low-power logic, 2013 Third Berkeley Symp. Energy Effic. Electron. Syst. (E3S) (2013) 1–2. [39] H.R. Huff (Ed.), Into the Nano Era, 106 Springer Berlin Heidelberg, Berlin, Heidelberg, 2009. [40] K.G. Anil, K. Henson, S. Biesemans, N. Collaert, Layout density analysis of FinFETs, in in: Proceedings of the 33rd Conference on European Solid-State Device Research, 2003. ESSDERC ’03, pp. 139–142, 2003.

voltage on the substrate voltage of thin-film SOI MOSFETs: extraction of the interface state densities, in SOI Conference, 1991. Proceedings, 1991, IEEE International, pp. 88–89, 1991. E. Pop, S. Sinha, K.E. Goodson, (Jan.), Monte Carlo Model. Heat. Gener. Electron. Nanostruct. (2002) 85–90 (Jan.). M.J.H. van Dal, et al., Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography, 2007 IEEE Symp. VLSI Technol. (2007) 110–111. H.-W. Cheng, C.H. Hwang, Y. Li, Propagation delay dependence on channel fins and geometry aspect ratio of 16-nm multi-gate MOSFET inverter, 1st Asia Symp. Qual. Electron. Des., 2009. ASQED 2009 (2009) 122–125. A. Kranti, G.A. Armstrong, Performance assessment of nanoscale double- and triple-

37