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Subthreshold performance of gate engineered FinFET devices and circuit with high-k dielectrics
Microelectronics Reliability 53 (2013) 499–504
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Research note
Subthreshold performance of gate engineered FinFET devices and circuit with high-k dielectrics D. Nirmal a,⇑, P. Vijayakumar b, Divya Mary Thomas a, Binola K. Jebalin a, N. Mohankumar c a
Department of Electronics and Communication Engineering, Karunya University, Coimbatore, Tamil Nadu, India Department of Electrical and Electronic Engineering, Karpagam College of Engineering, Coimbatore, Tamil Nadu, India c SKP Engineering College, Thiruvanamalai, Tamil Nadu, India b
a r t i c l e
i n f o
Article history: Received 18 April 2012 Received in revised form 13 September 2012 Accepted 13 September 2012 Available online 11 October 2012
a b s t r a c t This paper analyses the impact of gate engineering on the performance of gate engineered FinFETs for system-on-chip applications with high-k dielectrics. Equivalent oxide thickness of gate oxide can be reduced by the usage of high-k dielectric materials and it was found that by replacing high-k dielectric materials as gate oxide the performance of the device can be improved. Gate engineering technique used here is dual material gate technology and the simulations were done using Sentaurus simulator. The parameters such as ON current, OFF current, ION/IOFF ratio, DIBL (Drain Induced Barrier Lowering), normalized transconductance, transconductance generation factor, output resistance, intrinsic gain, and intrinsic gate capacitances were analyzed. A proper trading of Fin width, Fin doping and gate work function improves the short channel effects. The suitability of nanoscale dual material FinFETs for circuit applications was examined by comparing the performance of an inverter for different high-k dielectrics and the circuit showed a significant improvement in gain with increased k values. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction The decreasing gate control over the channel of the MOSFET is a matter of concern for future technology. The presence of second gate increases the effective gate control in FinFET thereby reducing DIBL. These multi-gate devices, which can be fabricated as Fin Field Effect Transistors (FinFETs), are potentially scalable to the end of International Technology Roadmap for Semiconductors (ITRS) because of their ultra-thin bodies which suppress the short channel effects owing to the simultaneous control of the channel by more than one gate [1]. FinFETs with channel lengths below 100 nm shows considerable threshold voltage roll off and DIBL effects. To overcome these effects, gate engineering technique is used. The gate engineered FinFETs provides a better scalability option due to its excellent immunity to SCEs (Short Channel Effects) [2,3]. Gate engineering technique such as DM-FinFET has two different materials with different work functions being merged together to form a single gate SOI (Silicon on Insulator) MOSFET. In the DM FinFET structure, the work function of the gate material are taken as 4.55 eV (M1, molybdenum) close to the source is chosen higher than that close to the drain end which is 4.1 eV (M2, aluminum) for n-channel FinFETs. As a result, the electric field and electron velocity along the channel suddenly increases near the interface of the two gate materials which results in increased gate transport effi⇑ Corresponding author. E-mail address: [email protected] (D. Nirmal). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.09.008
ciency [4]. This shows that the threshold voltage under gate material M1 is higher than that of under gate material M2. When the drain voltage exceeds the drain saturation voltage, the excess voltage is absorbed by gate metal M2 preventing the drain field from penetrating into the channel [5]. Either the channel is very lightly doped or undoped (1015 cm3). As a result, it leads to the reduction in mobility degradation in the device. This technique also avoids the effects due to the random microscopic dopant fluctuations [6–9]. Exponentially increased gate oxide leakage current with the decreasing gate oxide thickness is the main driver for search for high-k dielectric materials [1]. Also SiO2 is running out of atoms for further scaling. High-k dielectric materials have EOT of 1.0 nm with negligible gate oxide leakage and desirable transistor threshold voltages for n and p-channel FinFETs. So in this paper the device performance is analyzed by replacing the gate dielectric, SiO2 with various high-k materials such as Si3N4, Al2O3, LaAlO3, HfO2/ZrO2, and TiO2 [10]. 2. Device structure and parameters The technology parameters and the supply voltages used for device simulations are according to the suggestion by 2010 version of International Technology Roadmap for Semiconductors (ITRS) for 22 nm gate length devices [11]. Fig. 1 shows the schematic cross-sectional view of the DM-FinFET. As reported in [12] about the optimization of DMG (Dual Metal Gate) technology, the work
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D. Nirmal et al. / Microelectronics Reliability 53 (2013) 499–504
Fig. 1. Cross-sectional view of the DM-FinFET.
functions of metals M1 (molybdenum) and M2 (aluminum) were taken as 4.55 eV and 4.1 eV respectively along with equal lengths of L1 and L2 and a threshold voltage of 0.3 V at a drain voltage of 0.1 V was obtained. The source and the drain regions were doped with phosphorous active concentration of 1 1020 cm3 for creating the n-channel DM-FinFET. The channel region which has a thickness of 20 nm is lightly doped with boron active concentration of 1 1016 cm3. The use of poly-Si electrodes in MOS devices can significantly increase the capacitance equivalent thickness (CET) resulting in a high sheet resistance and causes dopant diffusion through the high-k dielectric layer. One viable way to solve these challenges is to use a metal as gate electrode. Metal gates eliminate depletion effects of polysilicon. All the simulations performed were calibrated with standard experimental data [12]. Device simulator DESSIS of integrated systems engineering technology computer aided design (ISE-TCAD) [13] was used for realization and analysis of all the devices used in this study. An enhanced slicer was used to observe the doping profile, the electric field and the carrier velocity along the channel. Simulations were performed for a wide range of proposed gate dielectric k values such as 3.9, 7.5, 10, 15, 25, and 40. The operation of the device in sub threshold regime is the main consideration for the performance analysis for each of these devices. In the simulation, the density gradient model was used which solved the quantum potential equations self-consistently with the Poisson and carrier continuity equations. The quantum potential was introduced to include quantization effects in a classical device simulation. In the density-gradient transport approximation, the quantum potential is a function of the carrier densities and their gradients. 2.1. Selection of ZrO2 as high-k Nanosizing of high-k dielectric materials seems to improve the electrical, mechanical and optical properties of any compound drastically due to the increase in surface area [1]. The band gap of SiO2 is 9 eV, which is large with sufficiently large conduction and valence band offsets. Also the band gap of TiO2 is 3.5 which are lesser than the above specified band gap range. Moreover the less band gap in TiO2 increases the leakage current. SiO2 has been
used as a gate oxide material for decades. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to unwieldy power consumption and reduced device reliability [15–19]. Based on the analysis, zirconia was found as the emerging alternate for SiO2 and being a metal oxide it is proved to be invariant with higher thermal expansion ratio when subjected for operation in an FET configuration [1]. Replacing the SiO2 with a high-k material allows the increase of gate capacitance with reduced leakage effects [16–19]. In this work the gate insulator silicon dioxide of the DM-FinFET was replaced with different high-k material and simulations were carried out to evaluate their performance. 3. Simulation results and discussion The simulation was performed using TCAD tools. In each simulation, the physical gate oxide thickness was proportionately scaled such that the (EOT) remains the same. 3.1. Analysis of parameters of dual material FinFET using high-k dielectrics The ON-current refers to the drive current in saturation, while OFF-current refers to the total leakage current, which is the sum of subthreshold, gate and junction leakage currents. The delay is a measure of the speed of the device and is measured as
s¼
C gg V dd ION
ð1Þ
where Cgg the total gate capacitance at the supply voltage Vdd and ION is the ON current of the MOS device under consideration. The gate engineered device with ZrO2 as dielectric material shows an increase of drain current by about 5% in the subthreshold regime over SiO2 based devices. The reason behind such improvement of the drain current is attributed to the increased electron velocity at the source end and thus improved carrier transport efficiency of the device [5]. Since this improvement is more prominent in the subthreshold regime, the device is applicable for low power subthreshold analog circuits. In Fig. 2a, the OFF current and the ON cur-
D. Nirmal et al. / Microelectronics Reliability 53 (2013) 499–504
rent of the dual material FinFET are plotted for various k values. SiO2 is found to have the highest OFF current and it decreases exponentially with increasing k value. So integration of high-k dielectrics in the device reduces the leakage in the device. Similarly the ON current decreases exponentially with increasing k values. The ratio of ON current to OFF current is plotted against the different high-k gate oxide material values are shown in Fig. 2b. It is clear that ION/IOFF ratio increases by 33% with increasing k value. This ratio should be high for the proper switching of the devices. Since the DM-FinFET with ZrO2 has a large ratio, the device switches between the OFF state and the ON state quickly. Here even TiO2 has the lowest value; it is not useful because of lower band gap thereby increasing the leakage. For logic applications, DIBL plays an important role as device dimensions are scaled rigorously. The DIBL co-efficient was computed as:
DIBL ¼
V t;lin V t;sat V dd V t;lin
ð2Þ
where Vt,lin and Vt,sat are the threshold voltages measured at linear and saturation region for drain voltages of 0.1 V and 1.2 V respectively. The supply voltage of 1.2 V was taken as per the conventions of ITRS 2010 for 45 nm gate length in regard of logic applications. From Fig. 2b, DIBL shows exponential decrease of 75% with increase in high-k value DM FinFET.
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The surface potential along the channel length for DM n-channel FinFETs is shown in Fig. 2c for various high-k values. In this figure, the position along the channel is plotted in the x-axis direction and the DM FinFETs devices show a step potential profile at the interface of the two metals along the channel. It is clearly visible that the DM FinFET technology provides a larger increase of potential, thereby improving DIBL characteristics. The step increase of surface potential in the case of the DM FinFET devices results in an additional electric field peak at the interface along with the existing peak at the drain end. These additional peaks due to gate engineering techniques reduce the effective field at the drain end, resulting in smaller DIBL and hot-carrier effects, which are the major effects in the case of the short-channel devices. The lateral electric field is high for the k value of 3.9 which corresponds to SiO2.The lateral electric field profile at the surface is shown in Fig. 2d, for different high-k dielectric materials. For DM FinFET devices, the electric field discontinuity at the interface of two gate metals causes channel field flattening, which results in a larger average velocity when the electrons enter the channel from the source. The electron velocity profile at the surface is shown in Fig. 3a, for different high-k dielectrics. 3.2. Analog performance The different analog performance parameters studied in this section are the transconductance (gm), transconductance genera-
Fig. 2. (a) Comparison of OFF current and ON current DM-FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V. (b) Comparison of ION/IOFF and DIBL for Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V. (c) Comparison of electrostatic surface potential along the channel in Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V. (d) Comparison of electron mobility variation along the channel in Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V.
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tion factor (gm/Id) and output resistance (Ro). Fig. 3b shows the variation of transconductance with normalized drain current at a drain bias of 1.2 V for various gate to source voltages. The DM FinFET device shows an improved drain current and a 3% increase in transconductance in strong inversion as the high-k dielectric value is increased. The improvement in peak gm in DM DG MOSFET can be attributed to the improved charge control by the top and bottom gates in the devices [14,15]. Another parameter examined is the transconductance generation factor (TGF) or gm/Id ratio. It is clear from Fig. 3c that the transconductance generation factor is maximum for TiO2 and minimum for SiO2 for different gate to source voltages. So the circuits based on subthreshold operation of devices are expected to provide a higher gain.
The output resistance, Ro of a MOS transistor was evaluated as
Ro ¼ V A =ID
ð3Þ
where VA and ID are early voltage and saturated drain current. Gate engineering device with TiO2 shows a higher output resistance. Such an improvement is due to the fact that the region of the channel under metal M2 provides a shielding effect such that the channel region under M1 is not affected by drain to source voltage variations. The output resistance variation of the DM FinFET device for different high-k material is shown in Fig. 3d. It is clear that TiO2 which corresponds to dielectric constant of 40 has a maximum output resistance of 220 MX whereas SiO2 has a minimum output resistance of 2 MX. Thus the output resistance increases as the
Fig. 3. (a) Comparison of lateral electric field along the channel in Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V. (b) Comparison of variation of drain current and transconductance in Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V. (c) Comparison of TGF for the Dual Material n-channel FinFETs with different high-k materials as a function of Vgs = 0.15 V. (d) Comparison of output resistance and intrinsic gain for Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V.
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D. Nirmal et al. / Microelectronics Reliability 53 (2013) 499–504 Table 1 Comparison of Cgd, Cgs, Cgg and gain of DM-FinFETs for different gate dielectric materials. Dielectric constant
Dielectric material
Gate to drain capacitance, Cgd (fF)
Gate to source capacitance, Cgs (fF)
Total gate capacitance, Cgg, (fF)
Voltage gain (V/v)
k = 3.9 k = 7.5 k = 10 k = 15 k = 25 k = 40
SiO2 Si3N1 Al2O3 LaAlO3 HfO2/ZrO2 TiO2
1 1.5 1.75 2.5 3.75 5.5
0.53 0.565 0.58 0.6 0.625 0.645
1.5 2.1 2.5 3.1 4.3 6
0.7115 0.7337 0.8111 0.8288 0.8348 0.8401
Fig. 4. (a) A high gain CMOS inverting amplifier. (b) Comparison of voltage transfer characteristics of CMOS inverter with DM n-channel FinFETs with different high-k materials as a function of Vds = 0.6 V.
dielectric constant value of gate oxide material increases. So this device should be applicable for feedback and cascade amplifiers. The gate-engineered FinFET device with an undoped body does not suffer from any mobility degradation issue, thereby exhibiting an increased gain in both the weak and strong inversion regimes. The intrinsic gain which is product of transconductance and output impedance is shown in Fig. 3d it is clear that intrinsic gain is minimum for SiO2. The intrinsic gate capacitances represent an important parameter in the case of RF applications. The intrinsic gate capacitances in the DM-FinFETs are gate to- source (Cgs), gate-todrain capacitances (Cgd). Table 1 shows the values of Cgs, Cgd and Cgg of the DM-FinFET for various dielectric constant values. The Cgs, Cgd and Cgg increases with dielectric thereby reducing the leakage current and increasing the gate control. The electron density at the source end is considerably less compared with that at the drain end in the case of the DM FinFET devices. This is due to the fact that the channel at the source side has a higher threshold voltage due to the higher work function material at the source side. The larger values of Cgd in the case of the DM FinFETs result from capacitance coupling between drain and gate electrodes.
3.3. Circuit applications The circuit performance of DM-FinFET was analyzed by investigating the gain of a simple push pull CMOS inverting amplifier. Fig. 4a shows a high gain CMOS inverting amplifier. The width of the p-channel device (Wp) is chosen three times the width of the
n-channel device (Wn) to match the subthreshold current of both the devices. The voltage transfer characteristics of the CMOS inverter with DM n channel FinFET with different dielectric constant values is shown in Fig. 4b, so here it is proved that the integration of high-k dielectrics improves the performance of the circuit. 4. Conclusion In this paper, we have clearly analyzed the influence of gate engineering on the performance of FinFET for different high-k dielectrics. A proper trading of Fin width, Fin doping and gate work function improves short channel effects. The performance of an inverter with different high-k dielectrics is also illustrated by using the DMFinFET architecture. Conventional SiO2 gate dielectric material was compared with different high-k dielectrics in the device and better performance was observed. However from the analysis, the ZrO2 based dielectric material was found to be the best alternative for SiO2 because TiO2 has a band gap of 3 eV which is not favorable for switching purposes. The gate capacitance of the device increases by 65%, ION/IOFF ratio increases by 33% and leakage current decreases by 70% as the gate dielectric material of the device is changed from SiO2 to ZrO2. The DM-FinFET device shows an improved drain current and a 3% increase in transconductance. DIBL shows exponential decrease of 75% in the ZrO2 based device over conventional device. The integration of high-k dielectrics in the DM-FinFET enhances the device performance to a great extend
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and it makes the device one of the promising candidates for future semiconductor devices. The DM-FinFET with nanosized ZrO2 as gate dielectric improves the overall performance of the device as well as circuit and they can be used for low power applications. As a result, DM-FinFET with ZrO2 as gate dielectric can be considered as a promising device for future semiconductor industry. With the CMOS processing technology already reached less than 100-nm regime, fabricating DM FinFET devices should not be too complicated in future. Thus, for thin-film silicon-on-insulator or FinFET devices, the gate work function engineering such as the DM FinFET technology is the most favorable technique for low-power sub threshold analog applications. References [1] Nirmal D, Nalini B, Vijayakumar P. Nanosized high k dielectric material for FinFET. Integr Ferroelectrics 2010;121(1):31–5. [2] Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP. Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 2001;89(3):259–88. [3] Colinge JP. Multiple-gate SOI MOSFETs. Solid State Electron 2004; 48(6):897–905. [4] Nirmal D, Thomas Divya Mary, Shruti K, Samuel Patrick Chella, Vijaya Kumar P, Mohan Kumar N. Impact of gate engineering on double gate MOSFETs using high-k dielectrics. In: Proceedings of the 3rd international conference on electronics computer technology, vol. 1, 2011. p. 31–4. [5] Mohan Kumar N, Binit Syamal, Sarkar CK. Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications. Microelectron Reliab 2009;49(12):1491–7. [6] Chakraborty S, Mallik A, Sarkar CK, Ramgopal Rao V. Impact of halo doping on the subthreshold performance of deep-sub micrometer CMOS devices and
[7]
[8]
[9] [10]
[11] [12]
[13] [14] [15]
[16] [17] [18]
[19]
circuits for ultralow power analog/mixed signal applications. IEEE Trans Electron Dev 2007;54(2):241–8. Mohan Kumar N, Binit Syamal, Sarkar CK. Performance and optimization of dual material gate (DMG) short channel BULK MOSFETs for analog/mixed signal applications. Int J Electron 2009;96(6):603–11. Yuan J, Woo JCS. A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance. IEEE Electron Dev Lett 2005;26(11):829–31. Nirmal D, Vijaya Kumar P. Fin field effect transistors performance in analog and RF for high-k dielectrics. Defence Sci J 2011;61(3):35–240. Nirmal D, Shruti K, Thomas Divya Mary, Samuel Patrick Chella, Vijaya Kumar P, Mohan Kumar N. Impact of channel engineering on FinFETs using high-k dielectrics. Int J Micro Nano Electron, Circ Syst 2011;3(1):7–11. International Technology Roadmaps for Semiconductor (ITRS); 2010. Chaudhry A, Kumar MJ. Investigation of the novel attributes of Na fully depleted dual-material gate SOI MOSFET. IEEE Trans Electron Dev 2004;51(9):1463–7. Integrated Systems Engineering (ISE) TCAD Manuals. Integrated Systems Engineering, Zurich, Switzerland; 2008 [release 10.0]. Lu H, Taur Y. An analytical potential model for symmetric and asymmetric DG MOSFETs. IEEE Trans Electron Dev 2006;53(5):1161–8. Mohan Kumar N, Binit Syamal, Sarkar CK. Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Trans Electron Dev 2010;57(4):820–6. Bouazra A, Abdi-Ben Nasrallah S, Said M, Poncet A. Current tunnelling in MOS devices with Al2O3/SiO2 gate dielectric. Res Lett Phys 2008:1–5. Robertson J. High dielectric constant oxides. Eur Phys J Appl Phys 2004;28(3):265–91. Manoj CR, Ramgopal Rao V. Impact of high k dielectrics on the device and circuit performance of nanoscale FinFETs. IEEE Electron Dev Lett 2007;28(4):295–7. Nirmal D, Vijaya Kumar P, Samuel Patrick Chella, Shruti K, Thomas Divya Mary, Mohan Kumar P. Analysis of dual gate MOSFETs using high k dielectrics. In: Proceedings of the 3rd international conference on electronics computer technology, vol. 1, 2011. p. 22–5.
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Research note
Subthreshold performance of gate engineered FinFET devices and circuit with high-k dielectrics D. Nirmal a,⇑, P. Vijayakumar b, Divya Mary Thomas a, Binola K. Jebalin a, N. Mohankumar c a
Department of Electronics and Communication Engineering, Karunya University, Coimbatore, Tamil Nadu, India Department of Electrical and Electronic Engineering, Karpagam College of Engineering, Coimbatore, Tamil Nadu, India c SKP Engineering College, Thiruvanamalai, Tamil Nadu, India b
a r t i c l e
i n f o
Article history: Received 18 April 2012 Received in revised form 13 September 2012 Accepted 13 September 2012 Available online 11 October 2012
a b s t r a c t This paper analyses the impact of gate engineering on the performance of gate engineered FinFETs for system-on-chip applications with high-k dielectrics. Equivalent oxide thickness of gate oxide can be reduced by the usage of high-k dielectric materials and it was found that by replacing high-k dielectric materials as gate oxide the performance of the device can be improved. Gate engineering technique used here is dual material gate technology and the simulations were done using Sentaurus simulator. The parameters such as ON current, OFF current, ION/IOFF ratio, DIBL (Drain Induced Barrier Lowering), normalized transconductance, transconductance generation factor, output resistance, intrinsic gain, and intrinsic gate capacitances were analyzed. A proper trading of Fin width, Fin doping and gate work function improves the short channel effects. The suitability of nanoscale dual material FinFETs for circuit applications was examined by comparing the performance of an inverter for different high-k dielectrics and the circuit showed a significant improvement in gain with increased k values. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction The decreasing gate control over the channel of the MOSFET is a matter of concern for future technology. The presence of second gate increases the effective gate control in FinFET thereby reducing DIBL. These multi-gate devices, which can be fabricated as Fin Field Effect Transistors (FinFETs), are potentially scalable to the end of International Technology Roadmap for Semiconductors (ITRS) because of their ultra-thin bodies which suppress the short channel effects owing to the simultaneous control of the channel by more than one gate [1]. FinFETs with channel lengths below 100 nm shows considerable threshold voltage roll off and DIBL effects. To overcome these effects, gate engineering technique is used. The gate engineered FinFETs provides a better scalability option due to its excellent immunity to SCEs (Short Channel Effects) [2,3]. Gate engineering technique such as DM-FinFET has two different materials with different work functions being merged together to form a single gate SOI (Silicon on Insulator) MOSFET. In the DM FinFET structure, the work function of the gate material are taken as 4.55 eV (M1, molybdenum) close to the source is chosen higher than that close to the drain end which is 4.1 eV (M2, aluminum) for n-channel FinFETs. As a result, the electric field and electron velocity along the channel suddenly increases near the interface of the two gate materials which results in increased gate transport effi⇑ Corresponding author. E-mail address: [email protected] (D. Nirmal). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.09.008
ciency [4]. This shows that the threshold voltage under gate material M1 is higher than that of under gate material M2. When the drain voltage exceeds the drain saturation voltage, the excess voltage is absorbed by gate metal M2 preventing the drain field from penetrating into the channel [5]. Either the channel is very lightly doped or undoped (1015 cm3). As a result, it leads to the reduction in mobility degradation in the device. This technique also avoids the effects due to the random microscopic dopant fluctuations [6–9]. Exponentially increased gate oxide leakage current with the decreasing gate oxide thickness is the main driver for search for high-k dielectric materials [1]. Also SiO2 is running out of atoms for further scaling. High-k dielectric materials have EOT of 1.0 nm with negligible gate oxide leakage and desirable transistor threshold voltages for n and p-channel FinFETs. So in this paper the device performance is analyzed by replacing the gate dielectric, SiO2 with various high-k materials such as Si3N4, Al2O3, LaAlO3, HfO2/ZrO2, and TiO2 [10]. 2. Device structure and parameters The technology parameters and the supply voltages used for device simulations are according to the suggestion by 2010 version of International Technology Roadmap for Semiconductors (ITRS) for 22 nm gate length devices [11]. Fig. 1 shows the schematic cross-sectional view of the DM-FinFET. As reported in [12] about the optimization of DMG (Dual Metal Gate) technology, the work
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D. Nirmal et al. / Microelectronics Reliability 53 (2013) 499–504
Fig. 1. Cross-sectional view of the DM-FinFET.
functions of metals M1 (molybdenum) and M2 (aluminum) were taken as 4.55 eV and 4.1 eV respectively along with equal lengths of L1 and L2 and a threshold voltage of 0.3 V at a drain voltage of 0.1 V was obtained. The source and the drain regions were doped with phosphorous active concentration of 1 1020 cm3 for creating the n-channel DM-FinFET. The channel region which has a thickness of 20 nm is lightly doped with boron active concentration of 1 1016 cm3. The use of poly-Si electrodes in MOS devices can significantly increase the capacitance equivalent thickness (CET) resulting in a high sheet resistance and causes dopant diffusion through the high-k dielectric layer. One viable way to solve these challenges is to use a metal as gate electrode. Metal gates eliminate depletion effects of polysilicon. All the simulations performed were calibrated with standard experimental data [12]. Device simulator DESSIS of integrated systems engineering technology computer aided design (ISE-TCAD) [13] was used for realization and analysis of all the devices used in this study. An enhanced slicer was used to observe the doping profile, the electric field and the carrier velocity along the channel. Simulations were performed for a wide range of proposed gate dielectric k values such as 3.9, 7.5, 10, 15, 25, and 40. The operation of the device in sub threshold regime is the main consideration for the performance analysis for each of these devices. In the simulation, the density gradient model was used which solved the quantum potential equations self-consistently with the Poisson and carrier continuity equations. The quantum potential was introduced to include quantization effects in a classical device simulation. In the density-gradient transport approximation, the quantum potential is a function of the carrier densities and their gradients. 2.1. Selection of ZrO2 as high-k Nanosizing of high-k dielectric materials seems to improve the electrical, mechanical and optical properties of any compound drastically due to the increase in surface area [1]. The band gap of SiO2 is 9 eV, which is large with sufficiently large conduction and valence band offsets. Also the band gap of TiO2 is 3.5 which are lesser than the above specified band gap range. Moreover the less band gap in TiO2 increases the leakage current. SiO2 has been
used as a gate oxide material for decades. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to unwieldy power consumption and reduced device reliability [15–19]. Based on the analysis, zirconia was found as the emerging alternate for SiO2 and being a metal oxide it is proved to be invariant with higher thermal expansion ratio when subjected for operation in an FET configuration [1]. Replacing the SiO2 with a high-k material allows the increase of gate capacitance with reduced leakage effects [16–19]. In this work the gate insulator silicon dioxide of the DM-FinFET was replaced with different high-k material and simulations were carried out to evaluate their performance. 3. Simulation results and discussion The simulation was performed using TCAD tools. In each simulation, the physical gate oxide thickness was proportionately scaled such that the (EOT) remains the same. 3.1. Analysis of parameters of dual material FinFET using high-k dielectrics The ON-current refers to the drive current in saturation, while OFF-current refers to the total leakage current, which is the sum of subthreshold, gate and junction leakage currents. The delay is a measure of the speed of the device and is measured as
s¼
C gg V dd ION
ð1Þ
where Cgg the total gate capacitance at the supply voltage Vdd and ION is the ON current of the MOS device under consideration. The gate engineered device with ZrO2 as dielectric material shows an increase of drain current by about 5% in the subthreshold regime over SiO2 based devices. The reason behind such improvement of the drain current is attributed to the increased electron velocity at the source end and thus improved carrier transport efficiency of the device [5]. Since this improvement is more prominent in the subthreshold regime, the device is applicable for low power subthreshold analog circuits. In Fig. 2a, the OFF current and the ON cur-
D. Nirmal et al. / Microelectronics Reliability 53 (2013) 499–504
rent of the dual material FinFET are plotted for various k values. SiO2 is found to have the highest OFF current and it decreases exponentially with increasing k value. So integration of high-k dielectrics in the device reduces the leakage in the device. Similarly the ON current decreases exponentially with increasing k values. The ratio of ON current to OFF current is plotted against the different high-k gate oxide material values are shown in Fig. 2b. It is clear that ION/IOFF ratio increases by 33% with increasing k value. This ratio should be high for the proper switching of the devices. Since the DM-FinFET with ZrO2 has a large ratio, the device switches between the OFF state and the ON state quickly. Here even TiO2 has the lowest value; it is not useful because of lower band gap thereby increasing the leakage. For logic applications, DIBL plays an important role as device dimensions are scaled rigorously. The DIBL co-efficient was computed as:
DIBL ¼
V t;lin V t;sat V dd V t;lin
ð2Þ
where Vt,lin and Vt,sat are the threshold voltages measured at linear and saturation region for drain voltages of 0.1 V and 1.2 V respectively. The supply voltage of 1.2 V was taken as per the conventions of ITRS 2010 for 45 nm gate length in regard of logic applications. From Fig. 2b, DIBL shows exponential decrease of 75% with increase in high-k value DM FinFET.
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The surface potential along the channel length for DM n-channel FinFETs is shown in Fig. 2c for various high-k values. In this figure, the position along the channel is plotted in the x-axis direction and the DM FinFETs devices show a step potential profile at the interface of the two metals along the channel. It is clearly visible that the DM FinFET technology provides a larger increase of potential, thereby improving DIBL characteristics. The step increase of surface potential in the case of the DM FinFET devices results in an additional electric field peak at the interface along with the existing peak at the drain end. These additional peaks due to gate engineering techniques reduce the effective field at the drain end, resulting in smaller DIBL and hot-carrier effects, which are the major effects in the case of the short-channel devices. The lateral electric field is high for the k value of 3.9 which corresponds to SiO2.The lateral electric field profile at the surface is shown in Fig. 2d, for different high-k dielectric materials. For DM FinFET devices, the electric field discontinuity at the interface of two gate metals causes channel field flattening, which results in a larger average velocity when the electrons enter the channel from the source. The electron velocity profile at the surface is shown in Fig. 3a, for different high-k dielectrics. 3.2. Analog performance The different analog performance parameters studied in this section are the transconductance (gm), transconductance genera-
Fig. 2. (a) Comparison of OFF current and ON current DM-FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V. (b) Comparison of ION/IOFF and DIBL for Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V. (c) Comparison of electrostatic surface potential along the channel in Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V. (d) Comparison of electron mobility variation along the channel in Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V.
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tion factor (gm/Id) and output resistance (Ro). Fig. 3b shows the variation of transconductance with normalized drain current at a drain bias of 1.2 V for various gate to source voltages. The DM FinFET device shows an improved drain current and a 3% increase in transconductance in strong inversion as the high-k dielectric value is increased. The improvement in peak gm in DM DG MOSFET can be attributed to the improved charge control by the top and bottom gates in the devices [14,15]. Another parameter examined is the transconductance generation factor (TGF) or gm/Id ratio. It is clear from Fig. 3c that the transconductance generation factor is maximum for TiO2 and minimum for SiO2 for different gate to source voltages. So the circuits based on subthreshold operation of devices are expected to provide a higher gain.
The output resistance, Ro of a MOS transistor was evaluated as
Ro ¼ V A =ID
ð3Þ
where VA and ID are early voltage and saturated drain current. Gate engineering device with TiO2 shows a higher output resistance. Such an improvement is due to the fact that the region of the channel under metal M2 provides a shielding effect such that the channel region under M1 is not affected by drain to source voltage variations. The output resistance variation of the DM FinFET device for different high-k material is shown in Fig. 3d. It is clear that TiO2 which corresponds to dielectric constant of 40 has a maximum output resistance of 220 MX whereas SiO2 has a minimum output resistance of 2 MX. Thus the output resistance increases as the
Fig. 3. (a) Comparison of lateral electric field along the channel in Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V. (b) Comparison of variation of drain current and transconductance in Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V. (c) Comparison of TGF for the Dual Material n-channel FinFETs with different high-k materials as a function of Vgs = 0.15 V. (d) Comparison of output resistance and intrinsic gain for Dual Material n-channel FinFETs with different high-k materials function of Vds = 0.6 V and Vgs = 0.15 V.
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D. Nirmal et al. / Microelectronics Reliability 53 (2013) 499–504 Table 1 Comparison of Cgd, Cgs, Cgg and gain of DM-FinFETs for different gate dielectric materials. Dielectric constant
Dielectric material
Gate to drain capacitance, Cgd (fF)
Gate to source capacitance, Cgs (fF)
Total gate capacitance, Cgg, (fF)
Voltage gain (V/v)
k = 3.9 k = 7.5 k = 10 k = 15 k = 25 k = 40
SiO2 Si3N1 Al2O3 LaAlO3 HfO2/ZrO2 TiO2
1 1.5 1.75 2.5 3.75 5.5
0.53 0.565 0.58 0.6 0.625 0.645
1.5 2.1 2.5 3.1 4.3 6
0.7115 0.7337 0.8111 0.8288 0.8348 0.8401
Fig. 4. (a) A high gain CMOS inverting amplifier. (b) Comparison of voltage transfer characteristics of CMOS inverter with DM n-channel FinFETs with different high-k materials as a function of Vds = 0.6 V.
dielectric constant value of gate oxide material increases. So this device should be applicable for feedback and cascade amplifiers. The gate-engineered FinFET device with an undoped body does not suffer from any mobility degradation issue, thereby exhibiting an increased gain in both the weak and strong inversion regimes. The intrinsic gain which is product of transconductance and output impedance is shown in Fig. 3d it is clear that intrinsic gain is minimum for SiO2. The intrinsic gate capacitances represent an important parameter in the case of RF applications. The intrinsic gate capacitances in the DM-FinFETs are gate to- source (Cgs), gate-todrain capacitances (Cgd). Table 1 shows the values of Cgs, Cgd and Cgg of the DM-FinFET for various dielectric constant values. The Cgs, Cgd and Cgg increases with dielectric thereby reducing the leakage current and increasing the gate control. The electron density at the source end is considerably less compared with that at the drain end in the case of the DM FinFET devices. This is due to the fact that the channel at the source side has a higher threshold voltage due to the higher work function material at the source side. The larger values of Cgd in the case of the DM FinFETs result from capacitance coupling between drain and gate electrodes.
3.3. Circuit applications The circuit performance of DM-FinFET was analyzed by investigating the gain of a simple push pull CMOS inverting amplifier. Fig. 4a shows a high gain CMOS inverting amplifier. The width of the p-channel device (Wp) is chosen three times the width of the
n-channel device (Wn) to match the subthreshold current of both the devices. The voltage transfer characteristics of the CMOS inverter with DM n channel FinFET with different dielectric constant values is shown in Fig. 4b, so here it is proved that the integration of high-k dielectrics improves the performance of the circuit. 4. Conclusion In this paper, we have clearly analyzed the influence of gate engineering on the performance of FinFET for different high-k dielectrics. A proper trading of Fin width, Fin doping and gate work function improves short channel effects. The performance of an inverter with different high-k dielectrics is also illustrated by using the DMFinFET architecture. Conventional SiO2 gate dielectric material was compared with different high-k dielectrics in the device and better performance was observed. However from the analysis, the ZrO2 based dielectric material was found to be the best alternative for SiO2 because TiO2 has a band gap of 3 eV which is not favorable for switching purposes. The gate capacitance of the device increases by 65%, ION/IOFF ratio increases by 33% and leakage current decreases by 70% as the gate dielectric material of the device is changed from SiO2 to ZrO2. The DM-FinFET device shows an improved drain current and a 3% increase in transconductance. DIBL shows exponential decrease of 75% in the ZrO2 based device over conventional device. The integration of high-k dielectrics in the DM-FinFET enhances the device performance to a great extend
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and it makes the device one of the promising candidates for future semiconductor devices. The DM-FinFET with nanosized ZrO2 as gate dielectric improves the overall performance of the device as well as circuit and they can be used for low power applications. As a result, DM-FinFET with ZrO2 as gate dielectric can be considered as a promising device for future semiconductor industry. With the CMOS processing technology already reached less than 100-nm regime, fabricating DM FinFET devices should not be too complicated in future. Thus, for thin-film silicon-on-insulator or FinFET devices, the gate work function engineering such as the DM FinFET technology is the most favorable technique for low-power sub threshold analog applications. References [1] Nirmal D, Nalini B, Vijayakumar P. Nanosized high k dielectric material for FinFET. Integr Ferroelectrics 2010;121(1):31–5. [2] Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP. Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 2001;89(3):259–88. [3] Colinge JP. Multiple-gate SOI MOSFETs. Solid State Electron 2004; 48(6):897–905. [4] Nirmal D, Thomas Divya Mary, Shruti K, Samuel Patrick Chella, Vijaya Kumar P, Mohan Kumar N. Impact of gate engineering on double gate MOSFETs using high-k dielectrics. In: Proceedings of the 3rd international conference on electronics computer technology, vol. 1, 2011. p. 31–4. [5] Mohan Kumar N, Binit Syamal, Sarkar CK. Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications. Microelectron Reliab 2009;49(12):1491–7. [6] Chakraborty S, Mallik A, Sarkar CK, Ramgopal Rao V. Impact of halo doping on the subthreshold performance of deep-sub micrometer CMOS devices and
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