- Email: [email protected]
Simulation Analysis of Hafnium-based-Oxide and Effects of Metallization on Electrical Performance of Gate-All-Around Finfet Devices
Available online at www.sciencedirect.com
ScienceDirect Procedia Materials Science 11 (2015) 444 – 448
5th International Biennial Conference on Ultrafine Grained and Nanostructured Materials, UFGNSM15
Simulation Analysis of Hafnium-Based-Oxide and Effects of Metallization on Electrical Performance of Gate-All-Around Finfet Devices M. Salamia, M.H. Shahrokh Abadia,* a
Faculty of Electrical and Computer Engineering, Hakim Sabzevari University, Sabzevar 9617976487, Iran
Abstract Simulation analysis, using Atlas Silvaco® has been performed to determine the effect of gate oxide and type of the metallization on the electrical performance of a Si-channel lightly doped n-type gate-all-around FinFET (n–-GAA-FinFET). The oxide of the gate (GOX) was developed using hafnium dioxide (HfO2) and hafnium silicon oxide (HfSiO4) to investigate the effects of short channel and the switching parameters of the device. The simulation results are shown that the HfO 2 can significantly increase the ON-state current and the threshold voltage of the device compared to the conventional oxides. Furthermore, it was observed that the material with work function lower than the customary metallization, such as Ag, Ta, Mo, and Ti as the gate contact metallization, can further increase the ON-state current, and simultaneously, can lower the threshold voltage of the device. The results also show a remarkable improvement into the logarithmic ratio of the On-state to the OFF-state currents of the device in order of 12 using the metal/HfSiO4/HfO2 gate stack. © 2015 2015Published The Authors. Published Elsevier Ltd. by Elsevier Ltd. by This is an open access article under the CC BY-NC-ND license Peer-review under responsibility of the organizing committee of UFGNSM15. (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the organizing committee of UFGNSM15 Keywords: Short channel effects; Gate-all-around FinFET; Gate stack material and high-k material.
1. Introduction Multiple-gates metal-oxide-semiconductor transistors have been developed from classical, planar, and single gate devices into three dimensional devices to modulate the current in the channel and decrease short-channel effects
* Corresponding author. Tel.: +98-51-44012826; fax: +98-51-4402823. E-mail address: [email protected]
2211-8128 © 2015 Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the organizing committee of UFGNSM15 doi:10.1016/j.mspro.2015.11.037
M. Salami and M.H. Shahrokh Abadi / Procedia Materials Science 11 (2015) 444 – 448
(SCEs), Ritzenthaler et al. (2011), Moreau et al. (2011). Furthermore, with increasing the number of gates, the number of transistors in the circuit will be reduced in contrast with the conventional CMOS implementations, Wang et al. (2015). Studies have shown that among the multi-gate FETs (MuG-FETs), the FinFET structures are suitable candidates for the continually scaling CMOS due to the unique ability to increase ON-state current, Im et al. (2014), Ferain et al. (2011) and to reduce leakage current, Hu et al. (2013), Liu et al. (2013) which led to improve the switching capability of FinFETs by degrading the subthreshold-slope (SS) parameter, Wei et al. (2015). In the nanoscale devices, the threshold voltage (VTH) adjustment becomes an emergency problem in the design of the integrated circuits owing to use scaled transistors and the material and the structural engineering can help to improve this issue, Li et al. (2013), Nawaz et al. (2014), Del Alamo (2011). In this paper a simulated model of gate-all-around FinFET (n–-GAA-FinFET) is investigated and the influence of the gate contact material as well as the gate oxide material on the threshold voltage and the ON and OFF-state currents are studied. Finely, a model consist of metal/spacer/high-k oxide gate stack is studied and its properties are calculated. 2. Device structure The structure of the GAA-FinFET with n+ipin+ doping distribution has been given in fig. 1. The device consists of the silicon fin with the rectangular cross-sectional shape which forms the channel region and connects to the source and drain regions at each end. The channel charge is electrostatically controlled by the biased electrodes of the gate stack wrapped around the fin and then the inversion current flows through the channel from the drain to the source by the drain-source voltage (VDS). All simulations are carried out using Atlas Silvaco simulator. Assuming high and uniform doping concentrations, Band gap narrowing (BGN) and auger recombination models are included in the simulations. Because of presence of high impurity atom in the channel and also consideration of an interface trap (or defect) effect, Shockley-Read-Hall (SRH) model is also used. The mobility model includes both concentration and parallel electric field Dependence. Table 1 shows the parameters of the device that have been used during this study.
Fig. 1. The structural model of the n–-GAA-FinFET. Table 1. Parameters used for simulated FinFET. Parameters Gate length (Lgate) Fin length (L) Distance between gate sidewall and source/drain contacts Fin height (Hfin) Fin width (Wfin) Doping concentration of channel (p-type) Doping concentration of source and drain(n-type) Oxide and Spacer thickness (tox)
Value 30 (nm) 0.12 (µm) 25 (nm) 14 (nm) 14 (nm) 1016 (cm-3) 1020 (cm-3) 1 (nm)
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M. Salami and M.H. Shahrokh Abadi / Procedia Materials Science 11 (2015) 444 – 448
3. Results and discussions 3.1. Effect of gate oxide Figure 2 shows the ID–VGS characteristics for the SiO2, HfO2 and HfSiO4 as the gate oxides. From this figure, it can be seen that the ON-state current, using only the HfO2 gate oxide, shows higher values for all values of VGS, in compared to SiO2 and HfSiO4. Furthermore, a decrement in the threshold voltage can be seen due to increasing the dielectric constant of the gate oxide, as a result of existence of a higher gate capacitance. Thus, the coupling between the gate and the channel is improved, causes to increase the inversion charge density and to decrease the VTH, resulting in the higher drain current.
Fig. 2. ID–VGS characteristics of GAA-FinFET for different gate oxides.
3.2. Effect of work function (WF) Recently, studies in the metal gate CMOS technology has led to replacement of conventional poly-Si gate electrodes with metals due to being free from gate depletion effects, Lee et al. (2006), G´amiz et al. (2003), Thomas (2011). According to this, the role of some novel metals, having different workfunctions, has been investigated in here. Fig. 3 shows the ID–VGS characteristics for different WFs from 4.3 eV to 5.1 eV (corresponded to metals such as Ag, Ti, Mo, Pt and Ta). It can be observed that the magnitude of the ON-state current increases with decreasing the WF while the VTH decreases. This can be explained due to that the ID and the VTH are functions of the inversion charges, depended to the flat-band voltage which is the difference between the WFs of the gate electrode and the channel; in which ID and VTH are indirectly and directly related to the flat-band voltage, respectively. Also, the results show that the OFF-state current significantly increases when the WF is reduced, translated into decreasing the ratio of ION/IOFF.
M. Salami and M.H. Shahrokh Abadi / Procedia Materials Science 11 (2015) 444 – 448
Fig. 3. ID–VGS characteristics of GAA-FinFET for different work function of gate contact.
3.3. Effect of spacer layer In the FinFET fabrication technology, to protect the channel in the process and to avoid defects at the dielectric/channel interface, a spacer layer is added between the oxide and channel. Referring to this issue, the effect of this extra layer, added to the gate stack, on the performance of the device is studied. Figure 4 shows the drain current versus VGS for the high-k oxide/spacer/metal gate stack with the different materials. From the figure, the HfSiO4/HfO2 gate stack shows the maximum ON-state current while the gate stack without the spacer shows the minimum value, simultaneously, the VTH is nearly the same for the all structures. Furthermore, the maximum ION/IOFF ratio (0.71×1012) is achieved for the HfSiO4/HfO2 gate stack, showing that, the FinFET with the spacer film can have more efficient switching performance than the device without the spacer.
Fig. 4. ID–VGS characteristics of GAA-FinFET for gate stack with and with spacer layer as a function of different oxide materials.
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M. Salami and M.H. Shahrokh Abadi / Procedia Materials Science 11 (2015) 444 – 448
4. Summary The results show that the work function (WF) of the gate contact is the main parameter for the determination of the device performance. The reducing WF leads to increase the ON-state current while the threshold voltage degrades and the OFF-state current increases. Thus, making an optimum decision of the WF is a tradeoff to achieve an efficient performance. Furthermore, using gate oxides such as the Hf-based ones can be promising candidates for the high-k dielectrics due to improvement the coupling between the gate oxide and the channel. It was observed that the GAA-FinFET with the gate stack consists of metal/spacer/high-k oxide exhibits superior OFF-state performances in terms of the leakage current (in order of 10-18A) and very high logarithmic ION/IOFF ratio (in order of 12).
References Del Alamo, J.A., 2011. Nanometre-scale electronics with III–V compound semiconductors. Journal of Nature 479, 317-323. Ferain, I., Colinge, C.A., Colinge, J.P., 2011. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Journal of Nature 479, 310-316. G´amiz, F., Godoy, A., Rold´an, J.B., Carceller, J.E., Cartujo, P., 2003. Effect of polysilicon depletion charge on electron mobility in ultrathin oxide MOSFETs. Journal of Semiconductor Science and Technology 18, 927–937. Hu, V.P.H., Fan, M.L., Su, P., Chuang, C.T., 2013. Comparative leakage analysis of GeOI FinFET and Ge bulk FinFET. IEEE Transactions Electron Devices 60, 3596 – 3600. Im, K.S., Kang, H.S, Lee, J.H., Chang, S.J., Cristoloveanu, S., Bawedin, M., Lee, J.H., 2014. Characteristics of GaN and AlGaN/GaN FinFETs. Journal of Solid-State Electronics 97, 66–75. Lee, B. H., Oh, J.H., Tseng, H., Jammy, R., Huff, H., 2006. Gate stack technology for nanoscale devices. Journal of Materials Today, 9, 32-40. Li, Y., Su, H.W., Chen, Y.Y., Hsu, S.C., Huang, W.T., 2013. The intrinsic parameter fluctuation on high-j/metal gate bulk FinFET devices. Journal of Microelectronic Engineering 109, 302–305. Liu, X., Wu, M., Jin, X., Chuai, R., Lee, J.H., Lee, J.H., 2013. The optimal design of 15 nm gate-length junctionless SOI FinFETs for reducing leakage current. Journal of Semiconductor Science and Technology 28, 105013-18. Moreau, M., Munteanu, D., Autran, J.L., 2011. Simulation study of Short-Channel Effects and quantum confinement in double-gate FinFET devices with high-mobility materials. Journal of Microelectronic Engineering 88, 366–369. Nawaz, S.M., Dutta, S., Chattopadhyay, A., Mallik, A., 2014. Comparison of random dopant and Gate-Metal workfunction variability between junctionless and conventional FinFETs. Journal of Electron Device Letters 35, 663 – 665. Ritzenthaler, R., Lime, F., Faynot, O., Cristoloveanu, S., Iñiguez, B., 2011. 3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors. Journal of Solid-State Electronics 65, 94–102. Thomas, S.M., 2011. Electrical characterisation of novel silicon MOSFETs and finFETs, PhD thesis, University of Warwick. Wang, G., Abedin, A., Moeen, M., Kolahdouz, M., Luo, J., Guo, Y., 2015. Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology. Journal of Solid-State Electronics 103, 222–228. Wei, X., Zhong, J., Luo, J., Wu, H., Zhu, H., Zhao, C., Yin, H., 2015. FinFETs using reverse substrate layer with improved gate capacitance characteristics for subthreshold application. Journal of Solid-State Electronics 104, 116–121.
ScienceDirect Procedia Materials Science 11 (2015) 444 – 448
5th International Biennial Conference on Ultrafine Grained and Nanostructured Materials, UFGNSM15
Simulation Analysis of Hafnium-Based-Oxide and Effects of Metallization on Electrical Performance of Gate-All-Around Finfet Devices M. Salamia, M.H. Shahrokh Abadia,* a
Faculty of Electrical and Computer Engineering, Hakim Sabzevari University, Sabzevar 9617976487, Iran
Abstract Simulation analysis, using Atlas Silvaco® has been performed to determine the effect of gate oxide and type of the metallization on the electrical performance of a Si-channel lightly doped n-type gate-all-around FinFET (n–-GAA-FinFET). The oxide of the gate (GOX) was developed using hafnium dioxide (HfO2) and hafnium silicon oxide (HfSiO4) to investigate the effects of short channel and the switching parameters of the device. The simulation results are shown that the HfO 2 can significantly increase the ON-state current and the threshold voltage of the device compared to the conventional oxides. Furthermore, it was observed that the material with work function lower than the customary metallization, such as Ag, Ta, Mo, and Ti as the gate contact metallization, can further increase the ON-state current, and simultaneously, can lower the threshold voltage of the device. The results also show a remarkable improvement into the logarithmic ratio of the On-state to the OFF-state currents of the device in order of 12 using the metal/HfSiO4/HfO2 gate stack. © 2015 2015Published The Authors. Published Elsevier Ltd. by Elsevier Ltd. by This is an open access article under the CC BY-NC-ND license Peer-review under responsibility of the organizing committee of UFGNSM15. (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the organizing committee of UFGNSM15 Keywords: Short channel effects; Gate-all-around FinFET; Gate stack material and high-k material.
1. Introduction Multiple-gates metal-oxide-semiconductor transistors have been developed from classical, planar, and single gate devices into three dimensional devices to modulate the current in the channel and decrease short-channel effects
* Corresponding author. Tel.: +98-51-44012826; fax: +98-51-4402823. E-mail address: [email protected]
2211-8128 © 2015 Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the organizing committee of UFGNSM15 doi:10.1016/j.mspro.2015.11.037
M. Salami and M.H. Shahrokh Abadi / Procedia Materials Science 11 (2015) 444 – 448
(SCEs), Ritzenthaler et al. (2011), Moreau et al. (2011). Furthermore, with increasing the number of gates, the number of transistors in the circuit will be reduced in contrast with the conventional CMOS implementations, Wang et al. (2015). Studies have shown that among the multi-gate FETs (MuG-FETs), the FinFET structures are suitable candidates for the continually scaling CMOS due to the unique ability to increase ON-state current, Im et al. (2014), Ferain et al. (2011) and to reduce leakage current, Hu et al. (2013), Liu et al. (2013) which led to improve the switching capability of FinFETs by degrading the subthreshold-slope (SS) parameter, Wei et al. (2015). In the nanoscale devices, the threshold voltage (VTH) adjustment becomes an emergency problem in the design of the integrated circuits owing to use scaled transistors and the material and the structural engineering can help to improve this issue, Li et al. (2013), Nawaz et al. (2014), Del Alamo (2011). In this paper a simulated model of gate-all-around FinFET (n–-GAA-FinFET) is investigated and the influence of the gate contact material as well as the gate oxide material on the threshold voltage and the ON and OFF-state currents are studied. Finely, a model consist of metal/spacer/high-k oxide gate stack is studied and its properties are calculated. 2. Device structure The structure of the GAA-FinFET with n+ipin+ doping distribution has been given in fig. 1. The device consists of the silicon fin with the rectangular cross-sectional shape which forms the channel region and connects to the source and drain regions at each end. The channel charge is electrostatically controlled by the biased electrodes of the gate stack wrapped around the fin and then the inversion current flows through the channel from the drain to the source by the drain-source voltage (VDS). All simulations are carried out using Atlas Silvaco simulator. Assuming high and uniform doping concentrations, Band gap narrowing (BGN) and auger recombination models are included in the simulations. Because of presence of high impurity atom in the channel and also consideration of an interface trap (or defect) effect, Shockley-Read-Hall (SRH) model is also used. The mobility model includes both concentration and parallel electric field Dependence. Table 1 shows the parameters of the device that have been used during this study.
Fig. 1. The structural model of the n–-GAA-FinFET. Table 1. Parameters used for simulated FinFET. Parameters Gate length (Lgate) Fin length (L) Distance between gate sidewall and source/drain contacts Fin height (Hfin) Fin width (Wfin) Doping concentration of channel (p-type) Doping concentration of source and drain(n-type) Oxide and Spacer thickness (tox)
Value 30 (nm) 0.12 (µm) 25 (nm) 14 (nm) 14 (nm) 1016 (cm-3) 1020 (cm-3) 1 (nm)
445
446
M. Salami and M.H. Shahrokh Abadi / Procedia Materials Science 11 (2015) 444 – 448
3. Results and discussions 3.1. Effect of gate oxide Figure 2 shows the ID–VGS characteristics for the SiO2, HfO2 and HfSiO4 as the gate oxides. From this figure, it can be seen that the ON-state current, using only the HfO2 gate oxide, shows higher values for all values of VGS, in compared to SiO2 and HfSiO4. Furthermore, a decrement in the threshold voltage can be seen due to increasing the dielectric constant of the gate oxide, as a result of existence of a higher gate capacitance. Thus, the coupling between the gate and the channel is improved, causes to increase the inversion charge density and to decrease the VTH, resulting in the higher drain current.
Fig. 2. ID–VGS characteristics of GAA-FinFET for different gate oxides.
3.2. Effect of work function (WF) Recently, studies in the metal gate CMOS technology has led to replacement of conventional poly-Si gate electrodes with metals due to being free from gate depletion effects, Lee et al. (2006), G´amiz et al. (2003), Thomas (2011). According to this, the role of some novel metals, having different workfunctions, has been investigated in here. Fig. 3 shows the ID–VGS characteristics for different WFs from 4.3 eV to 5.1 eV (corresponded to metals such as Ag, Ti, Mo, Pt and Ta). It can be observed that the magnitude of the ON-state current increases with decreasing the WF while the VTH decreases. This can be explained due to that the ID and the VTH are functions of the inversion charges, depended to the flat-band voltage which is the difference between the WFs of the gate electrode and the channel; in which ID and VTH are indirectly and directly related to the flat-band voltage, respectively. Also, the results show that the OFF-state current significantly increases when the WF is reduced, translated into decreasing the ratio of ION/IOFF.
M. Salami and M.H. Shahrokh Abadi / Procedia Materials Science 11 (2015) 444 – 448
Fig. 3. ID–VGS characteristics of GAA-FinFET for different work function of gate contact.
3.3. Effect of spacer layer In the FinFET fabrication technology, to protect the channel in the process and to avoid defects at the dielectric/channel interface, a spacer layer is added between the oxide and channel. Referring to this issue, the effect of this extra layer, added to the gate stack, on the performance of the device is studied. Figure 4 shows the drain current versus VGS for the high-k oxide/spacer/metal gate stack with the different materials. From the figure, the HfSiO4/HfO2 gate stack shows the maximum ON-state current while the gate stack without the spacer shows the minimum value, simultaneously, the VTH is nearly the same for the all structures. Furthermore, the maximum ION/IOFF ratio (0.71×1012) is achieved for the HfSiO4/HfO2 gate stack, showing that, the FinFET with the spacer film can have more efficient switching performance than the device without the spacer.
Fig. 4. ID–VGS characteristics of GAA-FinFET for gate stack with and with spacer layer as a function of different oxide materials.
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M. Salami and M.H. Shahrokh Abadi / Procedia Materials Science 11 (2015) 444 – 448
4. Summary The results show that the work function (WF) of the gate contact is the main parameter for the determination of the device performance. The reducing WF leads to increase the ON-state current while the threshold voltage degrades and the OFF-state current increases. Thus, making an optimum decision of the WF is a tradeoff to achieve an efficient performance. Furthermore, using gate oxides such as the Hf-based ones can be promising candidates for the high-k dielectrics due to improvement the coupling between the gate oxide and the channel. It was observed that the GAA-FinFET with the gate stack consists of metal/spacer/high-k oxide exhibits superior OFF-state performances in terms of the leakage current (in order of 10-18A) and very high logarithmic ION/IOFF ratio (in order of 12).
References Del Alamo, J.A., 2011. Nanometre-scale electronics with III–V compound semiconductors. Journal of Nature 479, 317-323. Ferain, I., Colinge, C.A., Colinge, J.P., 2011. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Journal of Nature 479, 310-316. G´amiz, F., Godoy, A., Rold´an, J.B., Carceller, J.E., Cartujo, P., 2003. Effect of polysilicon depletion charge on electron mobility in ultrathin oxide MOSFETs. Journal of Semiconductor Science and Technology 18, 927–937. Hu, V.P.H., Fan, M.L., Su, P., Chuang, C.T., 2013. Comparative leakage analysis of GeOI FinFET and Ge bulk FinFET. IEEE Transactions Electron Devices 60, 3596 – 3600. Im, K.S., Kang, H.S, Lee, J.H., Chang, S.J., Cristoloveanu, S., Bawedin, M., Lee, J.H., 2014. Characteristics of GaN and AlGaN/GaN FinFETs. Journal of Solid-State Electronics 97, 66–75. Lee, B. H., Oh, J.H., Tseng, H., Jammy, R., Huff, H., 2006. Gate stack technology for nanoscale devices. Journal of Materials Today, 9, 32-40. Li, Y., Su, H.W., Chen, Y.Y., Hsu, S.C., Huang, W.T., 2013. The intrinsic parameter fluctuation on high-j/metal gate bulk FinFET devices. Journal of Microelectronic Engineering 109, 302–305. Liu, X., Wu, M., Jin, X., Chuai, R., Lee, J.H., Lee, J.H., 2013. The optimal design of 15 nm gate-length junctionless SOI FinFETs for reducing leakage current. Journal of Semiconductor Science and Technology 28, 105013-18. Moreau, M., Munteanu, D., Autran, J.L., 2011. Simulation study of Short-Channel Effects and quantum confinement in double-gate FinFET devices with high-mobility materials. Journal of Microelectronic Engineering 88, 366–369. Nawaz, S.M., Dutta, S., Chattopadhyay, A., Mallik, A., 2014. Comparison of random dopant and Gate-Metal workfunction variability between junctionless and conventional FinFETs. Journal of Electron Device Letters 35, 663 – 665. Ritzenthaler, R., Lime, F., Faynot, O., Cristoloveanu, S., Iñiguez, B., 2011. 3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors. Journal of Solid-State Electronics 65, 94–102. Thomas, S.M., 2011. Electrical characterisation of novel silicon MOSFETs and finFETs, PhD thesis, University of Warwick. Wang, G., Abedin, A., Moeen, M., Kolahdouz, M., Luo, J., Guo, Y., 2015. Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology. Journal of Solid-State Electronics 103, 222–228. Wei, X., Zhong, J., Luo, J., Wu, H., Zhu, H., Zhao, C., Yin, H., 2015. FinFETs using reverse substrate layer with improved gate capacitance characteristics for subthreshold application. Journal of Solid-State Electronics 104, 116–121.