- Email: [email protected]
Automatic determination of signal flow through MOS transistor networks
53
INTEGRATION
Letter
Automatic determination of signal flow through MOS transistor networks W.F. Clocksin and M.E. Leeser Computer Laboratory,
University of Cambridge,
Cambridge
CB2 3QG, United Kingdom
Received 20 September
Abstract. We describe a method for automatically determining the signal flow through hierarchically specified MOS transistor nets. Direction is determined from the circuit schematic only; no knowledge of signal values or input/output relations is assumed, and particular design rules are not relied on. Unlike previous methods used for MOS transistor nets, our method does not require some transistors to be determined manually, and the method can deal with bidirectional transistors. Circuits are represented using Horn clauses as a hierarchical specification language, and the method is implemented in Prolog. We point out some interesting connections with the statistical thermodynamics of spin systems.
Keywords.
Logic programming,
circuit specification,
design automation.
1. Introduction
Signal flow may be viewed at a digital level as the propagation of logic levels through a network. Thus, power and ground connections are viewed as sourcesof signal flow. Similarly, inputs to a module and outputs from a module are sources and sinks of signal flow, respectively.Note the difference between signal flow and the more traditional view of current flow where power acts as a source of current flow and ground acts as a sink. For example, consider the CMOS inverter in Fig. 1. The dotted arrows show the direction of current flow through the transistors; the solid arrows show the direction of signal flow. Using the definition of signal flow we can derive the input node and output node of the inverter, and this will be shown later. North-Holland INTEGRATION,
the VLSI journal
0167-9260/86/$3.50
0 1986, Elsevier
4 (1986) 53-63 Science
Publishers
B.V. (North-Holland)
54
IV. F. Clocksitr. M. E. Leeser / A utotttatic detertttitratiott
of MOS signal flobc
Fig. 1.
Determining the signal flow through transistors is often a necessary precursor before further circuit analysis can be carried out. For example, both Crystal [ll] and TV [S] require flow analysis before they can proceed with timing analysis. Formal methods for circuit verification [l] and design simplification [4] depend on signal flow being specified in advance. Some design verification methods do not require a preliminary flow analysis, but proofs are easier to compute if the results of flow analysis are available [6]. One way to provide signal flow information is manually. by specifying the input and output roles of components’ ports. Some systems [l,ll] rely on manual specifications entirely. However, automatic signal flow determination can reduce the designer’s workload, particu-
William Clocksin is an Assistant Director of Research at the Computer Laboratory, University of Cambridge. From 1976 to 1980 he carried out postgraduate research at the Department of Artificial Intelligence, University of Edinburgh. in the areas of computer vision and implementation of high level programming languages, particularly Prolog, LISP, and POP-2. From 1980 to 1982 he was at Oxford University, where as GEC Fellow in Robotics he participated in a project that developed a visually-guided robot for welding thin sheet steel assemblies. Since joining the Computer Laboratory in 1983 he has concentrated on the use of standard and non-standard inference in problem solving with applications in design automation, and on high-performance implementations of Prolog. the BSI working group on Prolog Standardization, and is on the editorial turttal of Logic Prograttmittg.
Miriam Leeser received the B.S. degree in Electrical Engineering from Cornell University in 19SO. From 1980 to 1983 she worked in the network products group of Codex Corporation in Mansfield, Massachusetts designing multiprocessor architectures. She received the Diploma in Computer Science from Cambridge University in 1984, where she is pursuing her PhD degree. Her interests include VLSI design, Prolog. and temporal logic. She is currently investigating the use of temporal logic descriptions of circuits in hardware verification.
W. F. Clocksin, M. E. Leeser / Automatic
determination
of MOS signal flow
55
larly for the caseof MOS transistors, which, due to the symmetry of source and drain channels, are capable of conducting in different directions at different times. TV [8] automatically determines signal flow in nMOS transistor nets free of bidirectional transistors and specification errors. TV uses nine rules to determine the direction of transistors. In addition to the general Kirchoff current law, TV uses information about k-ratio rules for inverters as well as other information about the types of circuits used in the design methodology. The method described in this paper is intended for hierarchically specified MOS transistor nets that contain bidirectional transistors, and where there is no information about any particular design methodology. In addition we assume no knowledge about the specific layout. This prevents the use of, for example, the inverter k-ratio rule. Our method is data independent; it does not use knowledge of the values of inputs to a circuit. The analysis is static; its is only dependent on the circuit topology. In essencewe are determining the flow of information through a net assuming all transistors are turned on. Although it is unlikely that this configuration will occur in practice, we are able to determine those transistors whose direction will always remain the same. Transistors which can support signal flow in either direction are labelled bidirectional. Clearly we label some transistors bidirectional which, due to the inputs provided, will only propagate signals in one direction in practice. However, the algorithm guarantees to correctly find all bidirectional transistors, and will not incorrectly label any unidirectional transistor. This procedure will be able to determine the direction of a large percentageof transistors in most circuits. It will not provide much useful information about a design that relies heavily on bidirectional transistors; however, such designs are unusual. An initial implementation was based on TV, except that only four rules were used. Three of the rules were based on TV’s rules, and a new fourth rule was responsible for dealing with transistors whose direction was determined by case analysis if all else failed. While considering the fourth rule it was realised that this rule encompassedmost of the other rules. Our current method, discussed below, uses one rule to determine the directions of transistors. It emergesthat the rules used by TV can be viewed as caseanalysis with the constraint that all nodes have at least one sink and one source of signal flow. 2. Definitions
The input to the direction finder is a circuit specification. We use Prolog [2] as a specification language using a technique described in detail elsewhere [3]. A circuit is composed of a collection of modules and connections between modules. With each module is associated a set of ports between which connections are specified. Ports may be sinks or sources of signal flow or they may be both. Modules can be composed hierarchically, with modules specified in terms of other module specifications. At the bottom of the hierarchy are found primitive modules, the exact form of which depends on the technology being used. In this
W.F. Clocksin, ME. Leeser / Automatic determination of MOS signal flow
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b-4
(b)
0
Fig. 2.
paper we shall consider p- and n-transistors and power and ground supplies to be primitive. A circuit is representedas a set of Horn clauses in Edinburgh Prolog syntax. This notation directly expressesthe circuit topology and hierarchy. A module having n ports is represented by a predicate of arity n. A module may be specified as a Horn clause in which the head of the clause representsthe module to be defined, and the body of the clause is a composition of the sub-modules defining the module. The sub-modules are composed with the comma connective. Nodes, or junctions of connections, are represented by a unique like-named variable. The ‘:-’ connective of Prolog is reinterpreted to mean ‘is defined by’. The order of the modules in the body is not important. A node which is named by a variable not appearing in the head of the clause is said to be a hidden node. Nodes which are not hidden are called port nodes. For example, Fig. 2(a) depicts the module halfadd, composed of three gates with nodes named by variables as shown. Module halfadd is specified as: halfadd(A, B, S, C) :- xor(A, B, S), nand(A, B, I”), invert( T, C). The variable T defines the ‘hidden’ node between the output of the nand gate
W.F. Clocksin, M. E. Leeser / Automatic determination of MOS signal flow
51
and the input of the inverter. Figure 2(b) shows the definition of the nand gate in terms of primitive transistors and power and ground connections. A transistor is specified as trans( X, G, A, B), where X specifies the type of transistor (either p or n); G is the gate, and A and B are the two non-gate terminals. Module nand is specified as: nand(A, B, C):pwr(P), trans(p, B, P, C), trans(p, A, P, C), trans(n, A, C, T), trans(n, B, T, G), grid(G). The ports of the nand module do not have directions specified. In fact ports A and B are inputs, and port C is an output. Below we shall show that our method automatically infers port directions if they are not specified. 3. The method
The task of determining the direction of signal flow can be viewed as a consistent labelling problem [lo]. To solve the problem, it is necessary to associate with each transistor a label drawn from the set { right, left}. Refer to Fig. 3. If the two non-gate terminals of a transistor are arbitrarily named A and B, the label right is assigned to a transistor for which terminal A is a sink of signal flow and terminal B is a source of signal flow. The label left is assignedto a transistor for which terminal A is a source of signal flow and terminal B is a sink of signal flow. For a circuit consisting of n transistors, the number of unconstrained labellings is 2”. The problem is to assign labels to transistors such that a given constraint is satisfied. The constraint we use is that each node of a circuit must be connected to at least one sink and at least one source of signal flow. Moreover, if a node is directly connected to a power or ground, then at most one source of signal flow (the power or ground itself) is allowed. We shall call this constraint the Signal Law. The Signal Law is a consequenceof Kirchoff’s current law. For a circuit containing bidirectional transistors, multiple solutions are admitted. That is, there may be more than one possible labelling of a circuit that satisfies the Signal Law. A bidirectional transistor will be labelled right in one solution and left in another. It follows that the direction of port nodes (whether they are used as inputs or outputs) is an additional constraint on the solution. With our method there is a
A-B
A-B
>
< left Fig. 3.
right
58
W.F. Clocksin, M. E. Leeser / Automatic
determination
of MOS signal flow
choice of whether to attempt to derive the direction of port nodes automatically (at the risk of obtaining a weak solution), or to use a specified direction of port nodes to constrain the searchfor labellings of transistors. This is discussedbelow. 4. Implementation
The method is implemented in Prolog, using depth-first search through the hierarchical circuit specification to exhaustively enumerate the directions of transistors. The method compounds the direction finding of transistors with establishing the direction of nodes of non-primitive modules. Unlike previous approaches, the whole circuit is not ‘flattened’ into a set of primitive modules. First, the outermost module is decomposedinto its constituent modules, then the direction of the ports of each of these modules is established, and finally it is confirmed that the hidden nodes of the circuit obey the Signal Law. If a module is not primitive, then the direction of its ports is established recursively. The directions of ports of primitive modules, in this case n- and p-transistors, are determined as follows. Transistors have three ports: gate, source, and drain. A transistor’s gate terminal is always a sink of signal flow. If a transistor specified as a trans(n, A, B, C) is assignedthe label left, then B is its source and C is its drain. Similarly, if it is assignedthe label right then B is its drain and C is its source.A transistor sourceis a sourceof signal flow; its drain is a sink. Either the label left or the label right is assignedto a transistor. This is a nondeterministic choice which may be reversedsubsequently if it is found that the original choice leads to a violation of the Signal Law. Power and ground connections are always sourcesof signal flow. At any level of the hierarchy we can identify the set M of modules that comprises the immediately enclosing module. Labels taken from the set { in, out } are associatedwith each port of each module in M. The label in corresponds to the associatedport acting as a sourceof signal flow to a node outside the module; the label out correspondsto the port acting as a sink of signal flow. The labels of ports connecting to a given node are collected into a list associatedwith the node. A hidden node obeys the Signal Law if (a) its list contains at least one in and one out, and (b) if the node directly connects to a power or ground module, then it must contain only one irz. Only the hidden nodes of the enclosing module must satisfy the Signal Law; its ports are checked when the enclosing module itself becomes a sub-module of a larger circuit. If at any level of the hierarchy a node list does not satisfy the Sigrial Law, Prolog will automatically backtrack to find a direction of the sub-modules which satisfies the Signal Law. The effect of this procedure is to try both directions of all transistors until the Signal Law is satisfied. Further backtracking will find all possible solutions. Transistors whose directions are the same in all possible solutions are unidirectional, the remaining transistors are labelled bidirectional. When the procedure succeeds,each port of each module has an associatedlist of ins and 0~s. If all
W. F. Clocksin. h4. E. Leeser / Automatic
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elements on the list are ills, then the port is an output; if all elements on the list are outs then it is an input. Otherwise, it is bidirectional. In addition, the number of elements on the list is the number of primitive modules connected to that port. This information may be useful in subsequent analysis of the circuit where we wish to know the capacitive loading of a node. Note that the level of nesting of the hierarchy is arbitrary, and each module or submodule of a circuit may be specified at a different level. In the dynamic register example of the next section, the dynamic register is comprised of a combination of primitive transistors and non-primitive inverters. We can further exploit the hierarchy of the circuit specification using a technique described more fully elsewhere[4]. Once the directions of ports have been found for a type of submodule, the result can be stored in a library. This library would be consulted for each submodule when the procedure is invoked. Thus, direction setting only needs to be determined once for each type of submodule. In this context, trying both possible directions for all transistors in a circuit becomesreasonablefor circuits with very large numbers of transistors. For example, suppose we wish to include a CMOS inverter in our library. Running our procedure on the inverter circuit once will set the direction of both transistors and establish the input and output. This result will then be stored, and each additional time an inverter is discovered, the input and output nodes are looked up in the library. Instead of four possible labellings for each inverter submodule, only one is considered. The benefits become greater as our library and the complexity of the submodules contained in that library grow. 5. Examples
We will now show the result of applying this procedure to a few simple examples. These include a CMOS inverter, a dynamic register which illustrates submodules defined at different levels of hierarchy and the utility of a library, and a full adder which has bidirectional transistors. Example
1. A CMOS inverter (Fig. 1). This circuit is specified as:
invert(A, B) :- pwr( P), trans(p, A, P, B), grid(G), trans(n, A, B, G).
Fig. 4
60
W. F. Clocksin, 1’4.E. Leeser / Auromatic
determination
o/ MOS signal flow
Since any connection to power or ground is an input, it is clear that the n-transistor would be labelled right and the p-transistor would be labelled left. This correspondsto the arrows for signal flow shown in Fig. 1. The resulting node list for A is [A, out, out] telling us that A is the input to the module. Similarly, the resulting node list for B is [B, in, in] so B is the module’s output. Backtracking would not find further solutions. Example 2. A dynamic register (Fig. 4). This circuit is specified as: dreg(A, B, Load):trans(n, Load, A, X), invert( X, Y), invert( Y, B), trans(n, Z, B, X), invert( Load, Z). This simple module illustrates several key aspects of our approach. Internal connections such as nodes X, Y, and Z are hidden through use of Prolog variables. In addition, a module may combine submodules described at different levels of hierarchy; here we mix primitive and non-primitive elements. This example also illustrates the utility of a library of submodules. If the input and output of the inverter circuit were stored in a library, then only the direction of the two pass-transistors need be considered. Thus only four possible label assignments are investigated. From the method presented so far, it is impossible to ascertain a unique direction for the two pass-transistors. There are three ways to deal with this problem. One is to leave the direction specified as bidirectional until the register is used in an enclosing module. Another is to use specifications of the directions of ports. For example, in the dreg module, the specification that A is an input leads to the solution of the direction of the transistor directly connected to it. However, the specification that B is an output does not imply a single direction for the other transistor. Another approach is to incorporate a rule used by TV. This rule recognizesthat two transistors whose gates are the complements of one another and who each have a channel connected to the same node have the same direction with respect to that node. This rule explicitly recognizes a 2-to-1 multiplexer implemented with transistors, a configuration frequently found in designs. Such a rule is easily incorporated into our procedure. Note that this circuit is not implemented in true complementary MOS. This can be rectified by replacing the pass transistors by transmission gates consisting of p- and n-transistors with the same gate and channel connections. We would then add a rule which recognized that such pairs of transistors have the same direction. Example 3. A full adder. Figure 5 shows a full adder circuit built out of two modules, a sum part and a carry part. Each of these modules is itself built out of
WI. Clocksin, M. E. Leeser / Automaric
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o/ MOS signal flow
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1
1
L
8
t
NCA
-I
A
t c
A
NCA SUM
3 JNCA
ic I, r
NCA
C
u
” B
iF
‘h ,t
C
0
CARRY
Fig. 5
transistors. The top level specification of the adder is: adder(A, B, C, Sum, Carry):sumpart( A, B, C, NCA, Sum), carrypart(A, B, C, NCA, Curry). The sum part consist of twelve transistors, six of which whose direction cannot be established and are thus labelled as bidirectional. All of the transistors in the carry part are unidirectional. Our procedure also establishesthat A, B, and
62
W. F. Clocksin, M. E. Leeser / Aatotnatic
determination
of
MOS signal flow
C are always input ports and Sum and Carry are always output the different possible internal configurations.
ports despite
6. Discussion Determining the direction of signal flow can also be seen as a problem in the statistical thermodynamics of spin systems [5]. If we consider the Ising model, the magnetic moment or ‘spin’ of each atom in a two-dimensional square lattice is assigned a label drawn from the set { - 1, + l), and the energy of the bond between two neighbouring atoms is defined as the negative of the product of the spins of the atoms. Spins are assigned accordin g to criteria governing the total energy of the bonds in the lattice; for example, one might wish to find an assignment of spins such that total energy is minimised. The connection between transistor nets and spin systems is as follows. First, there is the problem of assigning a label from a set of two, for which the criteria for assigning labels depends on interactions between components: nodes in transistor nets and bonds in lattices. The difference is that while a bond joins a pair of nearest neighbors over a regular lattice, a node results from arbitrary connections between any number of components (transistors). Both systems can admit multiple solutions. Multiple solutions result from circuits containing bidirectional transistors, and in the spin context are characteristic of the magnetic alloys known as ‘spin glasses’. Determining signal flow can also be seen as combinatorial optimisation, which is well known [9] to have deep and useful connections with statistical thermodynamics. Consider transistor nets for which we calculate a cost function for each node. First, the directions of transistors are arbitrarily labelled. If a transistor terminal (source or drain) connecting to a node is a source of signal flow we assign a cost of - 1 to the terminal; if a terminal is a sink of signal flow we assign a cost of + 1 to the terminal. Transistor gates are always sinks and hence assigned a cost of + 1. The Signal Law can now be expressed as constraints on nodes. If a node is connected to n terminals where ci is the cost of terminal i, then the node must satisfy the inequation -n < Cc, < n, for i = 1 to n. Furthermore, if the node is connected to a power or ground source, it must satisfy the stronger constraint Cc; = n - 1, for i = 1 to n. The cost of the node is 0 if the constraint is satisfied, 1 if it is not. The total cost of a circuit is the sum of the costs for each node. A legal labelling of transistor directions will have minimum total cost. In the absence of bidirectional transistors, the solution will be unique and hence there is no lower cost. In the presence of bidirectional transistors the minimum total cost will remain constant: if a direction is changed, the roles of signal sink and source are merely exchanged from one node to another. The exchange propagates until another solution is found. Our method is able to recognise certain classes of specification errors, Circuit specifications that do not admit a labelling of transistor directions must be suspect as incorrectly specified. Such specifications contain at least one node
W. F. Clocksin, M. E. Leeser / Automatic
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which contains either all sinks or all sources of signal flow, an impossible situation in practice. Techniques exploiting combinatorial enumeration are always suspected as being inefficient, thus motivating heuristic techniques such as TV. We have already mentioned the use of the hierarchical specification of circuits to reduce the number of configurations to be examined. The number of different kinds of modules in the circuit becomes the important factor instead of the total number of transistors. Other means of reducing computation time are possible, such as the filtering technique of Waltz [12]. If the analogy with spin systems holds, finding the directions of transistors may fall to large-scale Monte Carlo optimisation techniques for which efficient methods are known [7,9].
-Acknowledgements We thank many members of the Computer Laboratory for discussions on the subject of transistors. The circuit of Fig. 5 was supplied by Inder Dhingra. M.E.L. is supported by a research studentship from Acorn Computers Ltd.
References [l] Barrow, H.G., VERIFY: A program for proving correctness of digital hardware designs, Arti/icial Intelligence 24 (1984) 437-491. [2] Clocksin, W.F. and C.S. Mellish, Programming in Prolog (Springer, Berlin, 1981). [3] Clocksin, W.F., Logic programming and the specification of circuits. Technical Report, Computer Laboratory, University of Cambridge, 1985. [4] Clocksin, W.F., Automatic specialisation of standard designs, Technical Report, Computer Laboratory, University of Cambridge, 1985. [5] Domb, C. and MS. Green, Phase Transitions and Critical Phenomena, Volrtrlle 5B (Academic Press, New York, 1976). [6] Gordon, M.J.C., A very simple model of sequential behaviour of nMOS, in: J.P. Gray, Ed., VLSI 81 (Academic Press, New York, 1981). [7] Jacobs, L. and C. Rebbi, Multi-spin coding: A very efficient technique for Monte Carlo simulations of spin systems. J. Comput. Phys. 41 (1981) 203-210. [8] Jouppi, N.P., TV: An nMOS timing analyzer. Proceedings of the 3rd Caltech VLSI Conference, 1983, pp. 71-76. [9] Kirkpatrick, S., C.D. Gelatt and M.P. Vecchi, Optimization by simulated annealing, Science 220 (1983) 671-680. [lo] Mackworth, A.K., Consistency in networks of relations, Artificial Intelligence 8 (1977) 99-118. [ll] Ousterhout, J.K., Crystal: A timing analyzer for nMOS VLSI circuits, Proceedings of the 3rd Caltech VLSI Conference, 1983, pp. 57-69. [12] Waltz, D., Understanding line drawings of scenes with shadows. in: P.H. Winston, ed., The Psychology 01 Computer Vision (McGraw-Hill, New York, 1975).
INTEGRATION
Letter
Automatic determination of signal flow through MOS transistor networks W.F. Clocksin and M.E. Leeser Computer Laboratory,
University of Cambridge,
Cambridge
CB2 3QG, United Kingdom
Received 20 September
Abstract. We describe a method for automatically determining the signal flow through hierarchically specified MOS transistor nets. Direction is determined from the circuit schematic only; no knowledge of signal values or input/output relations is assumed, and particular design rules are not relied on. Unlike previous methods used for MOS transistor nets, our method does not require some transistors to be determined manually, and the method can deal with bidirectional transistors. Circuits are represented using Horn clauses as a hierarchical specification language, and the method is implemented in Prolog. We point out some interesting connections with the statistical thermodynamics of spin systems.
Keywords.
Logic programming,
circuit specification,
design automation.
1. Introduction
Signal flow may be viewed at a digital level as the propagation of logic levels through a network. Thus, power and ground connections are viewed as sourcesof signal flow. Similarly, inputs to a module and outputs from a module are sources and sinks of signal flow, respectively.Note the difference between signal flow and the more traditional view of current flow where power acts as a source of current flow and ground acts as a sink. For example, consider the CMOS inverter in Fig. 1. The dotted arrows show the direction of current flow through the transistors; the solid arrows show the direction of signal flow. Using the definition of signal flow we can derive the input node and output node of the inverter, and this will be shown later. North-Holland INTEGRATION,
the VLSI journal
0167-9260/86/$3.50
0 1986, Elsevier
4 (1986) 53-63 Science
Publishers
B.V. (North-Holland)
54
IV. F. Clocksitr. M. E. Leeser / A utotttatic detertttitratiott
of MOS signal flobc
Fig. 1.
Determining the signal flow through transistors is often a necessary precursor before further circuit analysis can be carried out. For example, both Crystal [ll] and TV [S] require flow analysis before they can proceed with timing analysis. Formal methods for circuit verification [l] and design simplification [4] depend on signal flow being specified in advance. Some design verification methods do not require a preliminary flow analysis, but proofs are easier to compute if the results of flow analysis are available [6]. One way to provide signal flow information is manually. by specifying the input and output roles of components’ ports. Some systems [l,ll] rely on manual specifications entirely. However, automatic signal flow determination can reduce the designer’s workload, particu-
William Clocksin is an Assistant Director of Research at the Computer Laboratory, University of Cambridge. From 1976 to 1980 he carried out postgraduate research at the Department of Artificial Intelligence, University of Edinburgh. in the areas of computer vision and implementation of high level programming languages, particularly Prolog, LISP, and POP-2. From 1980 to 1982 he was at Oxford University, where as GEC Fellow in Robotics he participated in a project that developed a visually-guided robot for welding thin sheet steel assemblies. Since joining the Computer Laboratory in 1983 he has concentrated on the use of standard and non-standard inference in problem solving with applications in design automation, and on high-performance implementations of Prolog. the BSI working group on Prolog Standardization, and is on the editorial turttal of Logic Prograttmittg.
Miriam Leeser received the B.S. degree in Electrical Engineering from Cornell University in 19SO. From 1980 to 1983 she worked in the network products group of Codex Corporation in Mansfield, Massachusetts designing multiprocessor architectures. She received the Diploma in Computer Science from Cambridge University in 1984, where she is pursuing her PhD degree. Her interests include VLSI design, Prolog. and temporal logic. She is currently investigating the use of temporal logic descriptions of circuits in hardware verification.
W. F. Clocksin, M. E. Leeser / Automatic
determination
of MOS signal flow
55
larly for the caseof MOS transistors, which, due to the symmetry of source and drain channels, are capable of conducting in different directions at different times. TV [8] automatically determines signal flow in nMOS transistor nets free of bidirectional transistors and specification errors. TV uses nine rules to determine the direction of transistors. In addition to the general Kirchoff current law, TV uses information about k-ratio rules for inverters as well as other information about the types of circuits used in the design methodology. The method described in this paper is intended for hierarchically specified MOS transistor nets that contain bidirectional transistors, and where there is no information about any particular design methodology. In addition we assume no knowledge about the specific layout. This prevents the use of, for example, the inverter k-ratio rule. Our method is data independent; it does not use knowledge of the values of inputs to a circuit. The analysis is static; its is only dependent on the circuit topology. In essencewe are determining the flow of information through a net assuming all transistors are turned on. Although it is unlikely that this configuration will occur in practice, we are able to determine those transistors whose direction will always remain the same. Transistors which can support signal flow in either direction are labelled bidirectional. Clearly we label some transistors bidirectional which, due to the inputs provided, will only propagate signals in one direction in practice. However, the algorithm guarantees to correctly find all bidirectional transistors, and will not incorrectly label any unidirectional transistor. This procedure will be able to determine the direction of a large percentageof transistors in most circuits. It will not provide much useful information about a design that relies heavily on bidirectional transistors; however, such designs are unusual. An initial implementation was based on TV, except that only four rules were used. Three of the rules were based on TV’s rules, and a new fourth rule was responsible for dealing with transistors whose direction was determined by case analysis if all else failed. While considering the fourth rule it was realised that this rule encompassedmost of the other rules. Our current method, discussed below, uses one rule to determine the directions of transistors. It emergesthat the rules used by TV can be viewed as caseanalysis with the constraint that all nodes have at least one sink and one source of signal flow. 2. Definitions
The input to the direction finder is a circuit specification. We use Prolog [2] as a specification language using a technique described in detail elsewhere [3]. A circuit is composed of a collection of modules and connections between modules. With each module is associated a set of ports between which connections are specified. Ports may be sinks or sources of signal flow or they may be both. Modules can be composed hierarchically, with modules specified in terms of other module specifications. At the bottom of the hierarchy are found primitive modules, the exact form of which depends on the technology being used. In this
W.F. Clocksin, ME. Leeser / Automatic determination of MOS signal flow
56
b-4
(b)
0
Fig. 2.
paper we shall consider p- and n-transistors and power and ground supplies to be primitive. A circuit is representedas a set of Horn clauses in Edinburgh Prolog syntax. This notation directly expressesthe circuit topology and hierarchy. A module having n ports is represented by a predicate of arity n. A module may be specified as a Horn clause in which the head of the clause representsthe module to be defined, and the body of the clause is a composition of the sub-modules defining the module. The sub-modules are composed with the comma connective. Nodes, or junctions of connections, are represented by a unique like-named variable. The ‘:-’ connective of Prolog is reinterpreted to mean ‘is defined by’. The order of the modules in the body is not important. A node which is named by a variable not appearing in the head of the clause is said to be a hidden node. Nodes which are not hidden are called port nodes. For example, Fig. 2(a) depicts the module halfadd, composed of three gates with nodes named by variables as shown. Module halfadd is specified as: halfadd(A, B, S, C) :- xor(A, B, S), nand(A, B, I”), invert( T, C). The variable T defines the ‘hidden’ node between the output of the nand gate
W.F. Clocksin, M. E. Leeser / Automatic determination of MOS signal flow
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and the input of the inverter. Figure 2(b) shows the definition of the nand gate in terms of primitive transistors and power and ground connections. A transistor is specified as trans( X, G, A, B), where X specifies the type of transistor (either p or n); G is the gate, and A and B are the two non-gate terminals. Module nand is specified as: nand(A, B, C):pwr(P), trans(p, B, P, C), trans(p, A, P, C), trans(n, A, C, T), trans(n, B, T, G), grid(G). The ports of the nand module do not have directions specified. In fact ports A and B are inputs, and port C is an output. Below we shall show that our method automatically infers port directions if they are not specified. 3. The method
The task of determining the direction of signal flow can be viewed as a consistent labelling problem [lo]. To solve the problem, it is necessary to associate with each transistor a label drawn from the set { right, left}. Refer to Fig. 3. If the two non-gate terminals of a transistor are arbitrarily named A and B, the label right is assigned to a transistor for which terminal A is a sink of signal flow and terminal B is a source of signal flow. The label left is assignedto a transistor for which terminal A is a source of signal flow and terminal B is a sink of signal flow. For a circuit consisting of n transistors, the number of unconstrained labellings is 2”. The problem is to assign labels to transistors such that a given constraint is satisfied. The constraint we use is that each node of a circuit must be connected to at least one sink and at least one source of signal flow. Moreover, if a node is directly connected to a power or ground, then at most one source of signal flow (the power or ground itself) is allowed. We shall call this constraint the Signal Law. The Signal Law is a consequenceof Kirchoff’s current law. For a circuit containing bidirectional transistors, multiple solutions are admitted. That is, there may be more than one possible labelling of a circuit that satisfies the Signal Law. A bidirectional transistor will be labelled right in one solution and left in another. It follows that the direction of port nodes (whether they are used as inputs or outputs) is an additional constraint on the solution. With our method there is a
A-B
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< left Fig. 3.
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choice of whether to attempt to derive the direction of port nodes automatically (at the risk of obtaining a weak solution), or to use a specified direction of port nodes to constrain the searchfor labellings of transistors. This is discussedbelow. 4. Implementation
The method is implemented in Prolog, using depth-first search through the hierarchical circuit specification to exhaustively enumerate the directions of transistors. The method compounds the direction finding of transistors with establishing the direction of nodes of non-primitive modules. Unlike previous approaches, the whole circuit is not ‘flattened’ into a set of primitive modules. First, the outermost module is decomposedinto its constituent modules, then the direction of the ports of each of these modules is established, and finally it is confirmed that the hidden nodes of the circuit obey the Signal Law. If a module is not primitive, then the direction of its ports is established recursively. The directions of ports of primitive modules, in this case n- and p-transistors, are determined as follows. Transistors have three ports: gate, source, and drain. A transistor’s gate terminal is always a sink of signal flow. If a transistor specified as a trans(n, A, B, C) is assignedthe label left, then B is its source and C is its drain. Similarly, if it is assignedthe label right then B is its drain and C is its source.A transistor sourceis a sourceof signal flow; its drain is a sink. Either the label left or the label right is assignedto a transistor. This is a nondeterministic choice which may be reversedsubsequently if it is found that the original choice leads to a violation of the Signal Law. Power and ground connections are always sourcesof signal flow. At any level of the hierarchy we can identify the set M of modules that comprises the immediately enclosing module. Labels taken from the set { in, out } are associatedwith each port of each module in M. The label in corresponds to the associatedport acting as a sourceof signal flow to a node outside the module; the label out correspondsto the port acting as a sink of signal flow. The labels of ports connecting to a given node are collected into a list associatedwith the node. A hidden node obeys the Signal Law if (a) its list contains at least one in and one out, and (b) if the node directly connects to a power or ground module, then it must contain only one irz. Only the hidden nodes of the enclosing module must satisfy the Signal Law; its ports are checked when the enclosing module itself becomes a sub-module of a larger circuit. If at any level of the hierarchy a node list does not satisfy the Sigrial Law, Prolog will automatically backtrack to find a direction of the sub-modules which satisfies the Signal Law. The effect of this procedure is to try both directions of all transistors until the Signal Law is satisfied. Further backtracking will find all possible solutions. Transistors whose directions are the same in all possible solutions are unidirectional, the remaining transistors are labelled bidirectional. When the procedure succeeds,each port of each module has an associatedlist of ins and 0~s. If all
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elements on the list are ills, then the port is an output; if all elements on the list are outs then it is an input. Otherwise, it is bidirectional. In addition, the number of elements on the list is the number of primitive modules connected to that port. This information may be useful in subsequent analysis of the circuit where we wish to know the capacitive loading of a node. Note that the level of nesting of the hierarchy is arbitrary, and each module or submodule of a circuit may be specified at a different level. In the dynamic register example of the next section, the dynamic register is comprised of a combination of primitive transistors and non-primitive inverters. We can further exploit the hierarchy of the circuit specification using a technique described more fully elsewhere[4]. Once the directions of ports have been found for a type of submodule, the result can be stored in a library. This library would be consulted for each submodule when the procedure is invoked. Thus, direction setting only needs to be determined once for each type of submodule. In this context, trying both possible directions for all transistors in a circuit becomesreasonablefor circuits with very large numbers of transistors. For example, suppose we wish to include a CMOS inverter in our library. Running our procedure on the inverter circuit once will set the direction of both transistors and establish the input and output. This result will then be stored, and each additional time an inverter is discovered, the input and output nodes are looked up in the library. Instead of four possible labellings for each inverter submodule, only one is considered. The benefits become greater as our library and the complexity of the submodules contained in that library grow. 5. Examples
We will now show the result of applying this procedure to a few simple examples. These include a CMOS inverter, a dynamic register which illustrates submodules defined at different levels of hierarchy and the utility of a library, and a full adder which has bidirectional transistors. Example
1. A CMOS inverter (Fig. 1). This circuit is specified as:
invert(A, B) :- pwr( P), trans(p, A, P, B), grid(G), trans(n, A, B, G).
Fig. 4
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Since any connection to power or ground is an input, it is clear that the n-transistor would be labelled right and the p-transistor would be labelled left. This correspondsto the arrows for signal flow shown in Fig. 1. The resulting node list for A is [A, out, out] telling us that A is the input to the module. Similarly, the resulting node list for B is [B, in, in] so B is the module’s output. Backtracking would not find further solutions. Example 2. A dynamic register (Fig. 4). This circuit is specified as: dreg(A, B, Load):trans(n, Load, A, X), invert( X, Y), invert( Y, B), trans(n, Z, B, X), invert( Load, Z). This simple module illustrates several key aspects of our approach. Internal connections such as nodes X, Y, and Z are hidden through use of Prolog variables. In addition, a module may combine submodules described at different levels of hierarchy; here we mix primitive and non-primitive elements. This example also illustrates the utility of a library of submodules. If the input and output of the inverter circuit were stored in a library, then only the direction of the two pass-transistors need be considered. Thus only four possible label assignments are investigated. From the method presented so far, it is impossible to ascertain a unique direction for the two pass-transistors. There are three ways to deal with this problem. One is to leave the direction specified as bidirectional until the register is used in an enclosing module. Another is to use specifications of the directions of ports. For example, in the dreg module, the specification that A is an input leads to the solution of the direction of the transistor directly connected to it. However, the specification that B is an output does not imply a single direction for the other transistor. Another approach is to incorporate a rule used by TV. This rule recognizesthat two transistors whose gates are the complements of one another and who each have a channel connected to the same node have the same direction with respect to that node. This rule explicitly recognizes a 2-to-1 multiplexer implemented with transistors, a configuration frequently found in designs. Such a rule is easily incorporated into our procedure. Note that this circuit is not implemented in true complementary MOS. This can be rectified by replacing the pass transistors by transmission gates consisting of p- and n-transistors with the same gate and channel connections. We would then add a rule which recognized that such pairs of transistors have the same direction. Example 3. A full adder. Figure 5 shows a full adder circuit built out of two modules, a sum part and a carry part. Each of these modules is itself built out of
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1
1
L
8
t
NCA
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t c
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ic I, r
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transistors. The top level specification of the adder is: adder(A, B, C, Sum, Carry):sumpart( A, B, C, NCA, Sum), carrypart(A, B, C, NCA, Curry). The sum part consist of twelve transistors, six of which whose direction cannot be established and are thus labelled as bidirectional. All of the transistors in the carry part are unidirectional. Our procedure also establishesthat A, B, and
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C are always input ports and Sum and Carry are always output the different possible internal configurations.
ports despite
6. Discussion Determining the direction of signal flow can also be seen as a problem in the statistical thermodynamics of spin systems [5]. If we consider the Ising model, the magnetic moment or ‘spin’ of each atom in a two-dimensional square lattice is assigned a label drawn from the set { - 1, + l), and the energy of the bond between two neighbouring atoms is defined as the negative of the product of the spins of the atoms. Spins are assigned accordin g to criteria governing the total energy of the bonds in the lattice; for example, one might wish to find an assignment of spins such that total energy is minimised. The connection between transistor nets and spin systems is as follows. First, there is the problem of assigning a label from a set of two, for which the criteria for assigning labels depends on interactions between components: nodes in transistor nets and bonds in lattices. The difference is that while a bond joins a pair of nearest neighbors over a regular lattice, a node results from arbitrary connections between any number of components (transistors). Both systems can admit multiple solutions. Multiple solutions result from circuits containing bidirectional transistors, and in the spin context are characteristic of the magnetic alloys known as ‘spin glasses’. Determining signal flow can also be seen as combinatorial optimisation, which is well known [9] to have deep and useful connections with statistical thermodynamics. Consider transistor nets for which we calculate a cost function for each node. First, the directions of transistors are arbitrarily labelled. If a transistor terminal (source or drain) connecting to a node is a source of signal flow we assign a cost of - 1 to the terminal; if a terminal is a sink of signal flow we assign a cost of + 1 to the terminal. Transistor gates are always sinks and hence assigned a cost of + 1. The Signal Law can now be expressed as constraints on nodes. If a node is connected to n terminals where ci is the cost of terminal i, then the node must satisfy the inequation -n < Cc, < n, for i = 1 to n. Furthermore, if the node is connected to a power or ground source, it must satisfy the stronger constraint Cc; = n - 1, for i = 1 to n. The cost of the node is 0 if the constraint is satisfied, 1 if it is not. The total cost of a circuit is the sum of the costs for each node. A legal labelling of transistor directions will have minimum total cost. In the absence of bidirectional transistors, the solution will be unique and hence there is no lower cost. In the presence of bidirectional transistors the minimum total cost will remain constant: if a direction is changed, the roles of signal sink and source are merely exchanged from one node to another. The exchange propagates until another solution is found. Our method is able to recognise certain classes of specification errors, Circuit specifications that do not admit a labelling of transistor directions must be suspect as incorrectly specified. Such specifications contain at least one node
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which contains either all sinks or all sources of signal flow, an impossible situation in practice. Techniques exploiting combinatorial enumeration are always suspected as being inefficient, thus motivating heuristic techniques such as TV. We have already mentioned the use of the hierarchical specification of circuits to reduce the number of configurations to be examined. The number of different kinds of modules in the circuit becomes the important factor instead of the total number of transistors. Other means of reducing computation time are possible, such as the filtering technique of Waltz [12]. If the analogy with spin systems holds, finding the directions of transistors may fall to large-scale Monte Carlo optimisation techniques for which efficient methods are known [7,9].
-Acknowledgements We thank many members of the Computer Laboratory for discussions on the subject of transistors. The circuit of Fig. 5 was supplied by Inder Dhingra. M.E.L. is supported by a research studentship from Acorn Computers Ltd.
References [l] Barrow, H.G., VERIFY: A program for proving correctness of digital hardware designs, Arti/icial Intelligence 24 (1984) 437-491. [2] Clocksin, W.F. and C.S. Mellish, Programming in Prolog (Springer, Berlin, 1981). [3] Clocksin, W.F., Logic programming and the specification of circuits. Technical Report, Computer Laboratory, University of Cambridge, 1985. [4] Clocksin, W.F., Automatic specialisation of standard designs, Technical Report, Computer Laboratory, University of Cambridge, 1985. [5] Domb, C. and MS. Green, Phase Transitions and Critical Phenomena, Volrtrlle 5B (Academic Press, New York, 1976). [6] Gordon, M.J.C., A very simple model of sequential behaviour of nMOS, in: J.P. Gray, Ed., VLSI 81 (Academic Press, New York, 1981). [7] Jacobs, L. and C. Rebbi, Multi-spin coding: A very efficient technique for Monte Carlo simulations of spin systems. J. Comput. Phys. 41 (1981) 203-210. [8] Jouppi, N.P., TV: An nMOS timing analyzer. Proceedings of the 3rd Caltech VLSI Conference, 1983, pp. 71-76. [9] Kirkpatrick, S., C.D. Gelatt and M.P. Vecchi, Optimization by simulated annealing, Science 220 (1983) 671-680. [lo] Mackworth, A.K., Consistency in networks of relations, Artificial Intelligence 8 (1977) 99-118. [ll] Ousterhout, J.K., Crystal: A timing analyzer for nMOS VLSI circuits, Proceedings of the 3rd Caltech VLSI Conference, 1983, pp. 57-69. [12] Waltz, D., Understanding line drawings of scenes with shadows. in: P.H. Winston, ed., The Psychology 01 Computer Vision (McGraw-Hill, New York, 1975).