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Automatic process control for VLSI linewidth
792
World Abstracts on Microelectronics and Reliability
of integrated circuits through 1990, but it is unclear which of the optical approaches will be successful. Electron beams are the optimum choice for masks and customization, but for volume production their cost is, and will remain, prohibitive. Beyond 1990, the situation for volume production of devices smaller than 0.5 #m is not predictable. X-ray lithography offers the best process control, but an electron storage ring, or a new laser/plasma source is needed to overcome the throughput and accuracy problems encountered with conventional electron bombardment sources. Competing with xrays are many other approaches using electrons, ions, and photons. Perhaps the most likely outcome will be that history will repeat itself, and that optics (by then vacuum UVillumination and immersion lenses) will continue to dominate, even down to 0.25 #m.
IC production fines move closer to full automation. JERRY LYMAN.Electronics 42 (8 July, 1985). Robots, guided vehicles, standard interfaces, and computer networks point to higher chip yields. Two-dimensional device simulation program: 2DP. S. P. GAUR, P. A. HABITZ, Y.-J. PARK, R. K. COOK, Y.-S. HUANG and L. F. WAGNER. I B M J. Res. Devl. 29 (3) 242 (May 1985). Mathematical details of a two-dimensional semiconductor device simulation program are presented. Applicability of the carrier transport model to shallow junction bipolar transistors is discussed. Use of this program to optimize device structures in new bipolar technology is illustrated by presenting calculated device characteristics for variations in a few selected process conditions. Software links that automatically transfer data from a two-dimensional process simulation program and to a quasi-threedimensional device equivalent circuit model generation program are also discussed. A new set of semiconductor equations for computer simulation of submicron devices. CHENGT. WANG. Solid-St. Electron. 28 (8) 783 (1985). A new set of semiconductor equations is proposed here which will be suitable for the numerical study of the carrier transport effects in submicron devices. With simplified models and comprehensive numerical techniques, the relative importance (on the device behavior) of several physical effects, such as velocity overshoot, intracollisional field effect, avalanche breakdown, carrier generation and temperature effect can be determined. The program that is capable of solving this set of equations will become an indispensible CAD tool if the current trend of the decreasing of the device dimensions continues. Rapid annealing technology for future VLSI. S. R. WILSON,W. M. PAULSONand R. B. GREGORY.Solid St. Technol. 185 (June 1985). The entire thermal treatment of water subsequent to a critical doping step must be precisely controlled. This thermal treatment usually includes such process steps as single-crystal and polycrystalline implant activations, silicide reactions and passivation glass reflow. Rapid thermal processing uses short-time, high-temperature steps and has been applied to each of these process steps with reasonable success. In addition, rapid thermal processing has been used to fabricate a variety of ion implanted devices which yielded very acceptable performance characteristics. The technology appears to be a useful and probably necessary tool for present and future VLSI circuits. Our results and the results of some other workers in the field are reviewed; present and possible future applications are discussed. Wafer dicing: on the threshold of automation. H. FACTORand K. KAUFMAN.Solid St. Teehnot. 8t (July t985). Two major forces are driving the development of dicing technology today: the trend toward automation and the need for technological sophistication resulting from wafer and production evolution. Some factors typifying this evolution include
larger diameter and thicker wafers, thinner streets tsometimes containing lithographic information), and a large variety of die sizes and patterns. Maximum-reliability equipment design and consistent, flexible image/pattern processing capabilities represent the newest challenges to dicing system manufacturers. At the same time, dicing equipment users are reexamining older automation concepts and must now participate actively in integrating new equipment into their facilities. Some innovative ideas are outlined and the way automation in the dicing process may become one of the leading elements in the semiconductuctor assembly factory of the future is discussed.
Borophosphosilicate glasses for integrated circuits. WERNER KERN and RONALDK. SMELTZER.Solid St. Technol. 171 (June 1985). Films of borophosphosilicate glass tBPSG) can be prepared by chemical vapor deposition (CVD) processes that are based on atmospheric pressure, low pressure, and plasma-enhanced techniques at temperatures in the range of 325-450"C. The films are being used as fusable dielectrics, primarily for silicon-gate MOS integrated circuits, to contour device topography at temperatures as much as 300°C lower than those employed with conventional phosphosilicate glasses. The advantages and problems of the various CVD processes for BPSG synthesis are discussed and the important properties of these films are described. The current use of BPSG in circuit fabrication of short-channel and radiation-hardened devices is described to illustrate the applicability of the technology. IC-design automation strides into silicon-compilation era, JEREMYYOUNG.Electronics 58 (24 June, 1985). More conventional chip-design tools get boost from hardware accelerators, expert-system technology. Review of single wafer reactor technology for device processing. G. S. MATHAD. Solid St. Technol. 221 (April 1985). During the past three years, there has been an explosion of equipment vendors offering a variety of single wafer etchers, fully automated and ready to roll on the floors of semiconductor manufacturing facilities. Etching one wafer at a time offers several advantages including improved process control, which relates to increased yields. This important manufacturing technology is available in the marketplace in various generic reactor types. These reactors, classified according to the pressure regimes in which they operate, are reviewed along with a discussion on their principles of operation and key design aspects. A review of plasma processing fundamentals. HERBERT H. SAWlN. Solid St. Technol. 211 (April 1985). The plasma physics and chemistry of glow discharge processes are reviewed. These fundamental phenomena are related to observable plasma etching effects including anisotropy, selectivity, uniformity, and loading. Typical effects of process parameters such as reactor geometry, feed gas composition, power, and pressure are discussed. Overlay accuracy for VLSI devices. W. WAKAMIYAand M. NAKAJIMA. Semiconductor Int. 322 (May 1985). Fine tuning the linewidths and resist thickness of stepper alignment marks. The gases of plasma etching: silicon-based technology. J. A. MUCHA. Solid St. Technol. 123 (March 1985). The trend toward higher and higher circuit density in microcircuit pattern delineation has required the use of ptasma etching for many process steps. Plasma processing for silicon-based technology is reviewed in terms ofthe gases and gas rnixtnr~,s required to selectively etch important films such as silicon, poly-silicon, oxide and nitride, metals, and organics. Automatic process control for VLSI linewidth. L. LAUCHLAN,
World Abstracts on Microelectronics and Reliability K. SAUTTER and T. BATCHELDER.Solid State Technol. 333 (April 1985). A method for in-line, automatic linewidth control for both spray and puddle development of photoresist is described. The equipment employed can also be used in a process diagnostic mode to evaluate such photoresist parameters as resist dissolution rate or initiation time before development actually begins. The implications of this tool for fully automated photoresist processing are discussed.
Low pressure plasma etching with magnetic confinement. T. D. MANTEI and T. E. WICKER. Solid St. Technol. 263 (April 1985). A low pressure plasma etching reactor has been tested which combines a d c plasma, a surface magnetic-field layer for charged-particle confinement, and independently controlled substrate biasing. The confinement geometry allows a reduction in operating gas pressure while maintaining high reactant densities (~ 1011 cm 3) and high etch rates. Typical operating gas pressures are 0.2 to 2.0 millitorr; gas flow rates are 1 to 5 sccm. With modest values of substrate bias voltage (0 to --400 V), silicon can be etched anisotropicalty with etch rates greater than 1 #m/min in SF6/O 2 at 2.0 millitorr. The Si to SiO 2 selectivity is 10-20.
Automating inter-equipment transport. PETER H. SINGER, Semiconductor Int. 56 (March 1985). Cassette-to-cassette automation is currently available on most front-end equipment, yet wafer transport between equipment is only beginning to be developed.
Elastic light scattering techniques for semiconductor technology. E. F. STEIGMEIERand H. AUDERSET.R C A Rev. 46 3 (March 1985). This paper provides an overview of elastic light scattering techniques for use in semiconductor technology. The following methods are described: (1) optical scanner used for dust and defect detection, (2) optical scanner used for testing the structural perfection of films and wafers, (3) rapid testing for acceptibility of polycrystalline silicon in terms of amorphous or crystalline deposition, and (4) elastic light scattering topography of starting wafers. The latter three methods are novel in the field, and can contribute to a considerable device yield improvement.
793
discusses some of the ways in which these problems have been solved. A full-scaled NMOS technology for VLSI circuits. J. Y. LE~, H. L. GARVIN, C. W. SLAYMANand B. D. RENSen. Microelectron. J. 16 (3) 34 (1985). A fully-scaled NMOS process was developed for VLSI circuits. Device isolation was achieved by channel stop implant using a reverse tone resist technique. This isolation process gives high field turn-on voltage, minimal narrow width effect and low body effect. A tri-level photoresist process was developed for gate definition. This process technology was demonstrated through the successful fabrication of an 8 × 8 bit parallel multiplier with submicrometer gatelengths. This 8 x 8 bit multiplier has a multiplication time of 9.5 ns.
Automatic x-ray alignment system for submicron VLSI lithography. B. FAY and W. T. NOVAK. Solid St. Technol. 175 (May 1985). An automatic x-ray alignment/exposure system developed for VLSI application involving printed linewidths in the one micron and submicron range is described. This paper focuses on an automatic alignment system designed to meet the specific overlay requirements for such applications. Other key elements of this fully automated, high throughput wafer exposure system are briefly presented.
Chromatography as a tool in the characterization and quality control of resist materials. L. E. STILLWAGON.Solid St. Technol. 113 (May 1985). Liquid chromatography, LC, is a useful and valuable tool in the analysis and characterization of resist materials. This paper describes two LC techniques, adsorption chromatography and size-exclusion chromatography, SEC, and then discusses the application of LC to resist materials. The applications section of the text is divided into two parts concerning photo- and electron-beam resists. The first part discusses the role LC can pla6, in either identifying and characterizing individual photoresist components or as a quality-control monitor for photoresists. In the second part, specific examples are presented relating the influence of resist molecular weight and molecular weight distribution measured by SEC, on the performance of electron-beam resist materials.
Advantages of magnetron etching. MICHAEL L. HILL and DAVID C. HINSON. Solid St. Technol. 243 (April 1985). Magnetron Ion Etching (MIE) represents a significant advance in dry etch technology. MIE eliminates many of the tradeoffs and compromises inherent in other dry etch approaches. It operates at low pressure (about 5 millitorr), and provides fast etch rates (> 6000 A/min for SiO2, > 15,000 A/min for anisotropic silicon etching and > 25,000 A/min for polymer etching). In addition, the sheath voltage seen by ions accelerated toward wafers is about 50% less than that of other technologies, leading to lower radiation damage of devices.
Advanced step and repeat aligner for VLSI. JIM DEY. Microelectron. J. 16 (3) 23 (1985). Semiconductor devices with minimum feature sizes of 1 to 3 #m are now being manufactured in large increasing volumes. These products can be manufactured most effectively using step and repeat exposure directly on the wafers. The first generation of production wafer steppers proved the viability of the technique in producing high quality, high resolution images on wafers. There is no longer any doubt that the technique results in substantial yield increases and improved device performance. However, there is concern about the ability of these first generation machines to fit confortably into a manufacturing environment and to have the versatility to handle the multitude of day-to-day problems that are encountered in production. Optical technology is not the problem. The second-generation wafer steppers attack the problems of throughput, alignment, flexibility, and suitability for production environments. The Eaton Series 8000 Wafer Steppers have been designed to address these problems. This paper
Materials and technology of wafering. NIELS JACKSON.Solid St. Technol. 107 (July 1985). Silicon wafering technology is simultaneously undergoing product/performance improvements and is becoming more cost effective due to international competitive factors. Choosing and/or optimizing wafering processes requires an understanding of substrate material properties which determine the inherent limitations of wafering equipment. The material physics of the two main wafering processes (ID and slurry saws) used today are explored. Equipment is examined for rigidity, programmability, and economy. The consequences of various coolants/lubricants, abrasives, and blade configurations are related to wafering performance. Common problem areas such as dimensional control, flatness, induced damage, and breakage are related to operating parameters. Finally, some novel wafering apparatus and concepts are presented for non-traditional wafering applications.
Diamond blade technology in die separation. GERRy B. GARIEPY. Solid St. Technol. 95 (July 1985). Die separation using an electroformed diamond blade with a through cut on a microprocessor controlled dicing saw has become the method of choice among leading IC producers. Good quality cuts and long blade life are assured through understanding the many variables and interactions affecting blade usage. This article reviews those variables, industry trends towards larger diameter wafers and narrow streets, and blade technology related to GaAs and other new materials. It also reviews problems related to dicing blade technology (chipping, productivity, and blade life) and recommends solutions.
World Abstracts on Microelectronics and Reliability
of integrated circuits through 1990, but it is unclear which of the optical approaches will be successful. Electron beams are the optimum choice for masks and customization, but for volume production their cost is, and will remain, prohibitive. Beyond 1990, the situation for volume production of devices smaller than 0.5 #m is not predictable. X-ray lithography offers the best process control, but an electron storage ring, or a new laser/plasma source is needed to overcome the throughput and accuracy problems encountered with conventional electron bombardment sources. Competing with xrays are many other approaches using electrons, ions, and photons. Perhaps the most likely outcome will be that history will repeat itself, and that optics (by then vacuum UVillumination and immersion lenses) will continue to dominate, even down to 0.25 #m.
IC production fines move closer to full automation. JERRY LYMAN.Electronics 42 (8 July, 1985). Robots, guided vehicles, standard interfaces, and computer networks point to higher chip yields. Two-dimensional device simulation program: 2DP. S. P. GAUR, P. A. HABITZ, Y.-J. PARK, R. K. COOK, Y.-S. HUANG and L. F. WAGNER. I B M J. Res. Devl. 29 (3) 242 (May 1985). Mathematical details of a two-dimensional semiconductor device simulation program are presented. Applicability of the carrier transport model to shallow junction bipolar transistors is discussed. Use of this program to optimize device structures in new bipolar technology is illustrated by presenting calculated device characteristics for variations in a few selected process conditions. Software links that automatically transfer data from a two-dimensional process simulation program and to a quasi-threedimensional device equivalent circuit model generation program are also discussed. A new set of semiconductor equations for computer simulation of submicron devices. CHENGT. WANG. Solid-St. Electron. 28 (8) 783 (1985). A new set of semiconductor equations is proposed here which will be suitable for the numerical study of the carrier transport effects in submicron devices. With simplified models and comprehensive numerical techniques, the relative importance (on the device behavior) of several physical effects, such as velocity overshoot, intracollisional field effect, avalanche breakdown, carrier generation and temperature effect can be determined. The program that is capable of solving this set of equations will become an indispensible CAD tool if the current trend of the decreasing of the device dimensions continues. Rapid annealing technology for future VLSI. S. R. WILSON,W. M. PAULSONand R. B. GREGORY.Solid St. Technol. 185 (June 1985). The entire thermal treatment of water subsequent to a critical doping step must be precisely controlled. This thermal treatment usually includes such process steps as single-crystal and polycrystalline implant activations, silicide reactions and passivation glass reflow. Rapid thermal processing uses short-time, high-temperature steps and has been applied to each of these process steps with reasonable success. In addition, rapid thermal processing has been used to fabricate a variety of ion implanted devices which yielded very acceptable performance characteristics. The technology appears to be a useful and probably necessary tool for present and future VLSI circuits. Our results and the results of some other workers in the field are reviewed; present and possible future applications are discussed. Wafer dicing: on the threshold of automation. H. FACTORand K. KAUFMAN.Solid St. Teehnot. 8t (July t985). Two major forces are driving the development of dicing technology today: the trend toward automation and the need for technological sophistication resulting from wafer and production evolution. Some factors typifying this evolution include
larger diameter and thicker wafers, thinner streets tsometimes containing lithographic information), and a large variety of die sizes and patterns. Maximum-reliability equipment design and consistent, flexible image/pattern processing capabilities represent the newest challenges to dicing system manufacturers. At the same time, dicing equipment users are reexamining older automation concepts and must now participate actively in integrating new equipment into their facilities. Some innovative ideas are outlined and the way automation in the dicing process may become one of the leading elements in the semiconductuctor assembly factory of the future is discussed.
Borophosphosilicate glasses for integrated circuits. WERNER KERN and RONALDK. SMELTZER.Solid St. Technol. 171 (June 1985). Films of borophosphosilicate glass tBPSG) can be prepared by chemical vapor deposition (CVD) processes that are based on atmospheric pressure, low pressure, and plasma-enhanced techniques at temperatures in the range of 325-450"C. The films are being used as fusable dielectrics, primarily for silicon-gate MOS integrated circuits, to contour device topography at temperatures as much as 300°C lower than those employed with conventional phosphosilicate glasses. The advantages and problems of the various CVD processes for BPSG synthesis are discussed and the important properties of these films are described. The current use of BPSG in circuit fabrication of short-channel and radiation-hardened devices is described to illustrate the applicability of the technology. IC-design automation strides into silicon-compilation era, JEREMYYOUNG.Electronics 58 (24 June, 1985). More conventional chip-design tools get boost from hardware accelerators, expert-system technology. Review of single wafer reactor technology for device processing. G. S. MATHAD. Solid St. Technol. 221 (April 1985). During the past three years, there has been an explosion of equipment vendors offering a variety of single wafer etchers, fully automated and ready to roll on the floors of semiconductor manufacturing facilities. Etching one wafer at a time offers several advantages including improved process control, which relates to increased yields. This important manufacturing technology is available in the marketplace in various generic reactor types. These reactors, classified according to the pressure regimes in which they operate, are reviewed along with a discussion on their principles of operation and key design aspects. A review of plasma processing fundamentals. HERBERT H. SAWlN. Solid St. Technol. 211 (April 1985). The plasma physics and chemistry of glow discharge processes are reviewed. These fundamental phenomena are related to observable plasma etching effects including anisotropy, selectivity, uniformity, and loading. Typical effects of process parameters such as reactor geometry, feed gas composition, power, and pressure are discussed. Overlay accuracy for VLSI devices. W. WAKAMIYAand M. NAKAJIMA. Semiconductor Int. 322 (May 1985). Fine tuning the linewidths and resist thickness of stepper alignment marks. The gases of plasma etching: silicon-based technology. J. A. MUCHA. Solid St. Technol. 123 (March 1985). The trend toward higher and higher circuit density in microcircuit pattern delineation has required the use of ptasma etching for many process steps. Plasma processing for silicon-based technology is reviewed in terms ofthe gases and gas rnixtnr~,s required to selectively etch important films such as silicon, poly-silicon, oxide and nitride, metals, and organics. Automatic process control for VLSI linewidth. L. LAUCHLAN,
World Abstracts on Microelectronics and Reliability K. SAUTTER and T. BATCHELDER.Solid State Technol. 333 (April 1985). A method for in-line, automatic linewidth control for both spray and puddle development of photoresist is described. The equipment employed can also be used in a process diagnostic mode to evaluate such photoresist parameters as resist dissolution rate or initiation time before development actually begins. The implications of this tool for fully automated photoresist processing are discussed.
Low pressure plasma etching with magnetic confinement. T. D. MANTEI and T. E. WICKER. Solid St. Technol. 263 (April 1985). A low pressure plasma etching reactor has been tested which combines a d c plasma, a surface magnetic-field layer for charged-particle confinement, and independently controlled substrate biasing. The confinement geometry allows a reduction in operating gas pressure while maintaining high reactant densities (~ 1011 cm 3) and high etch rates. Typical operating gas pressures are 0.2 to 2.0 millitorr; gas flow rates are 1 to 5 sccm. With modest values of substrate bias voltage (0 to --400 V), silicon can be etched anisotropicalty with etch rates greater than 1 #m/min in SF6/O 2 at 2.0 millitorr. The Si to SiO 2 selectivity is 10-20.
Automating inter-equipment transport. PETER H. SINGER, Semiconductor Int. 56 (March 1985). Cassette-to-cassette automation is currently available on most front-end equipment, yet wafer transport between equipment is only beginning to be developed.
Elastic light scattering techniques for semiconductor technology. E. F. STEIGMEIERand H. AUDERSET.R C A Rev. 46 3 (March 1985). This paper provides an overview of elastic light scattering techniques for use in semiconductor technology. The following methods are described: (1) optical scanner used for dust and defect detection, (2) optical scanner used for testing the structural perfection of films and wafers, (3) rapid testing for acceptibility of polycrystalline silicon in terms of amorphous or crystalline deposition, and (4) elastic light scattering topography of starting wafers. The latter three methods are novel in the field, and can contribute to a considerable device yield improvement.
793
discusses some of the ways in which these problems have been solved. A full-scaled NMOS technology for VLSI circuits. J. Y. LE~, H. L. GARVIN, C. W. SLAYMANand B. D. RENSen. Microelectron. J. 16 (3) 34 (1985). A fully-scaled NMOS process was developed for VLSI circuits. Device isolation was achieved by channel stop implant using a reverse tone resist technique. This isolation process gives high field turn-on voltage, minimal narrow width effect and low body effect. A tri-level photoresist process was developed for gate definition. This process technology was demonstrated through the successful fabrication of an 8 × 8 bit parallel multiplier with submicrometer gatelengths. This 8 x 8 bit multiplier has a multiplication time of 9.5 ns.
Automatic x-ray alignment system for submicron VLSI lithography. B. FAY and W. T. NOVAK. Solid St. Technol. 175 (May 1985). An automatic x-ray alignment/exposure system developed for VLSI application involving printed linewidths in the one micron and submicron range is described. This paper focuses on an automatic alignment system designed to meet the specific overlay requirements for such applications. Other key elements of this fully automated, high throughput wafer exposure system are briefly presented.
Chromatography as a tool in the characterization and quality control of resist materials. L. E. STILLWAGON.Solid St. Technol. 113 (May 1985). Liquid chromatography, LC, is a useful and valuable tool in the analysis and characterization of resist materials. This paper describes two LC techniques, adsorption chromatography and size-exclusion chromatography, SEC, and then discusses the application of LC to resist materials. The applications section of the text is divided into two parts concerning photo- and electron-beam resists. The first part discusses the role LC can pla6, in either identifying and characterizing individual photoresist components or as a quality-control monitor for photoresists. In the second part, specific examples are presented relating the influence of resist molecular weight and molecular weight distribution measured by SEC, on the performance of electron-beam resist materials.
Advantages of magnetron etching. MICHAEL L. HILL and DAVID C. HINSON. Solid St. Technol. 243 (April 1985). Magnetron Ion Etching (MIE) represents a significant advance in dry etch technology. MIE eliminates many of the tradeoffs and compromises inherent in other dry etch approaches. It operates at low pressure (about 5 millitorr), and provides fast etch rates (> 6000 A/min for SiO2, > 15,000 A/min for anisotropic silicon etching and > 25,000 A/min for polymer etching). In addition, the sheath voltage seen by ions accelerated toward wafers is about 50% less than that of other technologies, leading to lower radiation damage of devices.
Advanced step and repeat aligner for VLSI. JIM DEY. Microelectron. J. 16 (3) 23 (1985). Semiconductor devices with minimum feature sizes of 1 to 3 #m are now being manufactured in large increasing volumes. These products can be manufactured most effectively using step and repeat exposure directly on the wafers. The first generation of production wafer steppers proved the viability of the technique in producing high quality, high resolution images on wafers. There is no longer any doubt that the technique results in substantial yield increases and improved device performance. However, there is concern about the ability of these first generation machines to fit confortably into a manufacturing environment and to have the versatility to handle the multitude of day-to-day problems that are encountered in production. Optical technology is not the problem. The second-generation wafer steppers attack the problems of throughput, alignment, flexibility, and suitability for production environments. The Eaton Series 8000 Wafer Steppers have been designed to address these problems. This paper
Materials and technology of wafering. NIELS JACKSON.Solid St. Technol. 107 (July 1985). Silicon wafering technology is simultaneously undergoing product/performance improvements and is becoming more cost effective due to international competitive factors. Choosing and/or optimizing wafering processes requires an understanding of substrate material properties which determine the inherent limitations of wafering equipment. The material physics of the two main wafering processes (ID and slurry saws) used today are explored. Equipment is examined for rigidity, programmability, and economy. The consequences of various coolants/lubricants, abrasives, and blade configurations are related to wafering performance. Common problem areas such as dimensional control, flatness, induced damage, and breakage are related to operating parameters. Finally, some novel wafering apparatus and concepts are presented for non-traditional wafering applications.
Diamond blade technology in die separation. GERRy B. GARIEPY. Solid St. Technol. 95 (July 1985). Die separation using an electroformed diamond blade with a through cut on a microprocessor controlled dicing saw has become the method of choice among leading IC producers. Good quality cuts and long blade life are assured through understanding the many variables and interactions affecting blade usage. This article reviews those variables, industry trends towards larger diameter wafers and narrow streets, and blade technology related to GaAs and other new materials. It also reviews problems related to dicing blade technology (chipping, productivity, and blade life) and recommends solutions.