Automatic removal of false reversals in telex networks

© EUROMICRO EUROMICROJournal6 (1980)37-40

Automatic Removal of False Reversals in Telex Networks M. Moustafa Rateb and M. Nagi Elyousfi Military Technical College, Cairo, Egypt

This paper introduces the industrial realization of a set-up that removes automatically the false reversals in S.C. telex networks. The time interval between two successive false call-connections is selected as a diagnostic criterion. The realized SSI-MSI set-up is discussed in details with associated design considerations in brief. A proposed solution using microprocessors is also introduced.

time i n t e r v a l is very small but not zero. The proposed design must include this f a c t o r and remove this simulated p o l a r i t y reversal when i t

1. INTRODUCTION A serious problem frequently occurs due to t e l e x l i n e worker's shortage in experience. This is the reversal of the subscriber's l i n e p o l a r i t y , e i ther in the man hole or at the subscriber's dist r i b u t i o n box. In S.C. t e l e x networks, the false reversal represents a call-connection from the exchange and the subscriber t e l e p r i n t e r ' s motor sta rt s . Since the p o l a r i t y is s t i l l reversed, a new call-connection from the exchange is taken place a f t e r a certain time period. These successive f a l s e call-connections w i l l l a s t as long as reversal defect is not removed leading to f u l l occupation of the exchange by this f a l s e communication.

Occurs.

2.2. Approaches to Solution There are two p o s s i b i l i t i e s to connect the automatic false reversal removing set-up: I. To connect the set to the subscribers control box. 2. To connect i t at the exchange. The f i r s t approach gives r i s e up to a simple r e a l i z a t i o n using SSIMSl-transistor c i r c u i t s . Studies proved that this approach secures better economy and higher r e l i ability. The second approach has the unique advantage of securing central supervision. The set-up in this position searches f or the selected c r i t e r i o n over a l l lines and removes this defect as i t appears. A microprocessor can serve f o r t h i s purpose i f i t is interfaced by a m u l t i p l e x e r and a buffer memory.

2. BASIC CRITERION AND APPROACHESTO SOLUTION 2.1. Basic C r i t e r i o n Since the l i n e carries many types of information, the c r i t e r i o n to be selected must have a special character such that no confusion may occur that disturbs the o r i g i n a l communication. The time i n t e r v a l between two successive false c a l l - c o n nections is s~lected as a c r i t e r i o n . The problem i s , what is the s u i t a b l e time i n t e r v a l ? I f a succession of two call-connections is detected, a false reversal is decided.

The f i r s t approach, which has proved successful in practice, w i l l be introduced in d e t a i l s , while a short review concerning the second approach w i l l be given. 3. BASIC IDEA

This r e l a t i o n is affected by two decisive cont r a d i c t i n g factors: I. The maximum probable time i n t e r v a l between two false c a l l - c o n n e c t i o n s . f o r a subscriber, in a s p e c i f i c exchange, i f false reversal is taking place. 2. The minimum time required f o r a nervous subscriber to press the s t a r t button in the control u n i t , to press the stop button and to press the s t a r t button once again. In t h i s case the subscriber is simulating the reversal c r i t e r i o n .

The t o t a l set-up is a s t a r t - s t o p system which begins operation as soon as a line-connection signal is detected and stops function ater a time of 10.24 sec. During this 10.24 sec the set-up ident i f i e s the occurrence of reversal, i f during this time i n t e r v a l , another l i n e connection signal occurs. The basic idea can be c l e a r l y understood by considering the block diagram (Fig. I) and the waveform chart (Fig. 2). The diagram consists of the f ollow ing blocks:

The maximum probable time between two false c a l l connections can be estimated from s t a t i s t i c s . The s t a t i s t i c s carried out on Cairo's local exchange proved that t h i s time w i l l never exceed ten seconds. This time is very short and the p r o b a b i l i t y that the subscriber w i l l carry out the sinulat i o n of the reversal c r i t e r i o n during this short

i. 2. 3. 4. 5. 6. 37

Matching and protection c i r c u i t . Identification circuit. Decision c i r c u i t . Memory. P o l a r i t y - r e v e r s a l relay e x c i t a t i o n c i r c u i t . Synchronizer including 10.24 sec determination

38

M.M. Rateb and M.N. Elyousfi

Line input from the exchange

i polarityreversal ] relay

Line output to eubecrib~ e r ' s telepr-

inter

r~

' !

(i) Input

(2) I (3) I cont- | Matching& ( I Identlflca- H Decision rol un~ protection H ion clrcult circuit

[cct

from

H

~ t~)

Memory

circuit

t 5 V.stabilized to all c~rcuite

'

I Stabillzedi power suppl~ circuit i 6 V (8)

(6)

J Shaping circuit

I

.•Latch circuit

Automatic

initial

preset circuit

I

(zo)

O0

get •

0~

I C12) State decoder

Synchzonizerand time intervaldeterminationcircuit~ Fig. 1. Block Diagram of the Proposed Device. and i n i t i a l presetting c i r c u i t s . 7. D.C. power supply. The matching and protection c i r c u i t acts to match the input information delivered from the call-connection relay "in the control u n i t " with the set-up. This input (1) is d i s t o r t e d since i t is usually picked up from a relay contact. This input p r a c t i c a l l y contains many spikes due to relay bouncing. This w i l l lead to a false decision. The c i r c u i t acts to remove those spikes and d e l i v e r s to the i d e n t i f i c a t i o n c i r c u i t a d i s t o r t i o n l e s s sharp f r o n t edged and slow rear edged pulse (2). The f r o n t edge excites a monostable m u l t i v i b r a t o r (6) which sets anS.R, latch (7). The output of the latch c i r c u i t enables 50 Hz voltage (8) a f t e r being shaped by a Schmitt t r i g g e r (9) via a control gate. The output of the control gate ( i 0 ) is applied to a counter modulo 512. A f t e r a time i n t e r v a l of 10.24 s e c t h e s t a t e decoder output (12) resets the latch and 5 0 H z i s disabled. I f during t h i s 10.24 sec a new c a l l connection signal is received (2) the i d e n t i f i cation c i r c u i t w i l l have an output logic one (3) which is applied memory. The decision c i r c u i t generates a delayed clock pulse (4) applied s i multaneously with the output of the i d e n t i f i c a t i o n c i r c u i t to memory. The memory controls the p o l a r i t y reversal relay through an e x c i t a t i o n c i r c u i t . The memory stores

the l a s t s i t u a t i o n and in case of deciding a new reversal the stored s t a t e ( O o r l ) m u s t b e c h a n g e d . I f Qn represents the present state, Qn + I the next state, CP the input delayed clock and X the input from decision c i r c u i t , then the chara c t e r i s t i c equation w i l l be: Qn ÷ I = ~

Qn + X.CP ~1~,

I f synch. JK FF is used for r e a l i z a t i o n of t h i s c i r c u i t then Qn + i = ~

Qn + J.CP ~ .

Comparison of both equations y i e l d s J = K = X, which implies the a p p l i c a t i o n of the output of the i d e n t i f i c a t i o n c i r c u i t to short c i r c u i t e d J and K inputs and the output of decision c i r c u i t as a clock. Since most of the c i r c u i t s contained in the setup are storage c e l l s , and since i t frequently occurs that the AC mains supply is disconnected, t h i s c i r c u i t presets a l l the memory c i r c u i t s into known i n i t i a l conditions a f t e r the AC supply is again connected. Its action lasts f o r some microseconds, during which i n i t i a l conditions are re-established. 4. DESIGN CONSIDERATIONS The matching and protection c i r c u i t is shown in Fig. 3. I t consists of the ripple-removal c i r c u i t consisting of the diode and R.C. c i r c u i t , a

Automatic Removal of False Reversals in Telex Networks

39

be altered for other exchanges and control boxes. S t a t i s t i c s showed that the minimum time separat i o n between two successive pulses is approximately 1.5 sec. For a c i r c u i t which removes the r i p p l e s in the worst conditions the r e l a t i o n

f--X.

Tpmin ~ 5RfC must be f u l f i l l e d , where Tpmin is the minimum probable pulse duration which in our case is 80 msec, and Rf is the forward resistance of the selected diode. I t is also v a l i d that RrR (Tmi n - Tpmax) ~ 5C~--T-I~r , where Rr = the reverse resistance of the selected diode, Tpmax = the maximum probable pulse durat i o n , and Tmin = the minimum time i n t e r v a l between two successive pulses.

~/'I A A A A A / I ~.A { " V V V V V V ~. "

The f i r s t condition y i e l d s the maximum value of the condensator and the second one leads to the value of the resistance. The rise time in t h i s case w i l l be:

:

t r = 2.2RfC and the slope of the output w i l l be: S = Vcc/2.2RfC. Since the f o l l o w i n g stage is a Schmitt t r i g g e r i n v e r t e r , then in selecting the condensator, the slope of the output of the ripple-removal c i r c u i t must be steePer than that recommended by the manufacturer.

I I I

C11)

I I

(z2)

t Fig. 2. Waveform Chart. Schmitt t r i g g e r i n v e r t e r of type (7414) and a monostable (74123). Experiments showed that when false reversal takes place the line-connection relay energizes f o r a time i n t e r v a l Tp = 80-350 msec. This r e s u l t is achieved by t e s t i n g a large number of subs c r i b e r ' s l i n e s . However, these parameters could

I

Contro|u -- -

n

i

t

~

Monostable

-F

5. A FURTHER SOLUTION USING A MICROPROCESSOR I f the set-up is to be connected in the exchange, a microprocessor can help e f f e c t i v e l y in the solution of the false reversal problem. The setup including the microprocessor module acts to search for the reversal c r i t e r i o n over a l l subscribers l i n e s . The searching cycle w i l l be selected to be equal to the maximum probable i n terval between two successive pulses. The searching i n t e r v a l is divided into a number of samp l i n g i n t e r v a l s . The sampling i n t e r v a l must satisfy: Ts ~

I . . . . . . . . . . . . .

F

We introduce t h i s consideration as a guide f o r designers, when other types of systems are dealt w i t h . The monostable M.T,V. can be realized by one h a l f of the I.C. (74123) to produce a pulse of duration in the order of one microsecond. The i d e n t i f i c a t i o n c i r c u i t can be realized by a ring counter using the ~C (74295). The countermod512 is realized by two ICs of type (7493) plus one h a l f of the IC (7476) connected as a T. f l i p f l o p . The memory is realized by the second h a l f of the IC (7676).

I

Fig. 3. The matching and protection c i r c u i t .

Tpmin.

This allows the m u l t i p l e x i n g of a large number of subscribers but on the other hand t h i s is a l so l i m i t e d by the time required to execute the

40

M.M. Rateb and M.N. Elyousfi

microprogram. A multiplexer serves to supply a series of ones and zeros to a buffer memory. This information is ordered in the buffer such that a f t e r the end of each searching cycle a pattern concerning the situation of each subscriber's l i n e is available. The microprocessor now executes a program which recognizes i f the pattern received stands for a reversal or not. The output delivered, w i l l be the address of each l i n e and the decision i f reversal exists or not. A demultiplexer provided with a memory at the output, w i l l serve to control the p o l a r i t y - r e v e r s a l relays, of a l l the searched subscriber's lines.

REFERENCES

[ I ] Millman J. Halkias, Integrated Electronics: Analog and D i g i t a l Circuits and Systems (McGraw-Hill, 1972). [2] Peterson H i l l , Digital Systems, Hardware Organization and Design (John Wiley & Sons, 1973). [3] A.M. Abd-Alla and A.C. Metzer, Principles of Digital Computer Desing (PrenticeHall, 1976). [4] Nagle, David and Carrol, An Introduction to Computer Logic (Prentice Hall, 1975). [5] Daniel R. McGlynn, Microprocessor Technology, Architecture and Applications (John Wiley & Sons, 1976) [6] Laurence Altman, Microprocessors, Electronics Book Series (McGraw-Hill, 1975). M. Musta~a Rateb, Chief of Logic, Pulse and Digital Dept., Military Technical College, Cairo, is Brig. Staff. Professor. He received his B.S. degree in Electronic Engineering from MTC in 1964, the M.S. degree in Automatic Fault Finding from Brno University (CSSR) in 1968 and the Ph.D. in Digital Communication from Brno University in 1975. He is lecturer on the subjects computer logic, digital and indicator systems, in addition to leading M.S. works in coding and digital communication aspects. He is involved in solution of the problems connected with telecommunication networks, e.g. Telex for the welfare of the Egyptian Telecommunication Organization.

M. Nagi Elyousfi, Chief of Communication Dept., Military Technical College, Cairo, is Brig. Staff Professor. He received his B.S. degree in Electronic Engineering from MTC (Military Technical College) in 1965, the M.S. degree in Digital Communication from Brno University (CSSR) in 1968, and the Ph.D. in data computer communication from Brno University in 1975. Since then he has been in his department as lecturer on communication subjects (telephony, telex, data communication), leader of post-graduate courses and M.S. projects. He also participates in solving communication problems for the Egyptian Telecommunication Organization (solution of false polarity reversals problem on telex connection).He participates in communication planning for new towns and areas.