- Email: [email protected]
Bridgeless high voltage battery charger PFC rectifier
Renewable Energy xxx (2012) 1e8
Contents lists available at SciVerse ScienceDirect
Renewable Energy journal homepage: www.elsevier.com/locate/renene
Bridgeless high voltage battery charger PFC rectifier Aysha Kemadish AL-Kaabi a, Abbas A. Fardoun a, Esam H. Ismail b, * a b
Electrical Engineering Department, University of United Arab Emirates, P.O. Box 17555, Al-Ain, United Arab Emirates Electrical Engineering Department, College of Technological Studies, P.O. Box 35007, 36051 Al-Shaab, Kuwait
a r t i c l e i n f o
a b s t r a c t
Article history: Received 8 July 2012 Accepted 21 September 2012 Available online xxx
A high step-up bridgeless single phase acedc power factor correction (PFC) rectifier based on Cuk topology is proposed for high voltage battery charger application. The proposed topology is designed to operate in the discontinuous conduction mode (DCM) to achieve the following advantages: simple control, high power factor, soft switching at turn on and low harmonic content of the line input current. In addition, the proposed converter exhibits low inrush current and low magnetic emission rate similar to the conventional Cuk topology. Besides, all the inductors in converter can be coupled on the same magnetic core, hence high power density is also possible. Compared to the conventional Cuk converter, the proposed bridgeless topology has lower conduction losses and higher voltage gain. Simulation and experimental results are presented along with the theoretical analysis. Ó 2012 Elsevier Ltd. All rights reserved.
Keywords: Bridgeless rectifier Cuk converter Discontinuous conduction mode (DCM) Power factor correction (PFC) Total harmonic distortion (THD)
1. Introduction The dramatic growth of electronic equipment usage in recent years has resulted in a greater need to ensure that the line current harmonic content of any equipment connected to the ac mains meets regulatory standard such as (EN 61000-3-2). Active power factor correction (PFC) techniques based on basic dcedc converter topologies have been developed for high power factor and low input current harmonic ac/dc rectification [1e7]. However, conventional PFC rectifiers allow the current to flow through two bridge diodes in addition to the switching component of the converter. This results in higher conduction losses increasing the thermal stresses of the converter. Nowadays, considerable research has been directed towards maximizing the efficiency of the bridgeless rectifier. Since bridgeless PFC rectifier has lower number of semiconductor devices in the current path, it results in lower conduction losses, higher efficiency and cost saving. There are several bridgeless topologies that have been proposed such as buck, buckeboost, boost, single-ended primary inductance converter (SEPIC), and Cuk converters among others [8e24]. The bridgeless PFC boost rectifier is the dominant topology because of its low cost, inherent power factor capability and high performance in terms of efficiency, power factor and simplicity. However, the boost topology suffers from discontinuous output current resulting in higher electromagnetic emissions and
* Corresponding author. Tel.: þ965 99788776; fax: þ965 25381284. E-mail addresses: [email protected], [email protected] (E.H. Ismail).
high inrush current. Also, for input/output isolated applications, boost converter typically requires an additional dcedc stage because it is not easy to insert an isolation transformer [11e17]. Also, the boost topology has higher inrush current. Fig. 1 shows classical configuration of connecting utility power to the battery via a PFC converter. The charger must draw current at high power factor to maximize power from the ac mains. A relay is added in series to disconnect the system in case of system fault. Note that high inrush current increases the stresses on the relay connecting the load to the line voltage; typically a bulkier relay is added to handle the higher stresses. On the other hand, unlike the Boost converter, SEPIC and Cuk converters offer several advantages in the PFC applications such as easy implementation of transformer isolation, inherent inrush current limitations during the start-up and overload conditions, lower ripple on the input current and less electromagnetic interference (EMI). Recently, several bridgeless PFC rectifiers based on SEPIC topology have been presented [19e23]. The SEPIC topologies have discontinuous output current. A bridgeless Cuk PFC rectifier with continuous input/output topologies has been presented in Ref. [24] for low voltage applications. In this paper, a high step-up acedc rectifier with isolation and natural PFC capability is proposed for electric vehicle applications. The proposed bridgeless topology is derived from the Cuk converter as shown in Fig. 2a. The Cuk based bridgeless topology exhibits lower inrush current during start-up and overload condition by a factor of twenty [1,25]. Note that the Cuk and the Sepic converter are different from the boost converter with respect to their ability of limiting start-up inrush current. For the case of Cuk converter
0960-1481/$ e see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.renene.2012.09.050
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
2
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
Fig. 1. Block diagram of a battery charger.
Fig. 2a, the input inductor L1 is connected to the energy transfer capacitor C1 (or C2). This is different for the boost converter where L1 is connected to the output filter capacitor through the output rectifier. The value of C1 is a relatively low value and its value is determined by the magnitude of the switching voltage ripple. In practice, the value of C1 is chosen such that switching voltage ripple across it is about 20e30% of the output dc voltage value. Therefore the value of C1 it is almost three orders of magnitude smaller than the output filter capacitor. Hence, inrush current during start-up condition in the Cuk converter is reduced by a factor more than
Fig. 3. Topological stages for the rectifier of Fig. 2b during switching cycle Ts: (a) switch ON topology, (b) switch OFF topology, (c) DCM topology.
Fig. 2. (a) Proposed bridgeless Cuk rectifier. Equivalent circuits for the proposed rectifier: (b) during positive half line period, (c) during negative half line period of the input voltage.
30 times compared to the boost converter. Other advantages include low EMI emission due to its inputeoutput filter and higher efficiency as a result of the bridgeless design. In addition, the proposed rectifier reduces the complexity of the controller so that one control signal is required. Also, it reduces the conduction loss as well as the thermal stress on the semiconductor devices due to the lower number of semiconductors in the current path. The remainder of the paper is organized as follows. Principle of operation and theoretical analysis is given in Section 2. Design procedure is presented in Section 3. Simulation and experimental results are shown in Sections 4 and 5, respectively. Comparison between the proposed topology and the conventional Cuk is given in Section 6. The paper concludes with some final remarks, given in Section 7.
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
3
2. Principle of operations and theoretical analysis 2.1. Principle of operation The proposed bridgeless PFC Cuk rectifier is shown in Fig. 2a. Fig. 2b shows the circuit topology during the positive half line cycle of the line voltage with the elements Q1 and Do1 conducting during the positive cycle. On the other hand, during the negative half line cycle the current flows through Q2 and Do2 as shown in Fig. 2c. The energy transfer capacitor voltages over the ac line period (TL) are given by:
vC1 ðtÞ ¼ vac þ vo1 vC2 ðtÞ ¼ vac þ vo2
0 t TL 0 t TL
(1) (2)
Note that the capacitors voltages are charged up by input voltage and biased by half the output voltage. Due to the symmetry of the operations, only the positive half line cycle is analyzed over a switching cycle Ts. The analysis assumes that the converter is operating at a steady-state. In addition, the following assumptions are made: pure sinusoidal input voltage, ideal lossless components, line frequency is much less than the switching frequency, and capacitors C1 and C2 are large enough such that the voltage across them can be considered constant over the whole switching cycle. The output filter capacitors Co1 and Co2 are assumed to large enough such that the voltage across them is constant over the ac line cycle. 2.1.1. First stage: [to, t1] In this stage, the power switch Q1 is turned on and diode Do1 is reversed biased by the capacitor voltage (vC1 ), Fig. 3a. The output diode Do2 is reversed biased by capacitor voltage (vC2 ). The input voltage is connected to ground directly. The three inductors are charging up linearly at a rate that is proportional to the input voltage vac. The rate of increase of the three inductor currents are given by
diLn vac ¼ ; n ¼ 1; o1; o2 dt Ln
(3)
This stage ends when switch Q1 is turned off, initiating the next stage. 2.1.2. Second stage: [t1, t2] The second stage starts at the instant t1 where the Q1 is turned off and diode Do1 begins to conduct, Fig. 3b. During this stage, the three inductor currents decrease linearly at a rate that is proportional to the output voltage Vo. The three inductors’ currents are given by
diLn Vo ¼ ; n ¼ 1; o1; o2 dt 2Ln
(4)
The stage ends when the diode Do1 is turned off; in other words, iLo1 ¼ 0. 2.1.3. Third stage: [t2, t3] The freewheeling stage is defined as the stage where both the switch Q1 and diode Do1 are in their OFF state as shown in Fig. 3c. The three inductors behave as current sources, which keep the currents constant. Hence, the voltage across the three inductors is zero. The converter remains in this stage until the switch Q1 is turned ON again initiating a new switching period. The length of this interval is (d3Ts) is given by:
d3 Ts ¼ ð1 d1 d2 ÞTs
(5)
Fig. 4. Theoretical inductors current waveforms over one switching cycle Ts during the positive half-cycle of the input voltage.
where d1, d2 and d3 are defined as the duty cycle for the stages 1 through 3, respectively. Fig. 4 shows the theoretical DCM current waveforms for the three inductors, switch Q1, and diode Do1 over one switching cycle and during the positive half-cycle of the input voltage. It can be seen from Fig. 4 that the raising and the falling slope of the three inductors currents are proportional to the input voltage (vac) and to the output voltage (Vo), respectively. Hence, they can be magnetically coupled into a common magnetic core. Accordingly, the size, weight, and cost of the proposed Cuk converter can be reduced and the efficiency can be further improved. 2.2. Steady-state analysis By applying the volt second balance on the inductors, the input to output voltage ratio can be expressed as:
d2 ¼
2d1 sin ðutÞ M
(6)
where M ¼ Vo/Vm is the voltage conversion ratio, Vo is the average output voltage, Vm is to the peak amplitude of the input voltage, and u is the line angular frequency. 2.3. Voltage conversion ratio M (d1, K) The input power of the converter can be expressed as,
hPin ðtÞiTL =2 ¼
2 TL
TL =2 Z
vac hiac ðtÞiTS dt
(7)
0
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
4
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
Using the power balance principle, the output to input current ratio can be expressed as follows by using Eq. (6),
angle (ut). Therefore, the minimum and maximum values of Kcrit are given by
io d ¼ 2 iac 2d1
Kcritmin <
(8)
Referring to the waveforms in Fig. 4, the average input current over one switching cycle is
< iac >TS ¼ < iL1 >TS
vac ¼ d T ½d þ d2 þ IX 2L1 1 S 1
(9)
Furthermore, the average output currents over one switching cycle can be written as:
< iLo1 >TS ¼
vac d T ½d þ d2 2Lo1 1 S 1
(10)
< iLo2 >TS ¼
vac d T ½d þ d2 IX 2Lo2 1 S 1
(11)
where, < iLo1 >TS þ < iLo2 >TS ¼ 2io . By substituting the sum of the three inductor currents waveforms in Eq. (8), the average input current over one switching cycle can be expressed as
iac
d2 Ts ¼ 1 vac 2Leq
(12)
where 1/Leq ¼ (1/L1) þ (1/Lo1) þ (1/Lo2). The input current as a function of the emulated input resistance (Re) of the converter can be written as
iac ¼
vac Re
(13)
where
Re ¼
Kcritmax <
1 2M 2
(19)
(20)
respectively. Therefore, for values of K < Kcrit_min, the converter always operates in DCM and it operates in CCM when for values of K > Kcrit_max. However, for values of Kcrit_min < K < Kcrit_max, then the converter operates in both modes, i.e. in DCM near the zero crossing of the input line voltage and in CCM near the maximum value of the input line voltage. 2.5. Large signal model According to Eq. (13), the input port of the proposed rectifier can be modeled by a pure resistor as shown in Fig. 5, whereas the output port can be modeled according to the following relation.
Pout ¼
2 Vac V2 ¼ o Re RL
(21)
where Vac is the root-mean-square (rms) value of the input voltage vac. From (21), the voltage conversion ratio M can be expressed by,
sffiffiffiffiffiffiffiffi RL M ¼ 2Re
(22)
2.6. Stresses
2Leq d21 TS
(14)
The input current iac is in-phase with input voltage vac at any given operating point; thus the input current obeys Ohm’s law as shown in Eq. (13), hence unity power factor is obtained. The voltage conversion ratio as a function of the conduction parameter K is found by substituting Eq. (12) into (7) and using converter power balance,
d1 ffi Mðd1 ; KÞ ¼ pffiffiffiffiffiffi 2K
(15)
where the dimensionless parameter K can be expressed as:
K ¼
1 2ð2 þ MÞ2
2Leq RL TS
(16)
2.4. Critical conduction parameter (Kcrit) To operate in DCM, The following inequalities must be held:
d1 þ d2 < 1
The voltage and current stresses of the converter components are shown in Table 1. Voltages and currents are normalized with respect to the output voltage Vo and load current Io, respectively. The voltage stress of the switches is illustrated in Fig. 6. Unlike the conventional Cuk converter, Fig. 6 shows that the switch Q1 and the output diode Do1 are not subjected to a high voltage stress. Therefore, a power MOSFET with low RDS-ON and Schottky diodes can be utilized in the proposed rectifier to further minimize the conduction losses. 3. Design procedure The converter can be designed for a given operating point (vac, Vo, output power and switching frequency) by using the following procedure: - The critical conduction parameter (Kcrit) can be evaluated from Eq. (18). - Select K < Kcrit to ensure DCM operation. - The duty cycle is calculated from Eq. (15).
(17)
By manipulating Eqs. (5), (15) and (16) and substituting in Eq. (17), the following condition must be satisfied for DCM operation,
Kcrit <
1 2ð2sin ut þ MÞ2
(18)
where the dimensionless parameter Kcrit is the critical value of K. Note that Eq. (18) shows that the value of Kcrit depends on the line
Fig. 5. Averaged circuit model for the proposed rectifier in DCM (all inductors operates in DCM.).
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8 Table 1 Normalized current and voltage stresses. Component
Voltage 2þM 2M 2þM 2M 2þM 2M 1 2 1 2 1 2
Q1, Q2 Do1, Do2 C1 , C2 Co1, Co2 L1 Lo1, Lo2
-
Co1 ¼ Co2 ¼ Current
4. Simulation results M 3 2 1 2 M 3 2
3.1. Energy transfer capacitors design To ensure the input characteristics of the proposed converter near-perfect PFC, the capacitors C1 and C2 must be carefully selected. The selections of these capacitors depend on two constraints. First, the voltages across C1 and C2 must follow the input voltage profile within a line cycle [1]. Second, the resonant frequency (fr) of C1, C2, L1, Lo1 and Lo2 must be much greater than the line frequency. The C1 and C2 designed equation is given by:
1 ð2pfr Þ2 ðL1 þ Lo1 Þ
(23)
3.2. Output capacitors design Output capacitors Co1 and Co2 are utilized to filter the load voltage. Thus, the value of the output capacitors is inversely proportion to the output voltage ripple Dvo as shown in Eq. (24). The output capacitor Co1 and Co2 values which are required to maintain a peakepeak output voltage ripple Dvo is given by
Co1 ¼ Co2
1 ¼ Dvo
3T Z L =8
iLo1 Io dt
(24)
TL =8
where Io is the output load current. Substituting the values of Io and iLo1 and solving the integration yields,
Fig. 6. Semiconductor voltage stress.
(25)
M
L1 can be obtained considering the maximum current ripple. Evaluate Leq from Eq. (16). Evaluate the output inductor Lo1 and Lo2. The converter capacitors selection is discussed below.
C1 ¼ C2 ¼
TL Vo 1 1 1 1 þ RL 2Dvo Re M 2 p 2
5
The proposed rectifier is designed for the following power stage specifications: peak input voltage of 100 V at 50 Hz, output voltage of 250 V, switching frequency of 50 kHz, and output power of 125 W. In addition, actual semiconductor devices are used in the simulation; STTH1003SB (300 V) are used for the diodes and irfb4332pbf (250 V with RDS-ON ¼ 29 mU) for the active power switches. Moreover, taking also into account the conduction losses associated with the reactive components, an equivalent series resistor (ESR) of 50 mU is placed in series with all the inductors and capacitors in the circuit. The circuit components used in the simulation is chosen as follows: L1 ¼ 2 mH, Lo1 ¼ Lo2 ¼ 50 mH, C1 ¼ C2 ¼ 1 mF, Co1 ¼ Co2 ¼ 400 mF. The switches duty cycle d1 is set to 0.25 according to Eq. (15). Simulation studies were performed using ORCAD software package, to verify the analysis results. The input voltage and current are in-phase as shown in Fig. 7. The percent of the total harmonic distortion (%THD) in the line current is less the 1% and the simulated efficiency is about 95.7%. Fig. 7 also shows the output voltage with peakepeak voltage ripple equal to 8 V with an average dc value close to 250 V. It should be mentioned here that the output voltage ripple can be further reduced by connecting an additional small capacitor across the load terminals. Fig. 8a shows the switch Q1 as well as the output diode (Do1) currents over several switching periods. Fig. 8b shows the waveforms of the three inductors’ currents over several switching periods at peak input voltage which correctly demonstrates the DCM operating mode. Fig. 8b also shows that the three inductors’ currents have proportional slopes over the three different stages during a switching cycle. Thus, the three inductors can be coupled which lead to lower costs and smaller size. In addition, the three inductors are being charged by the input voltage when the Q1 is conducting, while they are discharging through the output capacitors during diode Do1 conduction. Fig. 8c and d shows the voltage waveforms across the energy transfer capacitors and the output filter capacitors, respectively. A very good agreement can be seen between simulation and the theoretical predictions. In order to demonstrate the effect of coupling the inductors on the input line current, the circuit of Fig. 2a has been simulated with coupled inductors. In this case, the output inductors Lo1 and Lo2 are both coupled to the input inductor L1, but that Lo1 and Lo2 are not directly coupled. Moreover, in the proposed topology, it is preferred that inductors Lo1 and Lo2 have equal values so that they carry the same ripple current. In this case, it can be shown that “near zero current ripples” in the input inductor L1 can be obtained if the following condition is met:
Fig. 7. Simulated waveforms for the proposed rectifier in DCM (input voltage vac, input current iac, and output voltage Vo).
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
6
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
Fig. 9. Simulated waveforms for the proposed rectifier in DCM: (a) uncoupled inductors, (b) coupled inductors.
the generated EMI noise level is greatly minimized as well as the requirement for the input filtering.
5. Experimental results
Fig. 8. Simulated waveforms for the proposed rectifier in DCM: (a) switch current iQ1 and diode current iDo1 , (b) inductors’ currents iL1 , iLo1 , and iLo2 , (c) energy transfer capacitors’ voltages vC1 and vC2 , and (d) output filter capacitors’ voltages vo1 and vo2.
k1o1 ¼ k1o2 ¼
1 2
sffiffiffiffiffiffiffi Lo1 L1
with Lo1 < L1
(26)
where k1o1 and k1o2 represent the coupling coefficient between L1eLo1 and L1eLo2, respectively. In order to verify the “near zero current ripples” in the input line current, the circuit of Fig. 2a has been simulated for the same power stage parameters and components values except for the values of the three inductors. The values of the coupled inductors used are L1 ¼ 500 mH, Lo1 ¼ Lo2 ¼ 50 mH. Thus, the values of both coupling coefficients k1o1 and k1o2 are set to 0.16. The simulated input voltage and input current waveforms for the uncoupled and coupled case are shown in Fig. 9a and b, respectively. It is evident from Fig. 9b that the high frequency switching ripples’ magnitude in the input current (iL1 ) is greatly reduced due to the coupling of the three inductors. Consequently,
The bridgeless DCM Cuk rectifier prototype test is validated at the same operating point as the simulation. The circuit components values are the same as those used in the simulation except for the active switches Q1 and Q2. Due to availability during prototype assembly, MOSFETs STY60NM50 from STMicroelectronics were used. A small high frequency input filter is used at the input port of the rectifier to bypass the high frequency current so that the input current consists of the low frequency part only. Fig. 10 shows the input current and line voltage. It can be seen that the line current and phase voltage are in phase. Fig. 11 depicts the waveforms of the three inductors currents (iL1 , iLo1 , and iLo2 ) during a few switching periods, which correctly demonstrates the DCM operating mode. The energy capacitor voltage waveforms (vC1 and vC2 ) are shown in Fig. 12a. It is evident that the capacitor voltages follow the input voltage and they are shifted up by half the output voltage as explained in Eqs. (1) and (2). Fig. 12b illustrates the output filter capacitor voltages (vo1 and vo2). It is clear from Fig. 12b that the voltages vo1 and vo2 are equal to half of the output load voltage. The experimental waveforms are obtained in the absence of any snubber circuits and without any special circuit layout. The efficiency at full load is close to 93.3%.
6. Conventional Cuk versus the proposed Cuk rectifier The circuit components in both the conventional PFC Cuk and the proposed bridgeless PFC Cuk have similar current stresses. However, the proposed Cuk subjects the reactive components and the semiconductor switches to a lower rms current stress compared to their counterparts in the conventional Cuk topology. On the other hand, the switching performance of the two converters remains mainly the same, which results in similar switching losses. In contrast, as shown in Table 2, the input current in the proposed Cuk flows through fewer power semiconductor devices compared to the conventional Cuk PFC. Thus, efficiency
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
7
Fig. 10. Experimental waveforms for the proposed rectifier of Fig. 2a (input voltage vac and input current iac).
improvement by using proposed Cuk mainly relies on the conduction loss difference between the two topologies. Regarding the voltage stress, as mentioned before, the voltage stresses on the switches (Q1 and Q2) and the diodes (Do1 and Do2) of the proposed converter is Vm þ Vo1 which is less than that for the conventional Cuk converter (Vm þ 2Vo1). Therefore, these reduced voltage stresses can make the proposed converter utilize a power MOSFET with low RDS-ON and Schottky diodes to minimize reverse recovery of diodes. As a result, the overall circuit efficiency can be further enhanced. It should be mentioned here that the proposed rectifier requires an additional floating switch which requires an additional gating circuitry. An efficiency comparison between the conventional and the proposed Cuk rectifiers is performed based on simulation results. In this comparison, both rectifiers are assumed to operate in DCM with the same operating conditions and parameters. The simulated efficiency includes conduction and switching losses of the semiconductor devices, inductors’ copper losses, as well as capacitors ESR losses. Furthermore, Pspice actual semiconductor models have been used to simulate the semiconductor devices: STTH5L06 (600 V) ultrafast fast high voltage rectifier for the diodes and STY60NM50 (500 V with RDSON ¼ 45 mU) for the power MOSFET(s). According to the simulation results, both rectifiers offer low input current THD which is 1.5% for the conventional Cuk and it is 0.7% for the proposed rectifier. However, the simulated efficiency for the conventional Cuk is about 92.5% while it is 94.7% for the proposed Cuk rectifier. Note that as mentioned in Section 4, the simulated efficiency for the proposed rectifier is higher than 94.7%. This is mainly due to the low ON resistance of the power MOSFETs (RDSON ¼ 29 mU).
Fig. 12. Experimental waveforms for the proposed rectifier of Fig. 2a. (a) Energy transfer capacitors’ voltages vC1 and vC2 , (b) output filter capacitors’ voltages vo1 and vo2. Table 2 Comparison between conventional and bridgeless Cuk rectifiers in DCM mode.
Diodes Switch Current conduction path in stage 1 Current conduction path in stage 2 Current conduction path in stage 3 Number of components Integrated magnetic Driver circuit complexity Ground
Conventional Cuk
Proposed Cuk rectifier
4 slow and 1 fast 1 2 slow diodes and 1 switch 3 diodes (2 slow and 1 fast) 2 slow diodes
2 fast 2 1 body diode and 1 switch 1 fast diode
10 One core for 2 inductors 1 non-floating
11 One core for 3 inductors 1 floating and 1 non-floating Floating
Non-floating
e
7. Conclusion
Fig. 11. Experimental inductors’ currents waveforms iL1 , iLo1 , and iLo2 for the proposed rectifier of Fig. 2a.
In this paper, a high step-up bridgeless Cuk acedc rectifier has been presented. The proposed high step-up bridgeless Cuk rectifier has been analyzed in DCM mode. The gain of the converter as a function of the control signal has been derived. The constraints for operation in DCM have been presented. The current and voltage stresses of the proposed topology are given. It was shown that the voltage stresses on the power switch and the output diode are lower than that of the conventional Cuk converter. The capability of the proposed topology has been built and tested at prototype level. The experimental results are in good agreement with the theoretical and simulation results. Efficiency improvement over the conventional Cuk PFC rectifier is demonstrated by simulation results. The improvement in the conversion efficiency is more than 3% at full load.
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
8
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
Acknowledgments This work was supported in part by the Emirates Foundation in the United Arab Emirate under contract # 2011/158.
References [1] Brkovic M, Cuk S. Input current shaper using Cuk converter. In: IEEE telecommunications energy conference, INTELEC 1992; 1992, p. 532e539. [2] Simonetti DSL, Sebastian J, Uceda J. The discontinuous conduction mode SEPIC and Cuk power factor preregulators: analysis and design. IEEE Trans Ind Electron 1997;44(5):630e7. [3] Jingquan C, Maksimovic D, Erickson RW. Analysis and design of a low-stress buck-boost converter in universal-input PFC applications. IEEE Trans Power Electron 2006;21(2):320e9. [4] Garinto D. A new zero-ripple boost converter with separate inductors for power factor correction. In: IEEE power electronics specialists conference, PESC 2007 record; 2007, p. 1309e1313. [5] Lázaro A, Barrado A, Sanz M, Salas V, Olías E. New power factor correction ACe DC converter with reduced storage capacitor voltage. IEEE Trans Ind Electron 2007;54(1):384e97. [6] Fardoun AA, Ismail EH. Non-isolated single stage PFC rectifier for wide-input large step-down. Int J Power Electron 2010;2(4):412e27. [7] Wu X, Yang J, Zhang J, Xu M. Design considerations of soft-switched buck PFC converter with constant on-time (COT) control. IEEE Trans Power Electron 2011;26(11):3144e52. [8] Oruganti R, Palaniapan M. Inductor voltage control of buck-type single-phase AC-DC converter. IEEE Trans Power Electron 2000;15(2):411e7. [9] Wei W, Hongpeng L, Shigong J, Dianguo X. A novel bridgeless buck-boost PFC converter. In: IEEE power electronics specialists conference, PESC 2008 record; 2008, p. 1304e08. [10] Mok K, Lai Y, Loo K. A single-stage bridgeless power-factor-correction rectifier based on flyback topology. In: IEEE international telecommunications energy conference, INTELEC 2011 record; 2011, p. 1e6. [11] Jang Y, Jovanovic MM. Bridgeless high-power-factor buck converter state-ofthe-art. IEEE Trans Ind Electron 2011;26(2):602e11.
[12] Jovanovic MM, Jang Y. State-of-the-art, single-phase, active power-factorcorrection techniques for high-power applications e an overview. IEEE Trans Ind Electron 2005;52(3):701e8. [13] Huber L, Jang Y, Jovanovic MM. Performance evaluation of bridgeless PFC boost rectifiers. IEEE Trans Power Electron 2008;23(3):1381e90. [14] Choi W-Y, Kwon J-M, Kim E-H, Lee J-J, Kwon BH. Bridgeless boost rectifier with low conduction losses and reduced diode reverse-recovery problems. IEEE Trans Ind Electron 2007;54(2):769e80. [15] Su B, Zhang J, Lu Z. Totem-pole boost bridgeless PFC rectifier with simple zero current detection and full range ZVS operating at the boundary of DCM/CCM. IEEE Trans Power Electron 2011;26(2):427e35. [16] Tsai H-Y, Hsia T-H, Chen D. A family of zero-voltage-transition bridgeless power-factor-correction circuits with a zero-current-switching auxiliary switch. IEEE Trans Ind Electron 2011;58(5):1848e55. [17] Su B, Lu Z. An interleaved totem-pole boost bridgeless rectifier with reduced reverse-recovery problems for power factor correction. IEEE Trans Power Electron 2010;25(6):1406e15. [18] Chen Z, Xu J, Zhou G, Zhang F. Analysis of bridgeless pseudo-boost PFC converter. In: IEEE international symposium on industrial electronics, ISIE 2012; 2012, p. 189e193. [19] Ismail EH. Bridgeless SEPIC rectifier with unity power factor and reduced conduction losses. IEEE Trans Ind Electron 2009;56(4):1147e57. [20] Sahid MR, Yatim AM. Modelling and simulation of a new bridgeless SEPIC power factor correction circuit. Simulat Model Pract Theory 2011;19(2):599e611. [21] De Melo PF, Gules R, Romaneli EFR, Annunziato RC. A modified SEPIC converter for high power factor rectifier and universal input voltage applications. IEEE Trans Power Electron 2010;25(5):310e21. [22] Sabzali AJ, Ismail EH, Al-Saffar MA, Fardoun AA. New bridgeless DCM SEPIC and Cuk PFC rectifiers with low conduction and switching losses. IEEE Trans Ind Appl 2011;47(2):873e81. [23] Mahdavi M, Farzanehfard H. Bridgeless SEPIC PFC rectifier with reduced components and conduction losses. IEEE Trans Ind Electron 2011;58(9): 4153e60. [24] Fardoun AA, Ismail EH, Sabzali AJ, Al-Saffar MA. New efficient bridgeless Cuk rectifiers for PFC applications. IEEE Trans Power Electron 2012;27(7):3292e 301. [25] Jayaram N, Maksimovic D. Power factor correctors based on coupled inductor SEPIC and Cuk converters with nonlinear-carrier control. In: IEEE applied power electronics conference and exposition, APEC 1998; 1998, p. 468e74.
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
Contents lists available at SciVerse ScienceDirect
Renewable Energy journal homepage: www.elsevier.com/locate/renene
Bridgeless high voltage battery charger PFC rectifier Aysha Kemadish AL-Kaabi a, Abbas A. Fardoun a, Esam H. Ismail b, * a b
Electrical Engineering Department, University of United Arab Emirates, P.O. Box 17555, Al-Ain, United Arab Emirates Electrical Engineering Department, College of Technological Studies, P.O. Box 35007, 36051 Al-Shaab, Kuwait
a r t i c l e i n f o
a b s t r a c t
Article history: Received 8 July 2012 Accepted 21 September 2012 Available online xxx
A high step-up bridgeless single phase acedc power factor correction (PFC) rectifier based on Cuk topology is proposed for high voltage battery charger application. The proposed topology is designed to operate in the discontinuous conduction mode (DCM) to achieve the following advantages: simple control, high power factor, soft switching at turn on and low harmonic content of the line input current. In addition, the proposed converter exhibits low inrush current and low magnetic emission rate similar to the conventional Cuk topology. Besides, all the inductors in converter can be coupled on the same magnetic core, hence high power density is also possible. Compared to the conventional Cuk converter, the proposed bridgeless topology has lower conduction losses and higher voltage gain. Simulation and experimental results are presented along with the theoretical analysis. Ó 2012 Elsevier Ltd. All rights reserved.
Keywords: Bridgeless rectifier Cuk converter Discontinuous conduction mode (DCM) Power factor correction (PFC) Total harmonic distortion (THD)
1. Introduction The dramatic growth of electronic equipment usage in recent years has resulted in a greater need to ensure that the line current harmonic content of any equipment connected to the ac mains meets regulatory standard such as (EN 61000-3-2). Active power factor correction (PFC) techniques based on basic dcedc converter topologies have been developed for high power factor and low input current harmonic ac/dc rectification [1e7]. However, conventional PFC rectifiers allow the current to flow through two bridge diodes in addition to the switching component of the converter. This results in higher conduction losses increasing the thermal stresses of the converter. Nowadays, considerable research has been directed towards maximizing the efficiency of the bridgeless rectifier. Since bridgeless PFC rectifier has lower number of semiconductor devices in the current path, it results in lower conduction losses, higher efficiency and cost saving. There are several bridgeless topologies that have been proposed such as buck, buckeboost, boost, single-ended primary inductance converter (SEPIC), and Cuk converters among others [8e24]. The bridgeless PFC boost rectifier is the dominant topology because of its low cost, inherent power factor capability and high performance in terms of efficiency, power factor and simplicity. However, the boost topology suffers from discontinuous output current resulting in higher electromagnetic emissions and
* Corresponding author. Tel.: þ965 99788776; fax: þ965 25381284. E-mail addresses: [email protected], [email protected] (E.H. Ismail).
high inrush current. Also, for input/output isolated applications, boost converter typically requires an additional dcedc stage because it is not easy to insert an isolation transformer [11e17]. Also, the boost topology has higher inrush current. Fig. 1 shows classical configuration of connecting utility power to the battery via a PFC converter. The charger must draw current at high power factor to maximize power from the ac mains. A relay is added in series to disconnect the system in case of system fault. Note that high inrush current increases the stresses on the relay connecting the load to the line voltage; typically a bulkier relay is added to handle the higher stresses. On the other hand, unlike the Boost converter, SEPIC and Cuk converters offer several advantages in the PFC applications such as easy implementation of transformer isolation, inherent inrush current limitations during the start-up and overload conditions, lower ripple on the input current and less electromagnetic interference (EMI). Recently, several bridgeless PFC rectifiers based on SEPIC topology have been presented [19e23]. The SEPIC topologies have discontinuous output current. A bridgeless Cuk PFC rectifier with continuous input/output topologies has been presented in Ref. [24] for low voltage applications. In this paper, a high step-up acedc rectifier with isolation and natural PFC capability is proposed for electric vehicle applications. The proposed bridgeless topology is derived from the Cuk converter as shown in Fig. 2a. The Cuk based bridgeless topology exhibits lower inrush current during start-up and overload condition by a factor of twenty [1,25]. Note that the Cuk and the Sepic converter are different from the boost converter with respect to their ability of limiting start-up inrush current. For the case of Cuk converter
0960-1481/$ e see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.renene.2012.09.050
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
2
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
Fig. 1. Block diagram of a battery charger.
Fig. 2a, the input inductor L1 is connected to the energy transfer capacitor C1 (or C2). This is different for the boost converter where L1 is connected to the output filter capacitor through the output rectifier. The value of C1 is a relatively low value and its value is determined by the magnitude of the switching voltage ripple. In practice, the value of C1 is chosen such that switching voltage ripple across it is about 20e30% of the output dc voltage value. Therefore the value of C1 it is almost three orders of magnitude smaller than the output filter capacitor. Hence, inrush current during start-up condition in the Cuk converter is reduced by a factor more than
Fig. 3. Topological stages for the rectifier of Fig. 2b during switching cycle Ts: (a) switch ON topology, (b) switch OFF topology, (c) DCM topology.
Fig. 2. (a) Proposed bridgeless Cuk rectifier. Equivalent circuits for the proposed rectifier: (b) during positive half line period, (c) during negative half line period of the input voltage.
30 times compared to the boost converter. Other advantages include low EMI emission due to its inputeoutput filter and higher efficiency as a result of the bridgeless design. In addition, the proposed rectifier reduces the complexity of the controller so that one control signal is required. Also, it reduces the conduction loss as well as the thermal stress on the semiconductor devices due to the lower number of semiconductors in the current path. The remainder of the paper is organized as follows. Principle of operation and theoretical analysis is given in Section 2. Design procedure is presented in Section 3. Simulation and experimental results are shown in Sections 4 and 5, respectively. Comparison between the proposed topology and the conventional Cuk is given in Section 6. The paper concludes with some final remarks, given in Section 7.
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
3
2. Principle of operations and theoretical analysis 2.1. Principle of operation The proposed bridgeless PFC Cuk rectifier is shown in Fig. 2a. Fig. 2b shows the circuit topology during the positive half line cycle of the line voltage with the elements Q1 and Do1 conducting during the positive cycle. On the other hand, during the negative half line cycle the current flows through Q2 and Do2 as shown in Fig. 2c. The energy transfer capacitor voltages over the ac line period (TL) are given by:
vC1 ðtÞ ¼ vac þ vo1 vC2 ðtÞ ¼ vac þ vo2
0 t TL 0 t TL
(1) (2)
Note that the capacitors voltages are charged up by input voltage and biased by half the output voltage. Due to the symmetry of the operations, only the positive half line cycle is analyzed over a switching cycle Ts. The analysis assumes that the converter is operating at a steady-state. In addition, the following assumptions are made: pure sinusoidal input voltage, ideal lossless components, line frequency is much less than the switching frequency, and capacitors C1 and C2 are large enough such that the voltage across them can be considered constant over the whole switching cycle. The output filter capacitors Co1 and Co2 are assumed to large enough such that the voltage across them is constant over the ac line cycle. 2.1.1. First stage: [to, t1] In this stage, the power switch Q1 is turned on and diode Do1 is reversed biased by the capacitor voltage (vC1 ), Fig. 3a. The output diode Do2 is reversed biased by capacitor voltage (vC2 ). The input voltage is connected to ground directly. The three inductors are charging up linearly at a rate that is proportional to the input voltage vac. The rate of increase of the three inductor currents are given by
diLn vac ¼ ; n ¼ 1; o1; o2 dt Ln
(3)
This stage ends when switch Q1 is turned off, initiating the next stage. 2.1.2. Second stage: [t1, t2] The second stage starts at the instant t1 where the Q1 is turned off and diode Do1 begins to conduct, Fig. 3b. During this stage, the three inductor currents decrease linearly at a rate that is proportional to the output voltage Vo. The three inductors’ currents are given by
diLn Vo ¼ ; n ¼ 1; o1; o2 dt 2Ln
(4)
The stage ends when the diode Do1 is turned off; in other words, iLo1 ¼ 0. 2.1.3. Third stage: [t2, t3] The freewheeling stage is defined as the stage where both the switch Q1 and diode Do1 are in their OFF state as shown in Fig. 3c. The three inductors behave as current sources, which keep the currents constant. Hence, the voltage across the three inductors is zero. The converter remains in this stage until the switch Q1 is turned ON again initiating a new switching period. The length of this interval is (d3Ts) is given by:
d3 Ts ¼ ð1 d1 d2 ÞTs
(5)
Fig. 4. Theoretical inductors current waveforms over one switching cycle Ts during the positive half-cycle of the input voltage.
where d1, d2 and d3 are defined as the duty cycle for the stages 1 through 3, respectively. Fig. 4 shows the theoretical DCM current waveforms for the three inductors, switch Q1, and diode Do1 over one switching cycle and during the positive half-cycle of the input voltage. It can be seen from Fig. 4 that the raising and the falling slope of the three inductors currents are proportional to the input voltage (vac) and to the output voltage (Vo), respectively. Hence, they can be magnetically coupled into a common magnetic core. Accordingly, the size, weight, and cost of the proposed Cuk converter can be reduced and the efficiency can be further improved. 2.2. Steady-state analysis By applying the volt second balance on the inductors, the input to output voltage ratio can be expressed as:
d2 ¼
2d1 sin ðutÞ M
(6)
where M ¼ Vo/Vm is the voltage conversion ratio, Vo is the average output voltage, Vm is to the peak amplitude of the input voltage, and u is the line angular frequency. 2.3. Voltage conversion ratio M (d1, K) The input power of the converter can be expressed as,
hPin ðtÞiTL =2 ¼
2 TL
TL =2 Z
vac hiac ðtÞiTS dt
(7)
0
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
4
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
Using the power balance principle, the output to input current ratio can be expressed as follows by using Eq. (6),
angle (ut). Therefore, the minimum and maximum values of Kcrit are given by
io d ¼ 2 iac 2d1
Kcritmin <
(8)
Referring to the waveforms in Fig. 4, the average input current over one switching cycle is
< iac >TS ¼ < iL1 >TS
vac ¼ d T ½d þ d2 þ IX 2L1 1 S 1
(9)
Furthermore, the average output currents over one switching cycle can be written as:
< iLo1 >TS ¼
vac d T ½d þ d2 2Lo1 1 S 1
(10)
< iLo2 >TS ¼
vac d T ½d þ d2 IX 2Lo2 1 S 1
(11)
where, < iLo1 >TS þ < iLo2 >TS ¼ 2io . By substituting the sum of the three inductor currents waveforms in Eq. (8), the average input current over one switching cycle can be expressed as
iac
d2 Ts ¼ 1 vac 2Leq
(12)
where 1/Leq ¼ (1/L1) þ (1/Lo1) þ (1/Lo2). The input current as a function of the emulated input resistance (Re) of the converter can be written as
iac ¼
vac Re
(13)
where
Re ¼
Kcritmax <
1 2M 2
(19)
(20)
respectively. Therefore, for values of K < Kcrit_min, the converter always operates in DCM and it operates in CCM when for values of K > Kcrit_max. However, for values of Kcrit_min < K < Kcrit_max, then the converter operates in both modes, i.e. in DCM near the zero crossing of the input line voltage and in CCM near the maximum value of the input line voltage. 2.5. Large signal model According to Eq. (13), the input port of the proposed rectifier can be modeled by a pure resistor as shown in Fig. 5, whereas the output port can be modeled according to the following relation.
Pout ¼
2 Vac V2 ¼ o Re RL
(21)
where Vac is the root-mean-square (rms) value of the input voltage vac. From (21), the voltage conversion ratio M can be expressed by,
sffiffiffiffiffiffiffiffi RL M ¼ 2Re
(22)
2.6. Stresses
2Leq d21 TS
(14)
The input current iac is in-phase with input voltage vac at any given operating point; thus the input current obeys Ohm’s law as shown in Eq. (13), hence unity power factor is obtained. The voltage conversion ratio as a function of the conduction parameter K is found by substituting Eq. (12) into (7) and using converter power balance,
d1 ffi Mðd1 ; KÞ ¼ pffiffiffiffiffiffi 2K
(15)
where the dimensionless parameter K can be expressed as:
K ¼
1 2ð2 þ MÞ2
2Leq RL TS
(16)
2.4. Critical conduction parameter (Kcrit) To operate in DCM, The following inequalities must be held:
d1 þ d2 < 1
The voltage and current stresses of the converter components are shown in Table 1. Voltages and currents are normalized with respect to the output voltage Vo and load current Io, respectively. The voltage stress of the switches is illustrated in Fig. 6. Unlike the conventional Cuk converter, Fig. 6 shows that the switch Q1 and the output diode Do1 are not subjected to a high voltage stress. Therefore, a power MOSFET with low RDS-ON and Schottky diodes can be utilized in the proposed rectifier to further minimize the conduction losses. 3. Design procedure The converter can be designed for a given operating point (vac, Vo, output power and switching frequency) by using the following procedure: - The critical conduction parameter (Kcrit) can be evaluated from Eq. (18). - Select K < Kcrit to ensure DCM operation. - The duty cycle is calculated from Eq. (15).
(17)
By manipulating Eqs. (5), (15) and (16) and substituting in Eq. (17), the following condition must be satisfied for DCM operation,
Kcrit <
1 2ð2sin ut þ MÞ2
(18)
where the dimensionless parameter Kcrit is the critical value of K. Note that Eq. (18) shows that the value of Kcrit depends on the line
Fig. 5. Averaged circuit model for the proposed rectifier in DCM (all inductors operates in DCM.).
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8 Table 1 Normalized current and voltage stresses. Component
Voltage 2þM 2M 2þM 2M 2þM 2M 1 2 1 2 1 2
Q1, Q2 Do1, Do2 C1 , C2 Co1, Co2 L1 Lo1, Lo2
-
Co1 ¼ Co2 ¼ Current
4. Simulation results M 3 2 1 2 M 3 2
3.1. Energy transfer capacitors design To ensure the input characteristics of the proposed converter near-perfect PFC, the capacitors C1 and C2 must be carefully selected. The selections of these capacitors depend on two constraints. First, the voltages across C1 and C2 must follow the input voltage profile within a line cycle [1]. Second, the resonant frequency (fr) of C1, C2, L1, Lo1 and Lo2 must be much greater than the line frequency. The C1 and C2 designed equation is given by:
1 ð2pfr Þ2 ðL1 þ Lo1 Þ
(23)
3.2. Output capacitors design Output capacitors Co1 and Co2 are utilized to filter the load voltage. Thus, the value of the output capacitors is inversely proportion to the output voltage ripple Dvo as shown in Eq. (24). The output capacitor Co1 and Co2 values which are required to maintain a peakepeak output voltage ripple Dvo is given by
Co1 ¼ Co2
1 ¼ Dvo
3T Z L =8
iLo1 Io dt
(24)
TL =8
where Io is the output load current. Substituting the values of Io and iLo1 and solving the integration yields,
Fig. 6. Semiconductor voltage stress.
(25)
M
L1 can be obtained considering the maximum current ripple. Evaluate Leq from Eq. (16). Evaluate the output inductor Lo1 and Lo2. The converter capacitors selection is discussed below.
C1 ¼ C2 ¼
TL Vo 1 1 1 1 þ RL 2Dvo Re M 2 p 2
5
The proposed rectifier is designed for the following power stage specifications: peak input voltage of 100 V at 50 Hz, output voltage of 250 V, switching frequency of 50 kHz, and output power of 125 W. In addition, actual semiconductor devices are used in the simulation; STTH1003SB (300 V) are used for the diodes and irfb4332pbf (250 V with RDS-ON ¼ 29 mU) for the active power switches. Moreover, taking also into account the conduction losses associated with the reactive components, an equivalent series resistor (ESR) of 50 mU is placed in series with all the inductors and capacitors in the circuit. The circuit components used in the simulation is chosen as follows: L1 ¼ 2 mH, Lo1 ¼ Lo2 ¼ 50 mH, C1 ¼ C2 ¼ 1 mF, Co1 ¼ Co2 ¼ 400 mF. The switches duty cycle d1 is set to 0.25 according to Eq. (15). Simulation studies were performed using ORCAD software package, to verify the analysis results. The input voltage and current are in-phase as shown in Fig. 7. The percent of the total harmonic distortion (%THD) in the line current is less the 1% and the simulated efficiency is about 95.7%. Fig. 7 also shows the output voltage with peakepeak voltage ripple equal to 8 V with an average dc value close to 250 V. It should be mentioned here that the output voltage ripple can be further reduced by connecting an additional small capacitor across the load terminals. Fig. 8a shows the switch Q1 as well as the output diode (Do1) currents over several switching periods. Fig. 8b shows the waveforms of the three inductors’ currents over several switching periods at peak input voltage which correctly demonstrates the DCM operating mode. Fig. 8b also shows that the three inductors’ currents have proportional slopes over the three different stages during a switching cycle. Thus, the three inductors can be coupled which lead to lower costs and smaller size. In addition, the three inductors are being charged by the input voltage when the Q1 is conducting, while they are discharging through the output capacitors during diode Do1 conduction. Fig. 8c and d shows the voltage waveforms across the energy transfer capacitors and the output filter capacitors, respectively. A very good agreement can be seen between simulation and the theoretical predictions. In order to demonstrate the effect of coupling the inductors on the input line current, the circuit of Fig. 2a has been simulated with coupled inductors. In this case, the output inductors Lo1 and Lo2 are both coupled to the input inductor L1, but that Lo1 and Lo2 are not directly coupled. Moreover, in the proposed topology, it is preferred that inductors Lo1 and Lo2 have equal values so that they carry the same ripple current. In this case, it can be shown that “near zero current ripples” in the input inductor L1 can be obtained if the following condition is met:
Fig. 7. Simulated waveforms for the proposed rectifier in DCM (input voltage vac, input current iac, and output voltage Vo).
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
6
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
Fig. 9. Simulated waveforms for the proposed rectifier in DCM: (a) uncoupled inductors, (b) coupled inductors.
the generated EMI noise level is greatly minimized as well as the requirement for the input filtering.
5. Experimental results
Fig. 8. Simulated waveforms for the proposed rectifier in DCM: (a) switch current iQ1 and diode current iDo1 , (b) inductors’ currents iL1 , iLo1 , and iLo2 , (c) energy transfer capacitors’ voltages vC1 and vC2 , and (d) output filter capacitors’ voltages vo1 and vo2.
k1o1 ¼ k1o2 ¼
1 2
sffiffiffiffiffiffiffi Lo1 L1
with Lo1 < L1
(26)
where k1o1 and k1o2 represent the coupling coefficient between L1eLo1 and L1eLo2, respectively. In order to verify the “near zero current ripples” in the input line current, the circuit of Fig. 2a has been simulated for the same power stage parameters and components values except for the values of the three inductors. The values of the coupled inductors used are L1 ¼ 500 mH, Lo1 ¼ Lo2 ¼ 50 mH. Thus, the values of both coupling coefficients k1o1 and k1o2 are set to 0.16. The simulated input voltage and input current waveforms for the uncoupled and coupled case are shown in Fig. 9a and b, respectively. It is evident from Fig. 9b that the high frequency switching ripples’ magnitude in the input current (iL1 ) is greatly reduced due to the coupling of the three inductors. Consequently,
The bridgeless DCM Cuk rectifier prototype test is validated at the same operating point as the simulation. The circuit components values are the same as those used in the simulation except for the active switches Q1 and Q2. Due to availability during prototype assembly, MOSFETs STY60NM50 from STMicroelectronics were used. A small high frequency input filter is used at the input port of the rectifier to bypass the high frequency current so that the input current consists of the low frequency part only. Fig. 10 shows the input current and line voltage. It can be seen that the line current and phase voltage are in phase. Fig. 11 depicts the waveforms of the three inductors currents (iL1 , iLo1 , and iLo2 ) during a few switching periods, which correctly demonstrates the DCM operating mode. The energy capacitor voltage waveforms (vC1 and vC2 ) are shown in Fig. 12a. It is evident that the capacitor voltages follow the input voltage and they are shifted up by half the output voltage as explained in Eqs. (1) and (2). Fig. 12b illustrates the output filter capacitor voltages (vo1 and vo2). It is clear from Fig. 12b that the voltages vo1 and vo2 are equal to half of the output load voltage. The experimental waveforms are obtained in the absence of any snubber circuits and without any special circuit layout. The efficiency at full load is close to 93.3%.
6. Conventional Cuk versus the proposed Cuk rectifier The circuit components in both the conventional PFC Cuk and the proposed bridgeless PFC Cuk have similar current stresses. However, the proposed Cuk subjects the reactive components and the semiconductor switches to a lower rms current stress compared to their counterparts in the conventional Cuk topology. On the other hand, the switching performance of the two converters remains mainly the same, which results in similar switching losses. In contrast, as shown in Table 2, the input current in the proposed Cuk flows through fewer power semiconductor devices compared to the conventional Cuk PFC. Thus, efficiency
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
7
Fig. 10. Experimental waveforms for the proposed rectifier of Fig. 2a (input voltage vac and input current iac).
improvement by using proposed Cuk mainly relies on the conduction loss difference between the two topologies. Regarding the voltage stress, as mentioned before, the voltage stresses on the switches (Q1 and Q2) and the diodes (Do1 and Do2) of the proposed converter is Vm þ Vo1 which is less than that for the conventional Cuk converter (Vm þ 2Vo1). Therefore, these reduced voltage stresses can make the proposed converter utilize a power MOSFET with low RDS-ON and Schottky diodes to minimize reverse recovery of diodes. As a result, the overall circuit efficiency can be further enhanced. It should be mentioned here that the proposed rectifier requires an additional floating switch which requires an additional gating circuitry. An efficiency comparison between the conventional and the proposed Cuk rectifiers is performed based on simulation results. In this comparison, both rectifiers are assumed to operate in DCM with the same operating conditions and parameters. The simulated efficiency includes conduction and switching losses of the semiconductor devices, inductors’ copper losses, as well as capacitors ESR losses. Furthermore, Pspice actual semiconductor models have been used to simulate the semiconductor devices: STTH5L06 (600 V) ultrafast fast high voltage rectifier for the diodes and STY60NM50 (500 V with RDSON ¼ 45 mU) for the power MOSFET(s). According to the simulation results, both rectifiers offer low input current THD which is 1.5% for the conventional Cuk and it is 0.7% for the proposed rectifier. However, the simulated efficiency for the conventional Cuk is about 92.5% while it is 94.7% for the proposed Cuk rectifier. Note that as mentioned in Section 4, the simulated efficiency for the proposed rectifier is higher than 94.7%. This is mainly due to the low ON resistance of the power MOSFETs (RDSON ¼ 29 mU).
Fig. 12. Experimental waveforms for the proposed rectifier of Fig. 2a. (a) Energy transfer capacitors’ voltages vC1 and vC2 , (b) output filter capacitors’ voltages vo1 and vo2. Table 2 Comparison between conventional and bridgeless Cuk rectifiers in DCM mode.
Diodes Switch Current conduction path in stage 1 Current conduction path in stage 2 Current conduction path in stage 3 Number of components Integrated magnetic Driver circuit complexity Ground
Conventional Cuk
Proposed Cuk rectifier
4 slow and 1 fast 1 2 slow diodes and 1 switch 3 diodes (2 slow and 1 fast) 2 slow diodes
2 fast 2 1 body diode and 1 switch 1 fast diode
10 One core for 2 inductors 1 non-floating
11 One core for 3 inductors 1 floating and 1 non-floating Floating
Non-floating
e
7. Conclusion
Fig. 11. Experimental inductors’ currents waveforms iL1 , iLo1 , and iLo2 for the proposed rectifier of Fig. 2a.
In this paper, a high step-up bridgeless Cuk acedc rectifier has been presented. The proposed high step-up bridgeless Cuk rectifier has been analyzed in DCM mode. The gain of the converter as a function of the control signal has been derived. The constraints for operation in DCM have been presented. The current and voltage stresses of the proposed topology are given. It was shown that the voltage stresses on the power switch and the output diode are lower than that of the conventional Cuk converter. The capability of the proposed topology has been built and tested at prototype level. The experimental results are in good agreement with the theoretical and simulation results. Efficiency improvement over the conventional Cuk PFC rectifier is demonstrated by simulation results. The improvement in the conversion efficiency is more than 3% at full load.
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050
8
A.K. AL-Kaabi et al. / Renewable Energy xxx (2012) 1e8
Acknowledgments This work was supported in part by the Emirates Foundation in the United Arab Emirate under contract # 2011/158.
References [1] Brkovic M, Cuk S. Input current shaper using Cuk converter. In: IEEE telecommunications energy conference, INTELEC 1992; 1992, p. 532e539. [2] Simonetti DSL, Sebastian J, Uceda J. The discontinuous conduction mode SEPIC and Cuk power factor preregulators: analysis and design. IEEE Trans Ind Electron 1997;44(5):630e7. [3] Jingquan C, Maksimovic D, Erickson RW. Analysis and design of a low-stress buck-boost converter in universal-input PFC applications. IEEE Trans Power Electron 2006;21(2):320e9. [4] Garinto D. A new zero-ripple boost converter with separate inductors for power factor correction. In: IEEE power electronics specialists conference, PESC 2007 record; 2007, p. 1309e1313. [5] Lázaro A, Barrado A, Sanz M, Salas V, Olías E. New power factor correction ACe DC converter with reduced storage capacitor voltage. IEEE Trans Ind Electron 2007;54(1):384e97. [6] Fardoun AA, Ismail EH. Non-isolated single stage PFC rectifier for wide-input large step-down. Int J Power Electron 2010;2(4):412e27. [7] Wu X, Yang J, Zhang J, Xu M. Design considerations of soft-switched buck PFC converter with constant on-time (COT) control. IEEE Trans Power Electron 2011;26(11):3144e52. [8] Oruganti R, Palaniapan M. Inductor voltage control of buck-type single-phase AC-DC converter. IEEE Trans Power Electron 2000;15(2):411e7. [9] Wei W, Hongpeng L, Shigong J, Dianguo X. A novel bridgeless buck-boost PFC converter. In: IEEE power electronics specialists conference, PESC 2008 record; 2008, p. 1304e08. [10] Mok K, Lai Y, Loo K. A single-stage bridgeless power-factor-correction rectifier based on flyback topology. In: IEEE international telecommunications energy conference, INTELEC 2011 record; 2011, p. 1e6. [11] Jang Y, Jovanovic MM. Bridgeless high-power-factor buck converter state-ofthe-art. IEEE Trans Ind Electron 2011;26(2):602e11.
[12] Jovanovic MM, Jang Y. State-of-the-art, single-phase, active power-factorcorrection techniques for high-power applications e an overview. IEEE Trans Ind Electron 2005;52(3):701e8. [13] Huber L, Jang Y, Jovanovic MM. Performance evaluation of bridgeless PFC boost rectifiers. IEEE Trans Power Electron 2008;23(3):1381e90. [14] Choi W-Y, Kwon J-M, Kim E-H, Lee J-J, Kwon BH. Bridgeless boost rectifier with low conduction losses and reduced diode reverse-recovery problems. IEEE Trans Ind Electron 2007;54(2):769e80. [15] Su B, Zhang J, Lu Z. Totem-pole boost bridgeless PFC rectifier with simple zero current detection and full range ZVS operating at the boundary of DCM/CCM. IEEE Trans Power Electron 2011;26(2):427e35. [16] Tsai H-Y, Hsia T-H, Chen D. A family of zero-voltage-transition bridgeless power-factor-correction circuits with a zero-current-switching auxiliary switch. IEEE Trans Ind Electron 2011;58(5):1848e55. [17] Su B, Lu Z. An interleaved totem-pole boost bridgeless rectifier with reduced reverse-recovery problems for power factor correction. IEEE Trans Power Electron 2010;25(6):1406e15. [18] Chen Z, Xu J, Zhou G, Zhang F. Analysis of bridgeless pseudo-boost PFC converter. In: IEEE international symposium on industrial electronics, ISIE 2012; 2012, p. 189e193. [19] Ismail EH. Bridgeless SEPIC rectifier with unity power factor and reduced conduction losses. IEEE Trans Ind Electron 2009;56(4):1147e57. [20] Sahid MR, Yatim AM. Modelling and simulation of a new bridgeless SEPIC power factor correction circuit. Simulat Model Pract Theory 2011;19(2):599e611. [21] De Melo PF, Gules R, Romaneli EFR, Annunziato RC. A modified SEPIC converter for high power factor rectifier and universal input voltage applications. IEEE Trans Power Electron 2010;25(5):310e21. [22] Sabzali AJ, Ismail EH, Al-Saffar MA, Fardoun AA. New bridgeless DCM SEPIC and Cuk PFC rectifiers with low conduction and switching losses. IEEE Trans Ind Appl 2011;47(2):873e81. [23] Mahdavi M, Farzanehfard H. Bridgeless SEPIC PFC rectifier with reduced components and conduction losses. IEEE Trans Ind Electron 2011;58(9): 4153e60. [24] Fardoun AA, Ismail EH, Sabzali AJ, Al-Saffar MA. New efficient bridgeless Cuk rectifiers for PFC applications. IEEE Trans Power Electron 2012;27(7):3292e 301. [25] Jayaram N, Maksimovic D. Power factor correctors based on coupled inductor SEPIC and Cuk converters with nonlinear-carrier control. In: IEEE applied power electronics conference and exposition, APEC 1998; 1998, p. 468e74.
Please cite this article in press as: AL-Kaabi AK, et al., Bridgeless high voltage battery charger PFC rectifier, Renewable Energy (2012), http:// dx.doi.org/10.1016/j.renene.2012.09.050