CAD tools for semicustom IC design

CAD tools for semicustom lC

design CAD tools are an integral part of semicustom design methodology. D Milford and N Kingswood assess the computer assistance that is available to the semicustom IC designer and show that no specific silicon-level design skills are needed

Recent papers in this journal 1"2 have provided an overview of semicustom design and descriptions of the most widely used semicustom technologies: gate arrays and cell-based ICs. This paper presents a survey of the various CAD tools which enable an electronic design engineer to use semicustom technology. It will be shown that the necessity for any specialized knowledge of silicon-level design is largely removed. semicustom ICs

CAD tools

simulation

Twenty years ago, when large-scale circuit integration was in its infancy, silicon design was an expert task performed to a great extent without computer assistance. The earliest CAD tools offered no more than limited assistance in draughting layout. Advances in fabrication techniques, providing smaller layout geometry and larger die size, have proceeded hand in hand with the development of sophisticated design tools which enable the technology to be fully exploited. Indeed, the computing power required for modern CAD relies extensively on the products generated by the previous generations of design tools: a classic example of bootstrapping. The use of CAD in semicustom design arises mainly out of the need to manage the enormous complexity of the design task within time spans dictated by the IC marketplace. Automation of the more routine tasks and computer assistance elsewhere offer considerable saving in time and labour. More importantly, a well designed CAD system can lend flexibility to the design process, help reduce design errors and provide documentation.

from the abstract (a circuit specification) to the concrete (an implementation). As VLSI circuit complexity grows there will be an increasing need for designers to work at the system level 3. The ultimate in design automation is the 'silicon compiler' which generates silicon layout from a formal input specification of the circuit behaviour. This has been realized to avery limited extent, but many of the silicon compilers which are presently available simply enable circuit design using a library of parametrized highlevel functional blocks 4. Thus, the construction of a circuit from a behavioural specification remains, to a large extent, a human activity. This dictates an iterative process (Figure I) in which circuit synthesis and analysis are repeated until all the design constraints have been satisfied. CAD tools can be divided into two classes: those that assist or automate synthesis and those which perform analysis. Synthesis tools

• design entry • layout • mask generation

Analysis tools • static analysis • dynamic analysis (simulation)

Design entry tools enable the user to input a specification of the circuit structure in a convenient form. Layout tools are used to determine the physical structure of the customized target device. Mask generation is a fully automated process which produces a specification of the fabrication geometry. In the case of a gate array this describes the final layer(s) of metal which form connections CLASSIFICATION OF CAD TOOLS between the prefabricated transistors. Static analysis examines the circuit structure for Circuit design can be regarded as a process which translates violations of design rules and reports errors. Dynamic analysis allows the circuit function and behaviour to be Department of Electricaland Electronic Engineering,University of Bristol, examined by simulating its response to a sequence of University Walk, Bristol BS8 1TR, UK input stimuli. Paper received: 23 May 1988 0141-9331/88/07363-10 $03.00 © 1988 Butterworth & Co. (Publishers) Ltd Vol 12 No 7 September 1988

363

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Layout A typical design route is illustrated in Figure 2. The tools are discussed below in further detail; they are presented according to their normal sequence in the design procedure.

364

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REQUIREMENTS FOR CAD

Modern CAD applications demand a platform with considerable computing power, good graphics facilities and large amounts of storage. The field is therefore dominated by workstations (e.g. Sun, Apollo) with a hardware and software base capable of supporting complex applications. However, improvements in software design have resulted in a limited area of semicustom CAD applications forwhich PC-based systems can be considered adequate, though add-ons such as hardware accelerators and memory extension may be required. An important feature which emerges from a consideration of the design route is the varying design perspective as operations proceed. At design entry a structural view predominates, whereas functional and spatial considerations are uppermost in the simulation and layout phases respectively. It is crucial that a correspondence between these views is maintained so that the designer develops a coherent conceptual model of the design process. In practice this is normally achieved by a suite of programs which operate upon a unified database containing all the design data. Different programs are invoked at different stages in the design, often under the control of a supervisory program which guides the user through the design environment. This supervisor may also check that operations are being performed in the corrent sequence, but data integrity is most effectively ensured by using a database management system (DBMS) which provides a common interface to all application programs facilitating the development and addition of new tools (Figure 3). One further vital consideration is the human interface

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to the CAD system. A substantial degree of user interaction is required throughout the design process so it is important that the interface encourages good design. A menu driven system employing intelligent use of graphics and pointing devices will generally satisfy this requirement. Online help and enforcement of design rules are also useful. COMPONENT LIBRARY

The key feature of semicustom technology is the delegation of responsibility for low-level silicon design from the designer to the vendor. An analogy can be drawn here with the use of high-level language by a software designer who does not wish to be concerned with computer architecture; he relies on the compiler writer for a correct implementation of the high-level code. In effect, the semicustom IC designer is provided wtth a library of famdiar components which serve as well characterized elements in the construction of a circuit. These range typically from simple gates through flipflops of various kinds to registers, encoders, decoders, adders

Microprocessors and Microsystems

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etc. Cell-based systems may also include analogue components. Each library element is supported at different stages of the design process by the relevant structural, behavioural or layout information. Further information on library implementation is given below.

Schematic of a simple decoder

The HDL provides a concise description of the circuit structure using a simple syntax. The DEF statement includes a list of inputs to and outputs from the circuit followed by a declaration of internal connection names. In the main block each component in the circuit requires a separate statement of the form component_instance := componenLtype(inputs,outputs); Note that unique names are assigned to each instance of a component type and to each 'net' (connection between components).

Hilo HDL

DESIGN ENTRY The design is captured by specifying the connections between components, either in the form of a textual description or by using a graphics interface.

Hardware description languages (HDLs) Although the scope of the hardware description language is wide, it can be used simply to define the topology of a circuit. Consider these descriptions of the circuit in Figure 4 which is constructed from library primitives. The first is used by Qudos in its Quickchip design system and the second is used to specify circuit structure to GenRad's Hilo simulator s. Qudos HDL DEF decoder(a,b:lN; w,x,y,z:lO);

CCT decoder (w,x,y,z,a,b) NOT invl(na, a) inv2(nb,b); AND andl(w, na,nb) and2(x,a,nb) and3(y,na, b) and4(z,a,b); INPUT a,b; WIRE na, nb; This text has a similar and slightly more economical syntax. These two examples illustrate basic HDL structure, there are many other features which allow, for example, parametrization of components and nets for simulation purposes. If a circuit description is entered using an HDI_ it will generally be checked and compiled into the database in a form suitable for access by subsequent programs. Of particular importance during simulation is the connectivity information, commonly referred to as the 'netlist'.

na,nb:lO; BEGIN invl inv2 and1 and2 and3 and4 END;

Schematic capture := := := := := :=

INV(a, na), INV(b,nb); AND(w,na, nb); AND(x,a, nb); AND(y,na, b); AND(z,a,b);

Vol 12 No 7 September 1988

Circuit structure is more commonly specified in diagrammatic form using an interactive high-resolution graphics editor. Making extensive use of menus and a pointing device (e.g. a mouse), symbols representing component types can be selected, positioned and connected together. The schematic editor will generally allow textual attributes to be attached to components (symbol instances) and

365

nets for use by subsequent processes. An attnbute may be used slmply to assign a name, to specify parameters such as propagation delay, or to specify critical nets, for example global clock signals which must have a low skew value. Dunng schematic capture the design is entered into the database as graphical data. On completlon the circult structure (netlist) is extracted m a form sultable for subsequent processing.

wdl be necessary to wnte behawoural ,nodel, :,~,~. below, sectlon on simulatlon) A change of vendor (new library of pnmitive~) wdl ledV~ most of the higher-level design unaffected Efficient functional partttiomng will generally re~ull m mmimlzation of intermodule commumcat~on. The~efore there ts hkely to be a good correspondence between functional and spatial partitiomng which ~an be exploited m the layout phase

Hierarchy Irrespective of the input mechanism it is important that a structured design methodology is supported by the CAD system. At the lowest level the circuit must be constructed using vendor-defined library components, but a singlelevel descnption becomes difficult to use in large circuits. The implementation of a hierarchical design regime encourages a modular approach in which the designer can mix top-down and bottom-up strategies. The design is partitioned into functional modules each with a well defined interface. Each module can be referenced from within other (higher-level) modules in the destgn hwerarchy forming a tree with the overall design as its root and library primitives as its leaves (Figure 5). In an HDL this is accomplished by making each orcurt defimtion a procedure which can be called from other circuit definitions. In fact, each circuit definition serves as a macro, each reference to it will substitute the structure defined within it. Thus, in the previous example, 'decoder' can be regarded as a user-defined component type and each reference to it will call up the specified collection of interconnected gates for inclusion in the final circuit. By analogy, when schematic capture is used for input the graphics editor will provide facilities to create a symbol as a representation of a schematic dtagram. The symbol can then be used in the schematics for higher levels ~n the hierarchy. H~erarchlcal design methods offer significant benefits. • Complexity is reduced, making the function of each circuit module readily comprehensible; individual HDL orcuit definitions are kept short and schemattcs rarely extend beyond a single screen. Seen in terms of the destgn tree, the branching factor is optimized for clarity of design. • Modularity allows partitioning of a large circuit among members of a design team. • Modules can be independently simulated pnor to simulation of the whole orcuit. At the higher levels it Intermediate nodes instances of user

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366

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STATIC ANALYSIS It must be assumed that for the majority of orcutts a complete analysis is impossible or impractlcal. There are two approaches to partial design venfication: static and dynamic analysis. Static analysis employs a rule base to uncover design errors in the circuit structure. These might include electrical checks such as • • • •

unconnected inputs undriven nets nets driven by more than one output (may be legal) excesslve fanout.

In a timing verifier 6 the circult performance ts examined by incorporating propagatlon delay data into the circuit model. Timing hazards can be identified and in synchronous orcuits the critical path between clocked elements can be found. Given the clock rate this enables flipflop set-upand-hold time violatlons to be reported. Unlike simulation, which is discussed below, static analysis does not require an exact specification of input stimuli. Some of these features may be incorporated into the design entry phase with checks running as a background process.

SIMULATION (DYNAMIC ANALYSIS) A complementary, and more empirical, approach to circuit analysis is to simulate the behaviour of the circuit in response to a particular sequence of input stimuli or 'test vectors'. The aim of simulation is to check the logical function of a design and to verify that the performance specification can be met when the circuit is fabricated. It =s also sometimes used to evaluate the operation of a circuit under conditions of faulty manufacture. There are several types of simulator but they all involve combining two types of information about the design, namely • circuit structure, which ~s contained in the netlist derived from the HDL or the schematics • models describing the behaviour/logic/timing of each of the components in the design. This information is bound together m a slmulation program which, by analogy with an actual circuit, can respond to stimuli in the form of input commands. At the most basic level these commands describe how the inputs to the circuit vary with time and the points in the circuit that are to be monitored. For small circuits it is usually only necessary to stRmulate the inputs and monitor the outputs. For larger circuits it may also be necessary to monitor internal points to check that the orcuit is behaving as expected. The commands can either be entered mteractively or, more usually, m the form of a command file. The latter approach is especially useful tn slmulattons that take some time. Depending on the

Microprocessors and Microsystems

simulator a number of other commands may also be permitted such as setting breakpoints when a connection takes a certain value, or at a certain time. Several simulation runs may be necessary to test all aspects of the design. The results generated by the simulation can usually be displayed in two ways. • Immediate results are displayed while the simulator is running. These are usually textual messages of the form 'Connection x changes to hi at time y' • Results can be output to a file. This file can subsequently be read by a postprocessor which will arrange the results in a clearer manner, either in tabular form or as graphical output. Unexpected behaviour is more easily recognized in a waveform representation.

Types of simulator A variety of simulator types have been developed to handle simulation at different levels in the design hierarchy. They range from behavioural simulators at the most abstract, through logic-level to circuit-level simulators which model according to physical principles. In semicustom applications the behaviour of each library component is well specified so simulation is normally performed at the behavioural or logic (gate or switch) level. Behavioural simulation

If a behavioural simulator is used to support semicustom design at the lowest level there should be a model for each of the library elements describing the characteristics which have been determined for it by the silicon vendor. There will also be provision for the designer to create models of the user-defined components which exist at higher levels in the design hierarchy7. This type of simulator allows the user to verify overall system behaviour before investigating implementation details at a lower level. The models that the user writes to describe these components are vendor independent and, unless they are very complex, will execute quickly and are useful in removing the more obvious errors from a design. The drawback is that they can only check the logical behaviour and approximate timings. Except for library models, accurate timing information is difficult to obtain since there is no direct correspondence to a physical component. An example of a typical model for a behavioural simulator is given in Figure 6. This shows the behavioural model for a decoder written in a hierarchical hardware description language (HHDL) used in the Helix simulator from Silvar-Liscos. It illustrates how a hardware description language can be extended to describe behaviour by adding the concept of time to the familiar features of a high-level language. The actual function of the model has been described in a 'subprocess' which is the construct used by HHDL to support the notion of concurrency. A model could contain several subprocesses each activated by different inputs and each effectively executing at the same 'time'. This enables the concurrent nature of hardware to be modelled. Another example of a behavioural simulator is Ella from Praxis8'9. Unlike Helix, which has many predefined functions, Ella requires the user to build behavioural

Vol 12 No 7 September 1988

use Iospack; comptype decoder (tphl, tplh :integer); default (* default valuesfor the delay *) tphl = 3; (* used if formal parametersare not set *) tplh = 4, reward a, b • ttlnet, outward w,x,y,z, ttlnet; var pos : integer; subprocess update"upontnJechecka,bdo (* executethMscodeif inputschange*) begin Iogpdsave(tplh,tphl,O,O,O,O);

pos .= Iogenc4(Io,lo,b,a); assignIogmpd(Iogfrombool(pos=O))to w delay Iogretdel; assignIogmpd(Iogfrombool(pos=l))to x delay Iogretdel; assignIogmpd(Iogfrombool(pos=2))to y delay Iogretdel, assignIogmpd(Iogfrombool(pos=3)) to z delay Iogretdel; end; begin (* dummy mare program*) end; Notes

The net type "ttlnet' has four possible logic values: HhLO,~Z 'logenc4' is a fibrary function which returns an integer derived from four logic values 'logfrombool" is a fibrary function which converts boolean TRUE/ FALSE to HI/LO "logmpd" returns a logic level and assigns the appropriate value to the global variable 'logretdel' Figure 6.

Typical m o d e l for a behavioural simulator

models using a small but powerful set of primitive constructs. Both languages offer considerable flexibility in the description of high-level circuit blocks and can therefore be used to specify circuit behaviour in an unambiguous way. In practice a behavioural simulator is built by compiling circuit structure and appropriate models into executable code. This customized simulator may take some time to compile but will generally execute efficiently. The speed of simulation will clearly depend upon the complexity of the circuit structure and its component models. When library models are used to obtain accurate timings it is useful to partition the design and simulate these parts individually to remove errors. Simulation of the full design can then be attempted with greater confidence. Gate-level s i m u l a t o r s

The type of simulator used at the lowest level of the hierarchy depends on the way the primitive components in the library are modelled. In the case of a functional/ behavioural simulator a single model is used to describe each library component. Alternatively, each library component may be specified to the simulator as a macro composed of more simple elements. In a gate-level logic simulator the design is expanded so that it is described totally in terms of gates. The increase in structural complexity which results from this decomposition is balanced by a simplification of the behavioural model for each element. This removes the need to build a customized simulator; gate behaviour can be built into a generalized 'simulation executive' which operates directly on structural data contained in the design database. A'table

367

dnven' simulator hke this may execute more slowly than a 'compiled code' stmulator but it offers many advantages, most importantly the facility to resimulate after alterations to the circuit structure without recompdation

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Switch-level simulators In some circumstances it is useful to simulate logic at lower than gate level. In a switch-level logic simulator the circuit structure is decomposed into transistors and wires with each transistor modelled as a simple sw~tch. This level of simulation tends to be useful for CMOS fabrication processes. The designer does not see this low-level modelling and is only able to access the library components. An example of this is the Exert simulator from European Silicon Structures (ES2) which is used in the Solo 1000/ 1200 design system. Circuit-level simulators, e.g. Spice, which model the individual transistors more accurately are not necessary since the library components are well characterized by the manufacturer.

Signal models The complexity of models is reflected in the detail in which the values of signals are described. In a simple digital simulation only the values (0, 1) would be used. This two-level simulation is only really useful for preliminary work. More usually a four-level system (0, 1, X, Z) is used where X is an unknown value and Z represents the high impedance state. Further values are used internally by many simulators to resolve conflicts caused by the use of wired logic and transmission gates. HILO, for example, uses the concept of 'weak' and 'strong' signals in this context.

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tplh(loaded) = tplh(unloaded) + load factor * Atplh The propagation of short pulses is particularly problematlc (Figure 8b). Warnings may be issued for short pulses which are liable to be simulated inaccurately. The effect of winng capacitance can only be evaluated after layout has been performed so initial simulation cannot take account of it. Postlayout simulation is therefore essential after backannotation (see 'Layout' section below) has added the appropriate contribution to the load factor on each net.

Timing models Fabrication variations All digital simulators measure the passage of time in quantized steps and most are 'event driven', based on some form of time queue. Each change in signal state is classed as an event which is placed on the time queue at the appropriate point. The simulator keeps a record of 'present time' and determines the consequences of every event scheduled for that time by exercising the appropriate component models. The models will determine whether and when future events are to be scheduled. When all 'current' events have been dealt with the simulator updates its record of the present time with the time of the next event(s) in the queue. The simulator can thus be viewed as a scheduler which uses the time queue to control the execution of component models. This is illustrated m Figure 7.

Whatever type of simulator is employed it is useful to have some check on how variations in the manufacturing process will affect the operation of the circuit. Some models allow this by permitting the designer to run the simulation using either nominal, minimum or maximum delays in the models. It is usually sufficient to verify the circuit runs correctly with the nominal delays and then rerun the simulation at maximum delay and then again at the minimum delay. In this respect, ICs have an advantage over discrete implementations because all the library components on a given chip will be subject to the same fabrication variations, so all the delays are likely to increase or decrease in proportion.

Analogue simulation Delay models The accuracy of a simulation depends ultimately on the complexity of the delay modelling. The simplest approach, which permits basic functional verification, assumes a unit delay through all components. For more realistic simulation the models must be considerably more elaborate. The effective propagation delay through a component is dependent on the rise and fall times of signals and these in turn depend upon loading (Figure 8a). In CMOS circuits the capacitive effect of fanout load and wiring can seriously degrade performance. A simple model of loaddependent delay will be included in most simulators by using incremental delay calculations, e.g.

368

Up to this point the discussion has focussed on the simulation of digital circuits. However, the inclusion of analogue components in semicustom architectures is becoming increasingly common, most often as peripheral units such as D/A and A/D converters. These components can be modelled by most behavioural simulators (see, for example, Reference 9) because they support operations on a range of data types. Some logic-level simulators (e.g. ES2's Exert) may be able to handle analogue signals by describing them as a quantized digital value. For instance, a signal which varies between 0 and 5 V may be represented as a number between 0 and 255. Thus a single wire carrying an analogue signal is represented to

Microprocessors and Microsystems

Ideal gate output

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the simulator as a bus comprising eight wires. In some applications a mixed-mode simulator is needed 1°. This allows some parts of a circuit to be modelled at circuit level (transistors, capacitors etc.) with analogue signals and other parts at logic level with digital signals. The simulator automatically handles the conversion of signals from analogue to digital and vice versa at the interfaces.

Test vector generation and fault simulation Simulation as a means of circuit analysis is deficient in a most important respect - - the use of a finite set of test vectors to simulate the circuit merely samples its behaviour. In all but trivial designs an exhaustive test is impossible so the composition of test vectors plays an important role in successful simulation. Most commonly the preparation of test vectors is done by a designer who knows what the circuit is expected to do and which parts of the design are liable to cause problems. This human

Vol 12 No 7 September 1988

effort can be assisted to a limited degree by computer analysis of the resultant activity on each net during simulation. The objective is to ensure that every part of the circuit has been exercised; a minimum requirement would be that each signal should toggle at least once during simulation. Having prepared a set of test vectors for simulation it is natural that they should be used as the basis for testing the fabricated device. The test vectors must therefore be assessed for their ability to detect faults introduced during manufacture. This can be automated in a process known as fault simulation. The circuit is first simulated as described earlier and the output response stored. This represents the 'good' response of the fault-free circuit. A fault is then introduced at an internal point of the circuit and the simulation is rerun. If the output response is different from that of the fault-free circuit then the fault is clearly detectable under test conditions. This process is repeated with a fault at different points in the circuit until all the internal points in the circuit have been tested, a

369

procedure which is obvtously computationally =ntensive If a particular fault does not alter the output response then It is possibly undetectable or it may be revealed by a modification to the test pattems. The fault most commonly injected into the circuit is that a connection has become stuck ~n a particular state: so-called 'stuck-at-0' or 'stuckat-l' faults. Despite this somewhat arbatrary approach the procedure is reported to give good fault coverage in practice ~. The overall aim of fault simulation is to produce a minimal set of input vectors which will dtscover the maximum number of possible faults In the circuit. As ICs grow in complexity testing becomes increastngly problematic. Desigmng for testabihty, automatic generation of test vectors and fault simulation are subject areas which are currently attracting considerable attention ~ -~8.

Hardware accelerators

Software simulation'of large circuits, especially at gate level, requires large amounts of memory and computing time. Hardware accelerators are sometimes used for simulations of such circuits 14' is. These devices have the s~mulation algorithm implemented in hardware and make use of concurrent operation to greatly speed up the execution time of the simulation. Execution speed can be increased by factors of 100. Although giving rapid simulations, particularly for fault simulation, these machines represent a considerable capital investment. LAYOUT

Once the circuit structure has been defined it must be translated into a physical design. The first step in this process is the expansion of the structural hierarchy into a single 'flattened' design composed only of library primttives. It is important, however, that each component retains traces of its hierarchical origin because this ~s likely to be significant in the physical layout. In a semicustom design the layout for each library element is defined by the vendor so the designer can visualize each component as a 'tile' which must be positioned on the chip surface with appropriate connections to other tiles. The layout task 19 ' 20 therefore decomposes naturally into two distinct operations: placement and routing. Placement

The objective of the placement task is much easter to descnbe than it is to achieve. What is required is a tiling of

the chip surface (wtthm certa,1 constraints) which optm~ic~the interconnection between components according t~ certain critena. A global mm~m~zatton of mterconne~ t~o~~ length is generally desirable though, in the case ot gate arrays, this must be qualified by considerations of ~Outlrlg density Leaving this astde for the moment, constder the issue of netlength mlmmlzatton alone 1-his problem, which belongs to a class known as NP-complete, requires an exhaustive search amongst all possible tihng patterns and takes an unreasonable length of time to compute. Automatic placement algonthms must therefore, ~n practEce, be based on heuristic principles w h c h cannot be guaranteed to produce optimal results. A small amount of help from the destgner can produce significant improvements ~n layout and the CAD system must be flexible enough to allow this. In preparation for placement the designer should sketch out a floorplan for the layout based on the circuit structure; in essence th~s consists of mapDng the structural hierarchy used during design entry into two dimensions (Figure 9). The floorplan division need not extend to the lowest level of the structural hierarchy and the area allocated to each division should be estimated from the contents of the corresponding structural subtree. The placement tool should provide a graphics Interface which allows the designer to implement the floorplan Components are selected group by group and placed within selected areas of the chip surface. A variety of imtial placement algonthms may be available and the placement can then be improved locally or globally by an =terative process using a combination of criteria such as netlength and congestion. It as important that the routing phase b not started prematurely; the overall layout is bound to be poor (or with some gate array designs, impossible) ff the placement is inefficient Routing

Automatic routing tools are generally effective but =t ts ~mportant that the chosen algorithm ts suited to the technology. Standard cells and gate arrays are often organized in rows of fixed-height cells with routing channels running between them. It is not surprisingto find that 'channel routing' algorithms are most efficient in this case. Where the physical layout is less well structured (e.g. in block cell-based systems and in 'sea of gates' arrays) a maze router is likely to be used. In either case, if the design is implemented with a cell-based technology the space reserved for routing can always be expanded. With some gate arrays, however, the routing resources are fixed and automatic routing may leave the design incompletely

A2

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370

Microprocessors and M~crosystems

connected. In this case the designer is obliged to use a larger array or, if there is only a small number of unrouted nets, to use a graphics editor with facilities for reorganizing the routing. Manual routing must, however, be regarded as a last resort; it is time consuming and error prone. Up to this point, efficient use of chip resources has been the major consideration guidingthe layout. In many designs routing may also play an important role in device performance. The capacitive load introduced by metal or polysilicon routing can make a significant contribution to propagation delays in the circuit. This is usually based on the size (length x width) of the connection and the properties of the material used to make the connection. Provision must be made in the CAD system for layout dependent delays to be taken into account during a final circuit analysis. Routing delays are generally added to the database after layout is complete in a process called backannotation.

M A S K GEN ERATION When the layout has been finalized the design is ready to be taken to the fabrication facility. A translation program must be run to produce a layout specification in one of a variety of standard formats. These include ClF (Caltech Intermediate Format), Gaelic and GDS II which was originated by Calma and is now a widely used standard. This data is used to prepare masks for each customization layer or to provide control for direct writing using electron beam machinery. The more comprehensive Electronic Design Interchange Format (EDIF), supported by a number of semiconductor and CAD vendors, is gaining popularity. This format is intended to embrace every aspect of VLSI design at a variety of levels from high-level behaviour down to cell layout.

PRACTICAL CONSIDERATIONS Designers who wish to venture into the world of semicustom design are now faced with a bewildering variety of operational modes. Selection of a CAD system will ultimately be based on considerations of cost, quality and flexibility. All the major semiconductor manufacturers are promoting ASIC design and have set up a network of design centres. These typically offer training and support for their design facilities which can generally be used at the centre or accessed remotely. For first-time users who do not wish to make a large commitment to the technology these centres provide a useful option 21. Alternatively, many vendors now offer CAD software to run on popular hardware platforms. Both these options commit the designer to the range of silicon products offered by a particular vendor. If vendor independence is considered important the designer may invest in a dedicated design workstation. The leaders in this field include Daisy, Valid and Mentor, each offering a variety of hardware and software packages. Use of these workstations is widespread so that, in collaboration with silicon vendors, they are able to offer comprehensive library support. The final option is provided by software companies

Vol 12 No 7 September 1988

supplying CAD systems to run on a variety of standard hardware platforms. This option might appear attractive since it requires no dedicated hardware and no commitment to a silicon vendor. However, prospective users are advised to make a thorough investigation, particularly with respect to library support. If the vendor coverage is inadequate then the user will need facilities to create libraries and should consider the investment of time and effort this entails.

REFERENCES 1 Hicks, P J, Cotterell, R A and York, T A 'Overview of semicustom IC design' Microprocessors Microsyst. Vol 12 No 5 (June 1988) pp 245-259 2 York, T A 'Gate array architectures' Microprocessors MicrosysL Vol 12 No 6 (July/August 1988) pp 323-330 3 Brumfitt, J 'Matching VLSI tools to system design needs' Electronic Prod. Des. Vol 8 No 7 (July 1987) pp 29-36 4 Trayner, P 'ASIC design with silicon compilers' Electronic Des. Auto. Vol 2 No 8 (October 1987) pp 4, 5, 12, 13 5 Blundell, B G, Daskalakis, C N, Heyes, N A E and Hopkins, T P An introductory guide to Silvar Lisco and HILO simulators MacMillan Education, Basingstoke, UK (1987) 6 Wildman, P and Millman, D 'Usingtiming analysis to ensure product manufacturability' Electronic Prod. Des. Vol 9 No 4 (April 1988) pp 33-35 7 Clark, D'Reducingthe risk of ASIC designs' Electronic Prod. Des. Vol 8 No 6 (June 1987) pp 29-31 8 Thorpe, T L and Peeling, N E 'The role of HDLs in the digital design process' in Sequin, C H (ed.) VLSI 87, Proc. IFIP TC IO/WG 10.5 InL ConL on VLSI NorthHolland, Amsterdam, The Netherlands (1988) pp 29-44 9 Barton, I 'Using HDL at the analogue level' Electronic Prod. Des. Vol 8 No 10 (October 1987) pp 53-59 10 Munns, D 'Mixed analogue-digital simulator for VLSI design' Electronic Prod. Des. Vol 8 No 10 (October 1987) pp 73-74 11 Wilkins, B R Testing digital circuits: an introduction Van Nostrand Reinhold, Wokingham, UK (1986) 12 Davison, C 'Software for physical fault injection' Electronic Des. Auto. Vol I No 3 (November 1986) pp 6, 7, 14 13 Son, K 'The parallel value list algorithm for fault simulation' Electronic Des. Auto. Vol 1 No 3 (November 1986) pp 8-10 14 Wilkins, G 'A dedicated fault simulation engine' Electronic Des. Auto. Vol I No 3 (November 1986) pp 12-13 15 Molt, G 'The role of acceleration in fault simulation' Electronic Des. Auto. Vol I No 3 (November 1986) pp 14-16 16 Ovington, P 'Self diagnosis of gate arrays' Electronic Des. Auto. Vol 2 No 2 (March 1987) pp 14-15 17 King, H 'Macro support for testable ASICs' Electronic Des. Auto. Vol 2 No 5 (June 1987) pp 8, 17 18 Graydon, J and Serbin, J 'ASIC verification for system engineers' Electronic Des. Auto. Vol 2 No 3 (April 1987) pp 6, 7, 11 19 Brown, A D 'Automated placement and routing' Computer-Aided Des. Vol 20 No 1 (January/February 1988) pp 39-44

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David Milford is a computer engineer at the University of Bristol. After graduating from Imperial College, London, UK, in 1968 with a degree in physics he taught for several years in further education. In 1984 he obtained a PhD at the University of Bath, UK, for work on special-purpose image generation hardware. Current research interests include image processing architectures and CAD support for programmable logic.

20 McDonald, S 'Gate array place and route in the logic design cycle' Electronic Prod. Des. Vol 8 No 10 (October 1987) pp 33-39 21 Kutzin, M 'Advantages of ASIC design centres' J. Semicustom ICs Vol 5 No I (September 1987) pp 12-15

Nigel Kingswood ~ a CAD officer at the Unwerslty o~ Bnstol, where he graduated in 1983 with a degree tn physics. He Js currently completing research for a PhD into parallel architectures for computed tomography

Hicks, P l (ed.) Semi-custom IC design and VLSI Peter Peregrinus, Stevenage, UK (1983) Russell, G (ed.) Computer aided tools for VLSI system design Peter Peregrinus, Stevenage, UK (1987) Russell, G, Kinniment, D I, Chester, E G and McLauchlan, M R CAD for VLSI Van Nostrancl Reinhold, Wokingham, U K (1985)

BIBLIOGRAPHY Rubin, S M Computer aids for VLSl design Addison-Wesley, Reading, MA, USA (1987)

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'I 988 survey of logic simulators' VLSI Syst. Des. Vol 9 No 2 (February 1988) pp 50-61 'Survey of gate arrays and cell libraries' VLSI SysL Des. Vol 8 No 12 (November 1987) pp 76-101

Microprocessors and Microsystems