Overview of semicustom IC design

Overview of semicustom IC design Reduced system cost and increased petformance are among the advantages to be gained by using ASK devices. Introducing a series of papers on chip architectures and their integration into systems, P J Hicks, R A Cottrell and T A York review the field of semicustom design using gate arrays, cell-based devices and PLDs

The paper provides a broad introduction to semicustom integrated circuit (IC) design. Brief descriptions are given of gate arrays, cell-based systems and programmable logic devices, particularly concerning traditional manifestations but a/so including recently introduced variations. The range of computer-aided design (CAD) too/s that are necessary to assist the design process are discussed. Typical routes to fabrication are described and costs are compared for each approach. semicustom ASlCs CAD tools

ICs

gate arrays

standard

cells

PLDs

and/or MSI standard parts and software programmable components such as microprocessors and single-chip microcontrollers. In the papers that are to follow this introductory overview the emphasis will be on semicustom ratherthan full custom techniques. However, some knowledge of the procedures and tradeoffs associated with full custom design is important if the advantages and disadvantages offered by semicustom design are to be fully appreciated. For this reason a short section is included here giving a brief summary of the full custom design route.

FULL All manufacturers of modern electronic equipment should be considering whether some, or possi bly all, of an electronic system can be integrated onto one or more integrated circuits (ICs). Increased integration can offer reduced manufacturing costs as a result of high packing density, low system component cost and simplified assembly. This advantage is accomplished by lower power dissipation per gate and higher switching speeds. In addition, system reliability is improved because fewer connectors and solder joints are necessary and the possibility of design security is increased. The manufacturer must choose a full custom or semicustom design technique appropriate to his/her particular requirements. It will be assumed that, as far as customized silicon ICs are concerned, the main choices are between full custom systems, cell-based systems, gate arrays and field programmable logic devices. The last three options are often collectively referred to as semicustom techniques. The other design options available, which will not be considered here, include the use of SSI Department of Electrical Engineering and Electronics, University of Manchester Institute of Science and Technology, PO Box 88, Manchester M60 lQD, UK Paper received: 5 January 1988. Revised: 7 March 1988 0141-9331/88/05245-15

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CUSTOM

DESIGN

Traditionally, full custom design has involved ‘hand crafting’ chips at the silicon level and has demanded a considerable amount of skill and experience on the part of the designer. Every individual transistor and connecting track has to be drawn in terms of basic geometric shapes (polygons) corresponding to features that will eventually be reproduced on the various mask levels for the silicon fabrication process. A typical process may require ten or more such masks to be produced. Drawing of the polygons is usually achieved using a graphics editor on a computer-aided engineering (CAE) workstation and is inevitably time consuming and error prone. The designer must observe a set of geometric design rules for the particular process that he/she is planning to use, and at some stage it is necessary to verify that the layout that has been drawn conforms to these rules. Cells containing anything from one to several tens of transistors represent the basic building blocks from which the final chip will be assembled. When the layout of a cell is complete it is simulated at the transistor level; this process will include track capacitances that have been extracted from the physical description to yield accurate performance estimations. These steps are then iterated until satisfactory performance is achieved. A number of cells can then be Butterworth

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combined into larger elements and simulated similarly, gradually ascending the hierarchy until the system is complete. For larger elements it becomes impractical to simulate at the transistor level, and typical switching delays that are obtained from circuit simulation of individual cells are used in a logic simulator to provide an indication of performance. Full custom design offers by far the greatest degree of flexibility of any of the techniques available in that it allows the designer total freedom to decide what to integrate onto the chip (e.g. mixed digital and analogue, power devices, special-purpose devices with integrated sensors). However, the time and effort involved can amount to many man years and for this reason it is only justifiable if production volumes exceeding about 100 000 units are anticipated. At this level design costs can be readily absorbed in sales, as will be demonstrated below. Because it is such a highly skilled and specialized activity, establishing an inhouse full custom design capability is usually beyond the reach of all but the largest manufacturers. To be effective it requires considerable investment in specially trained manpower, extensive computing resources and complex and costly CAD tools. All chips have some origin in full custom design and it is therefore an indispensible activity, but for the present purpose of discussing IC design for widespread application it will not be appropriate to consider it further. The sections that follow deal in more detail with the various semicustom design styles that currently exist, the computer-aided design (CAD) tools required to design them and the routes available for fabricating the devices.

GATE

ARRAY

n

n

n

a Routing channels

Logic

cells

b \

PeriDheral

cells

Contact

DESIGN

pads

I

C The gate array, also referred to as the masterslice or uncommitted logic array (ULA), is possibly the most popular approach to custom IC design’. In this paper the subject, despite its importance, is described only briefly, in preparation for a more comprehensive treatment to be presented in a subsequent paper2. The primary aim of gate array design is to offer the advantages of a custom approach yet remove responsibility for the labour-intensive transistor-level considerations, principally performance verification and physical layout, from the customer. To achieve this the silicon vendor carefully predetermines and characterizes a simple logic cell, typically having the potential to realize a few basic gates, and then repeatedly locates instances in a regular matrix covering most of the chip area. The gate array wafers are then fabricated as far as the interconnecting layer, typically representing 90% of the processing; it is then left to the discretion of the user to determine a suitable pattern for a specific application. The vendor can afford to commit significant resources to the intensive task of ‘hand crafting’ the uncommitted matrix, as it ultimately has the potential to realize an almost infinite variety of circuits and therefore possesses the essential commercial quality of widespread market appeal. To the customer, the design environment is akin to that usingSSI orMSl components,involvingthe’wiringup’of a variety of predetermined gates, the difference being that silicon, rather than the printed circuit board, forms the substrate. The success of the technique is largely due to the recent widespread availability of sophisticated and reasonably inexpensive CAD tools, enabling a large

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n

n

n

n

n

Figure 7. Conventional gate array architectures: cells; b, row cells; c, butting cells

a, block

proportion of the systems design community to become involved in the activity. A number of architectural forms are available, being characterized bythe pattern of cell layout and the amount of silicon explicitly devoted to interconnection paths. Classically, three common variants are found, as depicted in Figure 1. Those that are most generous in their provision for interconnections enable highly automated and therefore rapid layout. Those with a denser matrix of logic cells offer more efficient utilization of silicon. The compromise, the row cell architecture, has established itself as the favoured solution. Each of the alternatives includes a surrounding ring of peripheral cells which can, usually automatically, be configured to realize a number of desirable interfacing functions. Internal geometries of cells vary substantially between technologies but are fairly standard within each. Much, if not all, of the concern with intracell connections to form particular gate configurations is transparent to the designer; predetermined macros, supplied by the vendor and residing within the CAD environment, can automatically realize such structures. In analogy with TTL, a component such as a latch can be used with little or no concern for its construction, simply requiring placement and appropriate interconnection. As concern with cell details is often unnecessary the matter will not be discussed further here.

Microprocessors

and Microsystems

The gate array market is dominated by CMOS devices, which typically offer a few thousand gates with toggle rates up to about 50 MHz. Recent innovative families offer as many as 100 000 equivalent gates together with approximately 0.5 ns delays, and consequently the gate array technique now offers a high degree of versatility. Whereas traditionally gate arrays have been attractive only for implementing random logic, the latest arrays introduce the possibility of efficiently realizing regular structures, notably memory. In particular the compacted array and the structured array3 from LSI Logic offer interesting possibilities. Details are readily available from the manufacturer. Recent reviews of the spectrum of commercially available gate arrays can be found in the literature4t 5. To summarize, gate arrays achieve the objective of reducing design time relative to full custom devices, and require only a reduced customized mask set. Consequently they are appropriate for relatively small production volumes, typically a few thousand; in particular, prototyping using this medium is often attractive. Gate arrays incur the penalty of offering only a compromise solution in terms of silicon usage and performance, due to the uniformity of the matrix, but a suitable array can usually be identified for a particular requirement. Turnaround time for designs is typically a few months and a similar period is required if corrections are necessary. Consequently the importance of ‘first-time correct’ design is paramount. If sufficient turnover is anticipated, then time delays from completing a design to receiving a chip are possibly the major drawback associated with gate array design.

CELL-BASED

DESIGN

It has been observed that full custom IC design offers the best solution in terms of packing density and performance but demands a massive investment in terms of human effort and therefore money. Contrast this with gate arrays, which provide a much quicker and cheaper route to integrating circuits onto silicon albeit at the expense of compromises in terms of silicon efficiency and performance. Cell-based IC design can be viewed as an attempt to obtain the best of both worlds in that it offers the ease of design of gate arrays while retaining some of the density and performance advantages of full custom. As with the gate array, the primary objective is to eliminate the need for the engineer to hand craft circuitry into silicon at the individual component or transistor level. This is achieved by making available to the chip designer a range of predefined and precharacterized functional cells (collectively referred to as a cell library) which can be used as building blocks to construct any desired circuit. Cells can be drawn from the library as required and placed virtually anywhere on the silicon, although in practice they are normally constrained to lie in horizontal rows in a manner similar to that for the row cell gate array style shown in Figure 1. The areas of blank silicon between the rows are used to accommodate the metal tracks which connect the cells together in a unique fashion and so generate the required circuit function. Each cell has been skillfully hand crafted by whoever is responsible for supplying and maintaining the cell library, and therefore comes close to achieving optimum efficiency in terms of use of silicon area and performance.

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This ability to optimize the cells represents one of the major advantages that cell-based systems have over gate arrays. It will be recalled that the components in gate array cells are fixed in size and position by the manufacturer and there is consequently little or no scope for optimizing the way in which these components can be connected together to realize a particular function. It is invariably the case that a given function implemented as a gate array cell will occupy a larger silicon area and have inferior performance compared with a hand crafted cell in a cell library. It should be expected that the advantages that cellbased systems have over gate arrays have to be paid for in terms of drawbacks in other areas. Because the cells are hand crafted on all the mask levels that are used in the chip fabrication process, it inevitably follows that a full set of customized masks must be generated to manufacture a cell-based IC. In terms of manufacturing cost and time a cell-based chip will demand equivalent effort to that required to fabricate a full custom chip. Compare this with the situation for gate arrays where only one, or at most three orfour, customized masks will normally be required to commit the array to a specific task. However, the necessity of using a full set of masks brings further benefits. Since the starting point for a cell-based chip design is essentially a blank piece of silicon (just as it is for a full custom design) the final dimensions of the chip need only be large enough to ensure that all the cells and the tracks used to interconnect them can be accommodated on the silicon. As it is virtually impossible to fully use all the components on a gate array, the size of chip that would be required to integrate a given circuit will always be larger than the corresponding cell-based solution. Having established the fundamental principles on which cell-based design is based it is necessary at this point to distinguish between two major design styles that have emerged. Chronologically the first to appear was the one that is now most commonly referred to as standard cells. A later development that attempts to overcome some of the limitations of standard cells is an approach that we will refer to as ‘general cells’, but which may also be encountered under the more ambiguous terms ‘compiled cell’ or ‘optimized cell’.

Standard

cells

This approach may also be encountered under the names ‘polycell’ or ‘library custom’, and the basic philosophy extends the use of families that are encountered at board level, for instance TTLand 4000 series CMOS, onto silicon. Ratherthen selecting suitable devices from a catalogue, as is common practice for design using standard SSI or MSI parts at the board level, they are chosen from a library contained in a CAD system and placed on a silicon slice rather than a PCB. A typical library may provide about 100 simple logic functions such as gates, flipflops, latches, I/O pads and possibly also analogue parts (e.g. operational amplifiers, comparators, voltage references, A/D and D/A converters). There is good reason to support the argument that such a design style is to be encouraged, as it is similar to that in which many engineers are already experienced and therefore requires relatively little retraining. Cells can be represented at a variety of levels, two of which, logical and physical, are depicted in Figure 2. The cell-based designer is concerned with the logical level for

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General

NAND

3

Figure 2. Two levels of representation for cell-based design: a, logical representation; b, physical representation

schematic capture and simulation and the physical level for layout. The logic level is represented by conventional symbols together with a name and labelled input and output pins as shown in Figure 2a. The physical level is simply treated as a black box of height h and width w, with l/O ports available at ‘hit points’ situated on the interconnection grid as shown in Figure 2b. In common with the gate array style, mask-level features, depicted as overlapping polygons in the full custom approach, are transparent to the cell-based designer. Typically a hit point is provided for each I/O connection along both the top and bottom edges of the cell, simplifying layout but compromising area. Power and ground rails, routed through the cell, are implicitly included and designed so as to abut with those in adjacent cells. For a given library, h is usually constant such that uniform rows of cells having a standard height represent the normal manifestation of this type of chip. The width w varies depending on the function of the cell. In analogy with the TTL data book, each cell has an associated data sheet providing relevant details such as timing characteristics, input capacitances and drive capabilities. Essential data for such documentation is provided by the supplier following a nontrivial full custom design characterization sequence. This includes hand crafted layout and transistor-level simulation using a tool such as Spice, and culminates some weeks later in the verification of the performance of test cells under avariety of operating conditions. Fox6, in a discussion of the approach, suggests that from six to eight man weeks are required to fully implement a new cell. Consequently, for a moderate library containing, say, 50 cells, eight man years are required; this may in fact be doubled following allowance for production and verification of test chips, leadingto development costs of several million pounds.

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cells

Standard cells are an acceptable design methodology for circuits that are composed mostly of ‘random’ logic; however, they do not lend themselves readily to the incorporation of regular logic structures such as RAM and ROM. There is no reason in principle why such structures cannot be integrated onto achip alongwith standard-celltype layout. The memory block could either be custom designed specifically to suit the desired application, orthe silicon vendor might be able to offer a library of structures of differing sizes and organization. The disadvantages with the first alternative are the time and effort that would have to be expended in designing the memory essentially at the silicon level, and the high probability of design errors occurring. The second option overcomes the problems of the first but severely restricts the freedom of the designer to specify a memory that is tailored to personal requirements. The considerable investment required to build and maintain such a library precludes its existence. An alternative approach to realizing structures such as RAM or ROM in a cell-based design exploits their inherent regularity and repetition of elements. For instance, a ROM could be considered as an assembly of six such elements: two types of internal cell, decoder, word-line buffer, bit-line precharge transistor and multiplexer. It is possible to design a set of primitive subcells which represent the basic constituents of the ROM at the physical layout or mask level. By calling up these subcells from a library and assembling them in the appropriate manner it should be possible to create the physical layout of a ROM of any required size to suit any desired application. Since the composition rules for regular logic structures are fairly straightforward, there is no reason why the entire process of assembling the layout from the primitive subcell library should not be carried out automatically by a specifically designed software tool. The input to such atool would be a specification by the designer giving the dimensions of the required function and any necessary programming information. It should now be evident that the system as described above would have the power of generating complex cells of predetermined function but variable or ‘parameterized’ size. Such a facility would clearly overcome the most serious disadvantage associated with fixed-size complex cells and therefore represents a major step forward in terms of achieving optimum packing density without the need for hand crafting at the silicon level. It is claimed that the chip areas obtained for parameterized regular structures are seldom inefficient by a margin of more than 10% compared to the hand crafted equivalents’. The parameterized cells are characterized over a range of sizes to enable simple performance models to be constructed which the designer can use to predict the performance of whatever configuration will be required to suit a given application. It should be noted here that the performance of the parameterized cells varies as a function of their size or complexity and that the designer has no control over this in the system as it has been described so far. Developments of the parameterized cell concept will almost certainly lead to systems in which performance and possibly other features can be parameterized. A number of vendors are now able to supply parameterized cells to their customers, one example being the

Microprocessors

and Microsystems

Megacell system developed by Plessey7,8. This uses a 2 pm CMOS process, supports designs up to 20 000 gates and is structured on four levels. Microcells correspond to standard cells in a 50-element library, as described above, and are used for random logic. Paracells are equivalent to the parameterized cell with both memory and data path logic functions available. Supracells are large cells of fixed function which are not parameterized. They are effectively hand crafted standard parts and might include, for example, microprocessors or D/A and A/D converters. Finally, layout cells are simply combinations of any of the other three types to form a higher-level structure which may be stored for future use. It is instructive to examine the type of floor plan arrangements that result from incorporating blocks of LSI or VLSI complexity into a custom chip design. The cells may now have arbitrary dimensions and occupy a significant proportion of the total chip area. Several of these complex cells might be arranged in an appropriate manner on a single chip. Random or ‘glue’ logic could then be implemented in the form of a standard cell layout on some remaining part of the chip surface. This arrangement compares with that of the structured gate array3. Note that the concept of cell-based design has been generalized away from the restricted-layout organization of standard cells to produce a methodology in which cells can be of any shape or size and placed virtually anywhere on the surface of the chip. These additional degrees of freedom introduce new problems when it comes to the layout or placement of the cells and the routing of interconnection tracks between them. Whereas placement and routing algorithms for standard cell systems have been developed to the point where the whole process is fairly highly automated, a far greater level of manual assistance or intervention is normally called for in the case of general cells. Of the two tasks, cell placement is the most difficult and is invariably carried out by the chip designer working interactively at a graphics workstation. Such automatic placement algorithms for general cells that do exist tend to produce results that are far less efficient in terms of packing density than can be achieved with manual intervention. Automatic routing of the interconnections between general cells can be accomplished, although the task is complicated by the need to take account of power supply distribution. For instance, tracks must be designed which allow for the differing demands from various parts of the circuit. In some cases 100% successful automatic routing can be difficult to achieve and some level of manual intervention may be necessary to complete the job, in which case it is essential that checks are made automatically to prevent the insertion of incorrect connections. To successfully manage the complexity of VLSI it is beneficial to adopt a hierarchical design approach, in an analogous manner to that described for full custom design. On surveying the sales literature it is apparent that the functionality of cell library components is steadily increasing, and some vendors are now including microprocessor ‘cores’ which can be integrated alongside more modest cells. Typically these are replicas of standard microprocessor products, the descriptions for which are extracted directly from an existing database thus implying little extra effort by the vendor. Intel, for example, offers complex ‘VLSiCELs’ containing descriptions of some of its

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products; these are well characterized, relatively simple to employ and offer superior performance due to reduced interfacing overheads. The consequences to cell-based design should be apparent and this approach is worthy of further consideration. Further details can be found in, for example, Williams et a/.’ and Hall and Trickeyg.

Technology A survey of cell libraries4 lists 74 different companies offering cell library products. Of these libraries about 90% are based on CMOS, the remainder using bipolar and in a few cases gallium arsenide MESFET technologies. The preference for CMOS is due primarily to the relatively high complexities that can be achieved - currently about 20 000-30 000 gates. A modern 2 pm silicon-gate CMOS process can provide typical gate delays of 4 ns with system clock rates of up to 20 MHz. At a higher clock rate than this a complex chip may become power limited, i.e. the total power dissipation of the chip will exceed the capabilities of a low-cost package. In the case of bipolar technologies, current-mode logic (CML) and emittercoupled logic (ECL) cell chips are capable of system clock rates up to 100 MHz. The power dissipation per gate of these circuits is much greater than for CMOS with the result that complexities are limited to around a few thousand gates maximum. It should be noted that continuing advances in IC technology result in permanent demands for libraries to cater for reduced feature sizes. Unfortunately designs cannot be simply scaled in proportion and therefore new cells must be completely designed. There are some moves in the industry to provide technology independent cell-based design systems.

FIELD PROGRAMMABLE

SEMICUSTOM

DEVICES

It has been described above how ICs can be customized via user specification of mask details. Perhaps the major disadvantage of this approach is the time taken to design and fabricate such chips and the necessity for first-time correct solutions if additional delays and costs are to be avoided. An attractive alternative allows for customization to occur in the field when all masking stages are complete. Programmable logic devices (PLDs) offer such a facility and belong to the family known as ‘field programmable semicustom’.

Programmable

logic devices

Conventional PLDs exploit the regularity that is inherent in the sum-of-products expressions that are produced in a typical combinational logic design. The following represents a brief simplified description of the approach and the reader is referred to Green” for further details. Basically, PLDs are organized into two distinct areas called the AND plane and the OR plane. The AND plane accepts all inputs to the chip and produces the desired product terms. These are received by the OR plane which combines appropriate terms to produce the required sum-of-products expression. A PLD contains many switches that can be configured, by the user, to realize the required expression. It should be noted that the

249

AND-OR plane terminology is arbitrary and implementations can be realized in an alternative manner; for instance, a NOR-NOR of complemented inputs produces the equivalent result as confirmed by appropriate manipulation of Boolean expressions. Activation of the intersections can be achieved by a number of methods, including selectively blowing fuses using a high current or turning transistor switches on with large voltages, both of which methods are nonvolatile. The first method is, understandably, irreversible and is common in bipolar devices. The latter is found in MOS devices which have been fabricated using a special floating gate process. Such transistors have an extra, isolated gate which accumulates and stores charge for an extended period following application of an elevated voltage. This charge is sufficient to maintain the transistor in a turned-on mode, and in this manner selected switches can be activated. This latter method has the added advantage that the stored charge can be removed, usually by the application of ultraviolet light but in some instances following application of a large negative voltage, and therefore the device can be reprogrammed. Programming is best accomplished using dedicated tools that are readily available and appropriate for a wide range of products. Such tools typically cost from a few hundred to a thousand pounds depending on the degree of sophistication required. PLDs are ideal for realizing combinational logic and, by including registers on the outputs which can be synchronously fed back to selected inputs, it is simple to produce state machines. This latter facility is specifically included in a number of commercial devices. Modern CAD tools are available to assist in the design process, especially for determining the patterns that are required for activating intersections. A common starting point would be the specification of appropriate Boolean expressions which may then be minimized and manipulated into tabular form in preparation for fuse selection. Such tools typically run on small personal computers, rendering the approach relatively inexpensive, and designs can be realized in only a few hours. If a correction is required it is possible to implement this in a short time, often using the same chip. The above considerations form the basis of PLD design which traditionally manifests itself in three forms: programmable read-only memory (PROM), programmable array logic (PAL) and programmable logic array (PLA). Recently a new family, the logic cell array (LCA), has been developed. The varieties are described below.

Product terms Inputs

I

Fixed

read-only

OR

f

1021 1022 1023

/ Programmable

interconnections outputs

Figure 3.

-

0

,

2

3

ROM architecture

excess of 200 ns whilst those of bipolar devices are below 100 ns. It is possible to use PROMS to implement random logic - indeed this has often been done - but because all possible input combinations are included as product terms it is usually extremely wasteful. The number of fusible links that are required rises exponentially with the number of inputs, doubling for each extra input; alternative methods are therefore sought.

Programmable

array logic

In the mid 1970s Monolithic Memories (MMI) recognized the above limitation and developed the PAL family”. In contrast to the PROM, these devices use a programmable Programmable AND

Fixed OR

A

memory

These devices are widely used as nonvolatile computer control stores and data storage tables. A PROM has a fixed AND array which realizes all possible product terms from the inputs, and is usually in the form of a decoder. This feeds a programmable OR array as shown in Figure 3. A variety of manufacturers offer devices in NMOS, CMOS and bipolar technologies in a number of configurations. For example, an EPROM from Mitsubishi having 16 inputs and eight outputs (64k X 8 bit) represents about the limit of present functionality, offers 200 ns access time and costs about f15. Alternatively, a bipolar device from Fairchild in an 8k X 8 bit configuration has an access time of only 55 ns and costs about f90. As a rough guide, present CMOS devices operate with access times in

250

Programmable

I

r

Programmable

AND

Programmable connections

Figure 4.

Basic PAL architecture

Microprocessors

and Microsystems

Programmable A

f

1

0

34

7

8

11 12

15 16

AND

Fixed \

19 20

23 24

27 28

OR

t

31

23

24

b-

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12 L

9 0

rre 5.

Monolithic

3

4

Memories

7

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11 12

15 16

19 20

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AND with fixed OR array as shown in Figure 4. The advantage of the PAL is that the number of fusible links required is linearly dependent only on the number of inputs, and therefore logic implementations are more efficient than when PROMS are used. Product terms feed specific OR gates, of which there may be several on one chip, and these are frequently fed to registered outputs. The circuit layout for a typical PAL is shown in Figure 5. One disadvantage is that if identical product terms are required for separate OR gates then they must be

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independently realized in the AND array; this leads to inefficient utilization of silicon. PALS represent the most popular form of PLD and are available in avariety of forms, up to a complexity of about 64 inputs with 32 outputs each having 16 product terms, as represented by MegaPAL The market is dominated by MMI. Prices for a nonerasable version are typically less than f5, rising to about f20 for the electrically erasable variety. PALSare usually employed as a replacement for TTL designs in order to decrease package count.

251

Programmable

AND-OR planes plus control plane to enable selective inversion of inputs, as shown in Figure 6. A variation described as afield programmable logic sequencer (FPLS), which employs feedback registers to realize state machines, was introduced in 1979. Signetics now produce three families (Series 28, 24 and 20) of devices having up

logic arrays

In 1975, Signetics introduced a new product family called the field programmable logic array (FPL4) in which all logic connections, in both the AND and OR planes, are programmable. The devices have the usual form of

Programmable

AND

A /

Proorammable

OR

1 L

-

1 -

z? m- z z Figure 6.

252

Signetics PLSl53

m *z

,m PL4

Microprocessors

and Microsystems

to 22 inputs, 42 product terms and ten outputs, each of which can represent a articular sum-of-products expression P required by the user’ . Typically a PlA costs less than f 10, and the manufacturers claim that devices will usually replace about 15-20 dual inline packages. Allowing for costs of KS, PCBs, assembly and testing, the manufacturers deduce that the PLA approach typically offers about 37% savings over SWMSI solutions’2. A comparison has also been made with PALs, concluding that PL4s incur less redundancy of logic and require no external inverters to change the active output levels. Both bipolar and erasable CMOS versions are available. As with PALS, the efficiency of logic usage tends to fall off when more than a few hundred gates are involved; therefore it is not attractive to use these devices for large designs. The reader should be aware that some vendors refer to the PIA type of array as a ‘programmable gate array’ or even a ‘gate array’. Furthermore, one major vendor refers to PLAs when PALS are the devices actually on offer.

Logic

Cl0

a Steering

cell arrays

This category of array was introduced in 1986 by Xilinx, which has since collaborated with MMI in developing a family which now offers two arrays, the 2064 and 2018, with 1200 and 1800 usable gates respectively’3. Fabrication is via a 1.6 f_rrndouble-layer metal CMOS process. The term ‘programmable gate array’ (PCA) has also, with some justification, been applied to this chip. Logic cell arrays (LCAs) allow the user the benefits of electrically erasable programmability together with high gate utilization, and were developed in an effort to offerthe attractive features of both gate arrays and FPLDs whilst eliminating some of their respective limitations. The devices have a gate array block architecture with an interior matrix of logic cells embedded in a mesh of interconnect, all of which is surrounded by l/O cells. Unlike traditional gate arrays, customization is achieved by writing configuration data to internal storage cells which together form a RAM. This is readily achieved by the customer in the field using personal-computer-based tools, and the devices can easily be altered to realize a new hardware solution on the same chip. The first chip, LCA 2064, comprises a square matrix of 64 logic cells called configurable logic blocks (CLBs), whilst the more recent LCA 2018 has 100 such cells. A schematic representation of a CLB is shown in Figure 7a and comprises a four-input combinational logic element, a register fed by a common clock line, a series of configuration switches and two outputs. The combinatorial element can be programmed, via the storage cells, to realize any function of four inputs or any two functions of three inputs. The actual function realized by a CLB depends on the state of the routing switches which are in turn controlled by the storage elements. The I/O blocks are also programmable to enable a variety of roles to be fulfilled. Each block has an input, output or bidirectional capability with a tristate option, as represented schematically in Figure 7b. Inputs can be configured for TTL and CMOS thresholds and the blocks have an input registerwith a common clock. The 2064 has 58 I/O blocks while the 2018 has 74, and the chips are available in plastic leadless chip carrier, dual inline or pin grid array packages. Part of the interconnection matrix is shown in Figure 8.

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swatches

Reglstw

.

b

110

Figure 7. Logic ce// array blocks: block; b, configurable /IO block

a, configurable

clock

logic

It comprises three types of interconnect: general purpose, long lines and direct. General-purpose interconnect can be seen in Figure 8 as bundles of four horizontal and five vertical lines, located between logic blocks with switching cells at their intersection enabling selective connection of horizontal and vertical tracks, which are realized in different metal layers. Long lines run horizontally and vertically across the whole chip and bypass switches to yield low-delay tracks which can connect all CLBs or just selected columns. Direct interconnections can be realized between neighbours to reduce delays. Design using LCAs is realized using IBM PC XT or AT machines running MMI proprietary software that may be

mmable

Connected

Figure 8.

path

Interconnection

matrix

for a logic cell array

253

enhanced using a package from Futurenet. Programming of the LCA is achieved, either at powerup or on command, in serial or parallel into the storage cell RAM. For the 2064 array, 12 038 bit is required; this rises to 17 878 for the 2018. Loading can be achieved automatically from an external ROM when master mode is selected. Alternatively, peripheral and slave modes enable loading from a processor; in particular this is possible from the development system. A disadvantage of the LCA is that the configuration data is volatile and therefore lost on powerdown; however, it is possible to select a low-current option to allow retention of this data on loss of power with the simple addition of a battery backup (2 V at 20 nA). LCAs are available with toggle rates up to 70 MHz and cost between f 30 and f90. The manufacturers identify a number of possible application areas including UARTs, serial-to-parallel conversion, communication protocol translation, general interfacing and glue logic. LCAs are also likely to be extremely useful for rapid prototyping and system design verification. The family has recently been extended to offerarrays with 8000 equivalent gates.

CAD TOOLS FOR SEMICUSTOM

DESIGN

It is worthwhile considering first the way in which design is carried out. Top-down design is generally reckoned to be an ideal to aim for, but it is also true that low-level factors, such as implementation technology, can have an impact on high-level issues. In top-down design, a high-level behavioural description is derived for the system. This is essentially the specification. This description is then broken down hierarchically into progressively smaller units until it is at a level where it can be described in terms of the available building blocks. When this methodology is combined with a suitable simulator, it enables each design stage to be verified in the context of the overall system. In reality, design tends to proceed in a mixture of top-down and bottom-up or even middle-out methods, with frequent traversal of the hierarchy making modifications at various levels to improve the design. The availability of good simulation tools is a great asset in any of these scenarios.

verification patterns is a difficult problem, and one which is currently subject to a great deal of research effort. The complexity of VLSI chips is such that it is impossible to verify their operation in all possible states. However, to be aware of the problem is an advantage; at least it will be appreciated that significant effort is required in this area.

Schematic

capture

At the next stage, the chip to be designed must be described in terms of the basic functions provided by the chosen implementation technology. This typically involves entering a circuit diagram, or schematic, on a graphics screen. It is important that the capture system handles hierarchy, since hierarchy is essential in managing the complexity of VLSI systems. In a schematic capture system, hierarchy is provided by associating symbols with circuit diagrams at each level. This symbol can then be used in another circuit diagram at a higher level of the hierarchy. This is illustrated in Figure 9, which shows the circuit diagram for a binary counter constructed from a number of flipflops which in turn are built out of gates and, below that, transistors. With hierarchy supported in this manner, design can proceed in either a top-down or a bottom-up manner in accordance with the designer’s wishes.

\ 8: 03 P

04

s \

High-level

simulation

At the highest level, behavioural and functional simulators are available. These allow the designer to describe the behaviour of a system in a formal hardware description language, often an extended version of a standard highlevel computer programming language such as PASCAL. The designer must then provide input waveforms to test the system, and the simulator will produce the corresponding outputs. Such tools are very useful in developing a rigorous specification for a system. This is a key issue; too many designs flounder because the specification is inadequate - frequently being written in English, which is by its nature imprecise. Specifications should ideally be written in a behavioural language14. The specification should also include a set of design verification input and output waveforms. If an implementation stimulated by these input waveforms produces the desired output, it can be considered correct. Deriving the specification and in particular the design

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01

\

‘L

“DD

IN1 OUT IN2

Figure 9.

Example of hierarchical

description

Microprocessors

and Microsystems

Logic simulation Conceptually, high-level simulation and logic simulation are very similar. The computer is given a model of the circuit to be simulated, along with a set of input patterns, and calculates the circuit outputs. The essential difference between the two is that in high-level simulation a functional model is used, whereas in logic simulation a structural model is used. In other words, a functional model describes what the system does while a structural model describes what it is built from. Even this distinction is rather unreal because, in a logic simulator, some kind of functional model is required forthe basic building blocks, e.g. gates, and in a high-level simulator some form of structure is often present, with functional models for each element of the structure. Indeed, there is really a continuum between behavioural simulation and logic simulation, and there are many advantages for the designer if they can be combined in one simulation tool. Logic simulators vary in the way they model signals and gates. As they are dealing with digital systems, all model signals as 0 or 1, at least. Most simulators add at least one other state, frequently denoted X, to mean undefined. Many add a state denoted Z to represent high impedance, which is useful when simulating buses with many threestate drivers. A simulator using 0, 1, X and Z would be referred to as a four-state simulator. Some simulators add further values, e.g. to distinguish between 0 and 1 in the high-impedance case, or to identify signals which are currently rising or falling. The main difference between simulators in the way they model gates is in terms of delay modelling. The simplest simulators use a unit delay approach, where every gate is given an identical, arbitrary delay. Most simulators can assign actual delays to gates, giving a more realistic simulation. Some simulators can model fanoutdependent delay and may even include loading effects of the capacitance of the wires connected to the gate’s output. Simulators with complicated delay modelling or many logic states can frequently be operated optionally with a much simpler model. This has the effect of significantly reducing computer run times, and is often satisfactory for many purposes. It is general experience that the greatest amount of time in designing an ASIC is spent in the simulation phase. As each block within the design is completed, it must be verified by simulation, and deriving the input patterns is a nontrivial task. Frequently, several iterations are required to obtain a correct design. The large amount of time consumed by simulation, particularly in the case of complex designs containing many thousands of gates, has led in recent years to the launching onto the marketplace of hardware accelerators for logic simulation, sometimes known as simulation engines. A hardware accelerator has a special-purpose architecture optimized to run the types of algorithm normally associated with logic simulation. For a large design, containing hundreds of thousands of gates, simulation times can be reduced from days to hours or even minutes.

Other types of simulator There are other kinds of simulator which may be available to the designer.

Vol 72 No 5 June 7988

Switch-level

simulators

Switch-level simulators are of value in the design of MOS circuits, because they cope very well with the bidirectional components, transmission gates and pass transistors used in such technologies. However, they are not very good at modelling timing information.

Circuit simulators Circuit simulators allow the designer to describe a circuit in terms of basic components: transistors, resistors, capacitors etc. They model signals as analogue voltages and currents, and solve the equations for the circuit using numerical approximation methods. Although such simulators are vital to the designer of full custom chips, they are not usually necessary for semicustom devices. This is because the cells used in a semicustom approach will already be well characterized, and the data will be encapsulated in the delay modelling information used in the logic simulator.

Timing

verification

In many cases, the only tool available to the designer for timingverification will be the logic simulator. Provided the designer has used safe, synchronous logic design techniques, there should be no danger of race or other such timing-related problems in the design. Howeverwell gate delays are modelled, there is no guarantee of identifying and exercising the critical paths during a functional simulation. A better approach to adopt is static analysis, where the circuit is analysed to search for such critical paths and calculate their maximum delays. This can lead to an overpessimistic result, as not all critical paths can in fact be exercised in some circuits, but at least it will err on the side of caution. Where this sort of automatic tool is not available, it is up to the designer to do this manually. Naturally, having identified the critical paths, the design can be modified to improve its performance if required by concentrating efforts on these paths.

Testability

and testing

It is crucial to take testing of ICs into account at the design stage’ ‘8 ’ 6. Products can only be thoroughly tested if they are designed to be testable right from the initial concept. In contrast to PCBs, chips can only be tested by access to their external connections. The aim of test pattern generation is to derive a minimum set of test patterns which, when applied to the external inputs of a chip, enables all modelled faults to be detected at its external outputs. This is a nontrivial task and, particularly in the case of more complex chips, some form of design-fortestability technique must be adopted. The options here include partitioning, ad hoc techniques, scan design and built-in self test. There are various types of computer tools which can assist in the test pattern generation process. Fault simulators allow the circuit to be simulated in the presence of certain modelled faults. Such simulators allow the assessment of the fault cover of a set of test patterns, i.e. what proportion of faults is detected by them. Automatic test pattern generation programs attempt to derive test patterns which will actually detect specific

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faults by analysis of the circuit. Testability analysis programs attempt to assess the overall testability of a circuit, and of individual faults in the circuit; these can indicate to the designer that certain parts of the circuit ought to be reworked before proceeding to full test pattern generation. However, in spite of the existence of such tools as these, there can be no doubt that design for testability is essential for more complex chips.

Placement tools are often highly interactive, permitting the designer considerable control over the placement. This can be useful, particularly where difficulty is encountered in routing a chip; however, considerable experience is required to know how best to assist the computer in its task.

Routing

Physical

layout

For both gate arrays and standard cells, the layout phase is typically much shorter than the logic design phase. The layout phase is largely automatic, although some designer interaction may be required or desirable in some cases. The layout task is split into two subtasks: placement and routing. Placement The aim of the placement process is to position the components within the chip so as to make the routing task easier. As it is not possible or practical to attempt to route every possible placement to establish the quality of the placement, some kind of heuristic must be developed to assess the quality of a particular placement. Two factors which are typically taken into account in this process are the predicted total length. of the interconnecting tracks, possibly with a different weighting for horizontal and vertical segments, and wiring congestion in certain regions of the chip. In the case of gate arrays, the cells and routing channels are fixed in position, and the placement task consists of assigning particular circuit elements to particular cells in the array. With standard cells, the elements must be assigned approximate positions in rows, but can essentially be placed anywhere on the silicon. The placement process is, in fact, more critical for gate arrays, where the fixed routing channels make routing difficult as channels can become full. With standard cells, the routing channels can be made just the right width to accommodate the required wires. This does not, however, excuse the use of a bad placement which will produce a large and therefore costly chip with poor performance, due to the high capacitance of the unnecessarily long tracks. The placement task is usually divided into two phases: global placement and local optimization. Global placement attempts to put the components in approximately the right place, and local optimization tries swapping the location of various components to see if any improvement can be made. In the global placement process, the external connections (pads) will typically be placed first, as these are often fixed due to external considerations. The internal components will then be placed in proximity to those components already placed to which it has connections. One method of orderingthe placement is at each stage to place the component which has the highest connectivity to those already placed. An alternative is to place larger components first, followed by smaller components. The majority of placement tools do not make any use of the hierarchy of the circuit design. This is a disadvantage, because it is frequently sensible to keep together components belonging to a particular block in the hierarchy.

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The routing task consists of connecting together the components which have already been placed in the chip layout design. Routing is usually performed using two layers of interconnect, either two layers of metal or one of polysilicon and one of metal. Usually one layer is used for vertical routing and the other for horizontal. Some gate arrays are customized using only a single metal layer; in this case routing is performed using this layer in conjunction with fixed polysilicon underpasses. Almost invariably, routing channels are provided on the chips in between rows of components. Routing is essentially a fully automatic task, in contrast to placement which can be interactive. It is also a timeconsuming process, often taking several hours of CPU time on atypical workstation. This is especially true in the case of gate arrays, which are by their nature more difficult to route than cell-based designs. Unfortunately, the result of the routing is not always what is desired. With gate arrays, it may simply not be completed. With standard cells, the chip may be too big, or the wrong shape; the variable routing channels make this a real possibility. One approach in dealing with such problems is to try a different placement and give the router another try. Iterating round this loop can, however, be very time consuming due to the time taken by the router. For gate arrays, manual routing may also be available, although it can be very difficult if not impossible to route the last few connections which the computer has failed to route, and it may be necessary to ‘rip up’ significant portions of the computer routing. Some layout systems allow the designer to’rip up’some of the tracks, do some manual routing and then try to complete the task again automatically. This can be very useful. In any case, where gate arrays are concerned, good manual routing tools are essential, and these should embody checks to ensure that the designer is forbidden from making incorrect connections. Back annotation The long interconnection tracks often produced by the layout processes can have a significant impact on the petiormance of the chip, on account of the capacitive load they present to the gate outputs. It is therefore important that timing is verified after the layout has been completed using the actual track capacitances, which can easily be calculated, There are two principal ways in which this can be carried out. In the first approach, a maximum capacitance for each track will be specified at the circuit design stage, and this will be used in the timing analysis. The actual values need then only be compared with these maximum values and, provided they are not exceeded, no further action need be taken. In the second approach, the extracted track capacitances are back annotated into the circuit database, permitting the timing analysis to be performed a second time using the actual values of capacitance. In both cases the circuit performance is verified to a high degree of accuracy.

Microprocessors

and Microsystems

Libraries In all the preceding sections, it has been assumed that libraries have been available for all the stages of the design process. Indeed, fundamental to any gate array or standard cell systems is a library of basic components which can be used to build up circuits. There needs to be a set of libraries, each describing different aspects of the components. For the purposes of schematic capture, there needs to be a library of symbols which can be used to build up the circuit diagrams. Each component also requires an associated simulation model, including information on its timing properties, permitting use in a logic simulator. Finally, a physical model is required, describing the characteristics in layout terms. This will include shape, size and the location of the external connections. In the case of gate arrays, the layout tools also need a detailed description of the locations of all the prefabricated devices on the chip and mappings of physical library cell components on those devices.

Silicon

compilers

The concept of the silicon compiler is derived from an analogy with the software compiler that generates machine code to run on a computer from a program written in a high-level language. The software compiler is a completely general-purpose tool; any algorithm that can be expressed in terms of the high-level language may be turned into machine code to run on a computer. Ideally the silicon compiler should offer the same degree of generality. Thus any data processing algorithm that can be expressed in a suitable high-level hardware description language should, after being operated on by a silicon compiler, lead to the generation of a set of masks to run on a particular IC fabrication process. The current state of the art in silicon compilation is still some way removed from the ideal situation stated above. Of the silicon compilers that have so far been developed, most are constrained to deal with only one type of architecture and to generate mask layouts that conform to some prearranged floor plan. The designer can experiment by trying out different algorithms written in the highlevel description language to see what effect these have on the overall size and performance of the finished chips. A fundamental principle underlying the silicon compiler is that the designer should never be allowed to interfere with a design at the lowest level, i.e. the layout level. Some silicon compilers are constrained in a different way to that described above in that they may compile onto a gate array type of architecture. The term ‘silicon compiler’ can in fact be applied to any tool that converts a description of hardware expressed as some kind of highlevel language directly into silicon.

Database Typically there may be two databases containing circuit and layout information respectively. The task of a database is not only to store the data but also to maintain its integrity, and so the management involves maintaining a one-to-one correspondence between circuit and layout descriptions. Hence the use of a single database is preferable. In either case, tools to maintain this integrity must be provided.

Vol 72 No 5 June 7988

Project management tools are also closely associated with the database, if not part of it. They cover such areas as design state control, whereby any particular blocks may be ‘released’ for general use once they have been verified and the system will forbid further changes to released blocks. Such tools are particularly important when a design is carried out by a team rather than an individual designer. They greatly assist the designer in ensuring that the entire design has been adequately verified before sending it off for fabrication.

ROUTES TO FABRICATION When the design is completed and verified, it must be passed to a silicon vendor for fabrication. This may seem straightforward, but there is one large problem: whose fault is it if the chips simply do not work? This is a contractual issue which must be clearly defined in the interests of both parties.

Customer-vendor

interface

In most cases involving gate array or cell-based design the customer will be fairly closely tied in with the vendor of the specific system chosen. The stage at which data is passed to the vendor varies considerably. The more traditional approach is for the user to perform his/her own logic design and simulation, but to leave the placement and routing to the silicon vendor. In this case, the vendor will require the user to supply a logic diagram, preferably in machine readable form, and a set of simulation results. The vendor will resimulate the circuit to verify that the results agree with the user’s simulations. Once this has been established to the satisfaction of both parties, the vendor will contract to produce chips which will perform in accordance with the specification. It is, however, becoming more and more common for customers to do their own placement and routing, largely because of pressure on the vendor’s CAD department. This also avoids the problem of the simulation being performed twice, possibly on different CAD systems. It is important that the vendor has control of the CAD systems being used, and thus can again contract to produce chips which will perform in accordance with the specification. A vendor-specific CAD system has significant advantages in this respect compared with a general-purpose system. However it is achieved, it is very important that the user and vendor agree on a set of acceptance tests before fabrication takes place.

Fast turnaround

techniques

There is a great deal of interest amongst existing and potential users of ASlCs in methods for processing designs in very short timescales (i.e. days rather than weeks). One reason for this is a desire for fast prototyping of designs, while another is the frequent requirement to rework a design (perhaps to correct an error or include a modification) very quickly indeed so that it does not hold up the release of a new product. The technique that has received most attention in the context of fast turnaround is the commitment of gate arrays using direct-write electron-beam lithography. No

257

mask is required in this process; the fully metallized wafer is coated with an electron-sensitive resist layer and this is then scanned by an electron beam. A number of different gate array designs can be written directly onto a single silicon wafer, thus drastically reducing the cost per design. The time required for the machine to commit the metal layer of a wafer full of gate array chips may be as little as one hour, thus enabling a true fast turnaround service to be provided. The machine could also cope with a very large throughput, the only disadvantage being the high capital cost of the equipment.

COST

500

h

t

\

,Full

custom

Cell

based

COMPARISONS

Table 1 shows three columns of figures which can be taken as representative of the principal mask programmable ASIC options, i.e. gate arrays, cell-based custom and full custom. The gate array column assumes that only a single customizing mask is needed to pattern a single layer of metallization; modern arrays featuring double-layer metal will typically require three masks. The cell-based custom and full custom columns each show a requirement for eight custom masks, this number being appropriate for a basic single-layer metal CMOS process. More advanced processes with double-layer metal may demand 1 O-l 2 masks. The chip sizes given in the table are arbitrary and the only significance they have is in the relative amounts of silicon area consumed. It isassumed here that the designs being integrated using each of the different design styles are comparable in terms of complexity, overall number of transistors or gates etc. A yield of 40% working chips has been assumed for all of the design styles on the grounds that any yield improvement per unit area in the case of the semicustom methodologies will be offset by their larger overall chip areas compared with full custom chips. Simple calculations using the figures provided in the table permit the total number of chips and the actual yield of working chips to be evaluated for a wafer of 100 mm diameter. The final row in Table 1 indicates the level of effort typically needed to complete a design using the three methods under comparison. Again the figures are arbitrary and the only real significance is in their relative values, assuming designs of uniform complexity. A simple formula can be devised to calculate the unit cost of a chip, C, as a function of the number N of units produced mD+nM C=

Table 1.

N

W +--+ Y

P

Typical data for cost comparisons

Parameter No. of custom masks Chip size (mm2) Yield No. of chips per 100 mm wafer No. of working chips Design time (man months)

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tL

Gate array 1

Cell based

a

Number

Figure 70.

of

chips

produced

AS/C cost comparisons

where m = design time in man months;‘n = number of custom masks required; y = yield of working chips; D = cost of design effort per man month; M = cost per custom mask; W = cost per wafer; P = cost of packaging and test per chip. Let us assume some typical figures for the cost parameters listed above D = f3000 per man month M = fl200 per mask W = f400 per wafer P = f2.50per chip Notice that the first term in the cost equation containing the ‘up-front’ design costs and tooling charges (principally mask making) reduces linearly as production volume N increases. The other two terms are independent of N and therefore represent a fixed overhead per chip. Using the data provided above, and plotting C as a function of N, we obtain the curves shown in Figure 10. It is evident from this diagram that design costs are by far the most dominant contribution to the cost per chip at low production volumes, particularly for the full custom option. The shorter design timescales associated with the two semicustom techniques have a significant impact on reducing the cost per chip in this region. As N increases the design costs (and mask-making costs) are spread over a greater number of units of production until eventually the fixed silicon and packaging costs become dominant at high production volumes (> lo5 units).

Full custom

a

5 x 5.5 40% - 285

4.5 x 4.5 40% - 388

3.5 x 4 40% - 560

114

155

224

3

3

ia

SUMMARY

AND

ACKNOWLEDGEMENTS

This paper has attempted to provide an overview of semicustom IC techniques, the CAD tools required and routes to fabrication. Some of the material it contains has been adapted from a series of tutorials which were first presented at the 7th International Conference on Custom and Semicustom ICs held in London, UK, during November 1987. The cooperation of the organizers of the conference in allowing parts of this material to be reproduced here is gratefully acknowledged.

Microprocessors

and Microsystems

REFERENCES 1 2

3

4 5 6 7

8

9

10

Read, J W Gate arrays: design and applications Collins, London, UK (1985) York, T A ‘Semicustom IC design using gate arrays’ Microprocessors Microsyst Vol 12 No 6 (July/August 1988) to be published Davidson, S ‘Structured arrays - the next generation gate arrays’ Proc. 5th Int Conf. Custom and Semicustom ICs (1985) ‘Survey of gate arrays and cell libraries’ VLSf Syst Des. Vol 7 No 11 (November 1986) pp 54-86 ‘Buyers guide to ASlCs and ASIC design tools’ Comput Des. (15 August 1987) Fox, J ‘Cell-based design: a review’ IEE Proc. I Vol133 (June 1986) pp 77-82 Brothers, J S, Tomkins, J W and Williams, J S ‘The Megacell concept: an approach to painless custom design’ IEE Proc. E Vol 132 (March 1985) pp 91-98 Williams, J S, Pritchard, W D, Clewett, D R and Prior, B J 'Megacell - a design system for CMOS VLSI’ Proc. ESSCfRC 84 (September 1984) pp 127-I 31 Hall, C and Trickey, C ‘Microprocessor cores on standard cells: a feasibility study using Intel’s 8OC51 core’ Proc. 7th fnt Conf. Custom and Semicustom ICs, London, UK (November 1987) Green, D Modern logic design Addison-Wesley, Wokingham, UK (1986)

Peter Hicks was promoted to senior lecturer in the of Electrical Department Engineering and Electronics University of at the institute of Manchester Science and Technology (UMIST), UK, in 7985. Since joining the department he has developed the MSc course in integrated circuit system design at UMIST and is manager of the fntegrated Circuit Design and Test Centre at the same establishment, His research interests are in integrated sensor arrays and he has collaborated on the development of a series of position-sensitive multidetector systems.

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11 12 13 14

15 16

PAYPLA devices, programmable logic array handbook Monolithic Memories, Santa Clara, CA, USA Technical handbook 4: integrated circuits, part 7a, programmable logic devices Mullard, London, UK introducing the Logic Cell Array Monolithic Memories Santa Clara, CA, USA Miles, J ‘Ella - not just a hardware design and description language’ Proc. 3rd Silicon Design Conf., London, UK (July 1986) pp 65-76 Bennetts, R C Design of testable logic circuits Addison-Wesley, Wokingham, UK (1984) Wilkins, B R Testing digital circuits Van Nostrand Reinhold, Wokingham, UK (1986)

Robert Cottreff is a lecturer in the Department of Electrical Engineering and Electronics at UMfST, UK. He obtained his BSc in 1978, his MSc in 1979andhisPhDin7987,all at UMIST. His research interests are in VLSI design and CAD. Current projects are in silicon compiler tools for digita/ signal processing systems and in logic synthesis. Previous work has been on the design of special-purpose digital signal processors and on circuit extraction from IC layout

Trevor York is a lecturer in the Department of Electrical Engineering and Electronics at UMIST, UK. His research interests focus on integrated sensor arrays and aspects of wafer-scale integration. He received a PhD in physics from Manchester University, UK, in October 7982. The research primarily involved the development of a position-sensitive detector of low-energy electrons based on a charge-coupled device. Prior to this he was awarded a BSc in physics at the same institution in fuly 7979.

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