- Email: [email protected]
Carbon nanotube capacitors arrays using high-k dielectrics
Diamond & Related Materials 19 (2010) 221–224
Contents lists available at ScienceDirect
Diamond & Related Materials j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / d i a m o n d
Carbon nanotube capacitors arrays using high-k dielectrics Y. Choi a,⁎, L.E. Mosley b, Y. Min c, G.A.J. Amaratunga a a b c
Electrical Engineering Division, Department of Engineering, University of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 0FA, UK Intel Corporation, Santa Clara, California 95054, USA Intel Corporation, Chandler, Arizona 85226, USA
a r t i c l e
i n f o
Available online 29 September 2009 Keywords: Nanotubes Electrical properties characterization Electronic device structures
a b s t r a c t The electrical characteristics and fabrication process of nanocapacitor arrays using metal-high-k dielectriccarbon nanotube-metal layers (MICntM) were studied. MWCNTs arrays were fabricated using an electron beam lithography based lift-off process for catalyst definition and the high-k dielectric layer, hafnium oxide (HfO2), was deposited using rf magnetron sputtering. The MICntM structures show high capacitance and the compatibility with high-k dielectric material and its deposition processes. MICntM capacitors arrays with sputtered HfO2 show specific capacitance of 0.62 μF/cm2. The leakage current density at 1 V is less than 5 μA/cm2. The high aspect ratio of MWCNTs increases the effective electrode area and HfO2 allows higher permittivity, hence, higher capacitance structures are realized. © 2009 Elsevier B.V. All rights reserved.
1. Introduction Demanding higher capacitance structures for most applications should demonstrate a very high capacitance along with ultra-high integration density. In Si technology, the silicon pillar structure and high-k dielectric materials have been investigated as a solution, but there have been challenges to tackle the complexity of bottom electrode fabrication and low reliability [1,2]. Carbon nanotubes (CNTs) are an alternative to the traditional Si pillar to achieve high integration density of nanostructures. Since vertically aligned CNTs are obtained by a simple growth process, compared to precise etching/machining for Si, nanopillar, structures with a high aperture ratio can be readily obtained [3–5]. Multiwall carbon nanotubes (MWCNTs) arrays using patterned catalysts can be grown vertically by direct current plasma enhanced chemical vapor deposition (dc-PECVD) [6]. Using this technology, dimensions of MWCNTs can be controlled and a high degree of uniform growth is also achievable. Hafnium dioxide (HfO2) is a high-k dielectric which could replace silicon dioxide as the gate insulator in CMOS [7,8] and optoelectronic devices [9], allowing a thicker dielectric layer for low leakage current and high gate capacitance. However, in Si platforms, it is known that an interfacial layer of SiO2 will limit the highest possible gate capacitance since the dielectric layer in series will limit the total capacitance. Using MWCNTs, the interfacial layer formation will be minimized and the maximum capacitance can be achieved. HfO2 films can be prepared by e-beam evaporation [10], atomic layer deposition [9], and sputtering [11,12]. Among the techniques, sputtering enables deposition of HfO2 in a standard manner at low cost. Therefore, the
⁎ Corresponding author. Tel.: +44 1223 748318; fax: +44 1223 748348. E-mail address: [email protected] (Y. Choi). 0925-9635/$ – see front matter © 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.diamond.2009.09.005
combination of MWCNTs with high-k dielectric can be an ultimate solution to demonstrate higher capacitance structures with nanoscale elements. Here, we report the electrical characteristics and fabrication process of nanocapacitor arrays using metal-high-k dielectric-carbon nanotube-metal layers (MICntM). 2. Experiment Arrays of 200 nm wide dot patterns on p+ Si substrates were written using electron beam lithography. The pitch between dots was varied to explore the process window and to investigate the density dependence on electrical characteristics of MICntM capacitors arrays. As the bottom electrode, Nb thin film was deposited on the patterned substrates and then Ni a catalyst layer deposition was carried out using rf magnetron sputtering. Catalyst dots arrays were transferred using a lift-off technique. Fig. 1 shows the fabrication process flow of MICntM capacitors. MWCNTs were grown in a dc-PECVD system and a detailed description of MWCNTs growth can be found elsewhere [6]. Then high-k dielectric layer, hafnium oxide (HfO2), was deposited at room temperature directly from a metallic hafnium target by rf magnetron sputtering in an Ar/O2 gas mixture. HfO2 on flat Si surface showed the dielectric constant to be 7.76. Al was deposited as the top electrode by sputtering and the electrode area was 200 μm × 200 μm. Current-voltage (I-V) and capacitance-voltage (C-V) characteristics were obtained using HP 4140B and HP 4192A parametric analyzers respectively. 3. Results and discussion The MWCNTs growth process consists of four stages; substrate pretreatment (forming a diffusion barrier, i.e. bottom electrode), catalyst
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Fig. 1. A schematic diagram of MICntM capacitors fabrication processes. (a) Nb as bottom electrode and Ni catalyst dots arrays were formed using electron beam lithography. (b) Vertically aligned MWCNTs were grown by dc-PECVD. (c) Dielectric layer, HfO2, was deposited from hafnium target using sputtering. (d) Al top electrode was formed by sputtering.
deposition, catalyst annealing (sintering), and then nanotube growth. The initial catalyst layer is formed into islands or nanospheres by annealing at high temperature. It has been reported that the Ni breaks into small islands due to surface tension, as well as compressive stress due to the mismatch of the thermal expansion coefficients of Si and Ni [13,14]. However, naturally shaped catalyst islands result in nonuniform growth of MWCNTs in diameter and height [15]. For high capacitance device applications, it is highly desirable that the individual CNTs are properly spaced to accommodate the dielectric and metal layers. It is important to note that there is a huge difference between the nucleation of multiple CNTs from a ‘large’ catalyst film and the growth of a single isolated CNT from a ‘small’ catalyst dot. It is apparent that the large catalyst formed a line of multiple CNTs which had a significant variation in diameter and height. In contrast, the array of small catalyst dots produced relatively uniform CNTs. The key difference is that at 700 °C, the large catalyst region coalesces to form multiple nanoclusters of different sizes which then catalyzes the growth of uneven CNTs. For isolated 200 nm catalyst dots in the array, a single nanocluster of fixed volume/size was formed from each dot which led to more identical CNTs [6]. Fig. 2 shows scanning electron microscopy (SEM) images of catalyst dots and MWCNTs arrays. As seen, a single MWCNT grows from each 200 nm square catalyst dot. The density of nanotubes can be defined as the number of catalyst dots per unit area. In addition, the diameter of the nanotube can be controlled by the initial thickness of catalyst and the size of catalyst dot. This technique shows how the density of CNTs should be managed for demanding applications.
In principle the high aspect ratio of MWCNTs will lead to high capacitance because of increased electrode area, but it also will introduce issues of the step coverage on MWCNTs. Chemical vapor deposition (CVD) methods will deliver better step coverage than physical vapor deposition (PVD) methods in general. In order to verify the step coverage with sputtered HfO2 and Al on MWCNTs, SEM images of MICntM capacitors were taken from the bottom (Fig. 3(a)) to the top (Fig. 3(b)) of device. Fig. 3 shows MWCNTs at this density were fairly well coated with HfO2 and Al using sputtering whilst there is some roughness. The capacitance and leakage current density for various MWCNT array pitches are shown in Fig. 4. Devices having two different pitches of dot patterns were fabricated to compare with a fundamental metalinsulator-metal (MIM) structure. One is where the catalyst was patterned in 200 nm wide square dots with 1000 nm perpendicular pitch and the other is with 600 nm perpendicular pitch. For both devices, the horizontal pitch was 600 nm. MWCNTs were vertically grown on both simultaneously in a single deposition. The average height and diameter of MWCNTs were 1.5 μm and 100 nm respectively. A 50 nm thick HfO2 layer was deposited on the substrate while 30 nm HfO2 was formed on the MWCNTs sidewall. Subsequently a 100 nm thick Al was sputtered as the top electrode (200 μm × 200 μm). The capacitance and leakage current density as a function of voltage are shown in Fig. 4(a) and (b). The capacitance of the 600 nm pitch pattern is about two times higher compared to an equivalent MIM structure. This is mainly due to the increased effective electrode
Y. Choi et al. / Diamond & Related Materials 19 (2010) 221–224
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Fig. 2. SEM pictures of 200 nm wide, 8 nm thick Ni catalyst dot arrays whose perpendicular pitches were (a) 1000 nm and (b) 600 nm respectively and the horizontal pitches were 600 nm for both. Ni dots have been transferred onto Si with 20 nm Nb using electron beam lithography. (c) and (d) are SEM images of as grown MWCNTs arrays from (a) and (b) respectively. The scale bar corresponds to 1 μm.
area achieved by incorporating MWCNTs. The details of the enhanced mechanism can be found in our previous work [16]. However, from a cylindrical capacitance model [17,18] we can estimate the possible maximum capacitances of MICntM structures. If all parameters are as stated above, the capacitance of one single MICntM capacitor is 1.335 fF and therefore the capacitance by connecting 11100 MICntM capacitors in parallel (200 μm × 200 μm/0.36 μm2) is about 0.150 nF. In addition there is a flat surface area (=(200 μm × 200 μm) − (200 nm × 200 nm × 11100) = 35.56 × 10− 9 m2) and its capacitance from a planar capacitor model is 0.048 nF. Hence the total capacitance of MICntM structures can be as high as 0.198 nF. The experimental value shows a total capacitance of 0.184 nF, only an 8% reduction compared to the possible maximum. The leakage current density is about two orders of magnitude higher than in MIM structure, however, it is less than 5 μA/cm2 at 1 V. The increase in the leakage current is likely to be associated with non-uniform conformal dielectric deposition on MWCNTs.
4. Conclusions
Fig. 3. SEM images of MICntM capacitors arrays (a) at the bottom and (b) at the top. It shows decent step coverage with sputtered HfO2 and Al layers on MWCNTs. The scale bar corresponds to 1 μm.
The MICntM structures using HfO2 showed high capacitance. The compatibility of using high-k dielectric material and its deposition process with vertically aligned MWCNT arrays is demonstrated. It is important to note that the individual CNTs are properly spaced to accommodate the dielectric and metal layers. In order to achieve this, fine patterns of catalyst dots have been produced by electron beam lithography. The high aspect ratio of MWCNTs increase the effective electrode area and HfO2 allows higher permittivity, hence, higher capacitance structures are realized. The MICntM structure is a potential candidate to replace the Si pillar structures in nanoelectronic applications.
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Y. Choi et al. / Diamond & Related Materials 19 (2010) 221–224
References [1] B. Nagaraj, T. Sawhney, S. Perusse, S. Aggarwal, V.S. Kaushik, S. Zafar, R.E. Jones, J.-H. Lee, V. Balu, J. Lee, Appl. Phys. Lett. 74 (1999) 3194. [2] S.J. Lee, C.R. Cho, M.S. Kang, M.S. Jung, K.Y. Kang, Appl. Phys. Lett. 68 (1996) 764. [3] S. Iijima, Nature 354 (1991) 56. [4] A.M. Morales, C.M. Liber, Science 279 (1998) 208. [5] M. Tanase, L.A. Bauer, A. Hultgren, D.M. Silevitch, L. Sun, D.H. Reich, P.C. Searson, G.J. Meyer, Nano Lett. 1 (2001) 155. [6] K.B.K. Teo, S.-B. Lee, M. Chhowalla, V. Semet, V.T. Binh, O. Groening, M. Castignolles, A. Loiseau, G. Pirio, P. Legagneux, D. Pribat, D.G. Hasko, H. Ahmed, G.A.J. Amaratunga, W.I. Milne, Nanotechnology 14 (2003) 204. [7] M.J. Esplandiu, E.M. Patrito, V.A. Macagno, Electrochim. Acta 40 (1995) 809. [8] M.J. Esplandiu, E.M. Patrito, V.A. Macagno, Electrochim. Acta 42 (1997) 1315. [9] K. Kukli, J. Ihanus, M. Ritala, M. Leskela, Appl. Phys. Lett. 68 (1996) 3737. [10] Y. Tsou, F.C. Ho, Appl. Opt. 35 (1996) 5091. [11] K. Kita, K. Kyuno, A. Toriumi, Appl. Phys. Lett. 85 (2004) 54. [12] Y.-S. Suh, H. Lazar, B. Chen, J.-H. Lee, V. Misra, J. Electrochem. Soc. 152 (9) (2005) F138. [13] C. Bower, O. Zhou, W. Zhu, D.J. Wender, S. Jin, Appl. Phys. Lett. 77 (2000) 2767. [14] V.I. Merkulov, D.H. Lowndes, Y.Y. Wei, G. Eres, E. Voelkl, Appl. Phys. Lett. 76 (2000) 3555. [15] M. Chhowalla, K.B.K. Teo, C. Ducati, N.L. Rupesinghe, G.A.J. Amaratunga, A.C. Ferrai, D. Roy, J. Robertson, W.I. Milne, J. Appl. Phys. 90 (2000) 5308. [16] J.E. Jang, S.N. Cha, Y. Choi, D.J. Kang, D.G. Hasko, J.E. Jung, J.M. Kim, G.A.J. Amaratunga, Appl. Phys. Lett. 87 (2005) 263103. [17] R. Martel, T. Schmidt, H.R. Shea, T. Hertel, Ph. Avouris, Appl. Phys. Lett. 73 (1998) 2477. [18] H.T. Ng, J. Han, T. Yamada, P. Nguyen, Y.P. Chen, M. Meyyappan, Nano Lett. 4 (2004) 1247.
Fig. 4. (a) Capacitance-voltage (C-V) characteristics and (b) leakage current density of MICntM capacitors.
Acknowledgements This work was funded in part by support from Intel Corporation, USA.
Contents lists available at ScienceDirect
Diamond & Related Materials j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / d i a m o n d
Carbon nanotube capacitors arrays using high-k dielectrics Y. Choi a,⁎, L.E. Mosley b, Y. Min c, G.A.J. Amaratunga a a b c
Electrical Engineering Division, Department of Engineering, University of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 0FA, UK Intel Corporation, Santa Clara, California 95054, USA Intel Corporation, Chandler, Arizona 85226, USA
a r t i c l e
i n f o
Available online 29 September 2009 Keywords: Nanotubes Electrical properties characterization Electronic device structures
a b s t r a c t The electrical characteristics and fabrication process of nanocapacitor arrays using metal-high-k dielectriccarbon nanotube-metal layers (MICntM) were studied. MWCNTs arrays were fabricated using an electron beam lithography based lift-off process for catalyst definition and the high-k dielectric layer, hafnium oxide (HfO2), was deposited using rf magnetron sputtering. The MICntM structures show high capacitance and the compatibility with high-k dielectric material and its deposition processes. MICntM capacitors arrays with sputtered HfO2 show specific capacitance of 0.62 μF/cm2. The leakage current density at 1 V is less than 5 μA/cm2. The high aspect ratio of MWCNTs increases the effective electrode area and HfO2 allows higher permittivity, hence, higher capacitance structures are realized. © 2009 Elsevier B.V. All rights reserved.
1. Introduction Demanding higher capacitance structures for most applications should demonstrate a very high capacitance along with ultra-high integration density. In Si technology, the silicon pillar structure and high-k dielectric materials have been investigated as a solution, but there have been challenges to tackle the complexity of bottom electrode fabrication and low reliability [1,2]. Carbon nanotubes (CNTs) are an alternative to the traditional Si pillar to achieve high integration density of nanostructures. Since vertically aligned CNTs are obtained by a simple growth process, compared to precise etching/machining for Si, nanopillar, structures with a high aperture ratio can be readily obtained [3–5]. Multiwall carbon nanotubes (MWCNTs) arrays using patterned catalysts can be grown vertically by direct current plasma enhanced chemical vapor deposition (dc-PECVD) [6]. Using this technology, dimensions of MWCNTs can be controlled and a high degree of uniform growth is also achievable. Hafnium dioxide (HfO2) is a high-k dielectric which could replace silicon dioxide as the gate insulator in CMOS [7,8] and optoelectronic devices [9], allowing a thicker dielectric layer for low leakage current and high gate capacitance. However, in Si platforms, it is known that an interfacial layer of SiO2 will limit the highest possible gate capacitance since the dielectric layer in series will limit the total capacitance. Using MWCNTs, the interfacial layer formation will be minimized and the maximum capacitance can be achieved. HfO2 films can be prepared by e-beam evaporation [10], atomic layer deposition [9], and sputtering [11,12]. Among the techniques, sputtering enables deposition of HfO2 in a standard manner at low cost. Therefore, the
⁎ Corresponding author. Tel.: +44 1223 748318; fax: +44 1223 748348. E-mail address: [email protected] (Y. Choi). 0925-9635/$ – see front matter © 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.diamond.2009.09.005
combination of MWCNTs with high-k dielectric can be an ultimate solution to demonstrate higher capacitance structures with nanoscale elements. Here, we report the electrical characteristics and fabrication process of nanocapacitor arrays using metal-high-k dielectric-carbon nanotube-metal layers (MICntM). 2. Experiment Arrays of 200 nm wide dot patterns on p+ Si substrates were written using electron beam lithography. The pitch between dots was varied to explore the process window and to investigate the density dependence on electrical characteristics of MICntM capacitors arrays. As the bottom electrode, Nb thin film was deposited on the patterned substrates and then Ni a catalyst layer deposition was carried out using rf magnetron sputtering. Catalyst dots arrays were transferred using a lift-off technique. Fig. 1 shows the fabrication process flow of MICntM capacitors. MWCNTs were grown in a dc-PECVD system and a detailed description of MWCNTs growth can be found elsewhere [6]. Then high-k dielectric layer, hafnium oxide (HfO2), was deposited at room temperature directly from a metallic hafnium target by rf magnetron sputtering in an Ar/O2 gas mixture. HfO2 on flat Si surface showed the dielectric constant to be 7.76. Al was deposited as the top electrode by sputtering and the electrode area was 200 μm × 200 μm. Current-voltage (I-V) and capacitance-voltage (C-V) characteristics were obtained using HP 4140B and HP 4192A parametric analyzers respectively. 3. Results and discussion The MWCNTs growth process consists of four stages; substrate pretreatment (forming a diffusion barrier, i.e. bottom electrode), catalyst
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Fig. 1. A schematic diagram of MICntM capacitors fabrication processes. (a) Nb as bottom electrode and Ni catalyst dots arrays were formed using electron beam lithography. (b) Vertically aligned MWCNTs were grown by dc-PECVD. (c) Dielectric layer, HfO2, was deposited from hafnium target using sputtering. (d) Al top electrode was formed by sputtering.
deposition, catalyst annealing (sintering), and then nanotube growth. The initial catalyst layer is formed into islands or nanospheres by annealing at high temperature. It has been reported that the Ni breaks into small islands due to surface tension, as well as compressive stress due to the mismatch of the thermal expansion coefficients of Si and Ni [13,14]. However, naturally shaped catalyst islands result in nonuniform growth of MWCNTs in diameter and height [15]. For high capacitance device applications, it is highly desirable that the individual CNTs are properly spaced to accommodate the dielectric and metal layers. It is important to note that there is a huge difference between the nucleation of multiple CNTs from a ‘large’ catalyst film and the growth of a single isolated CNT from a ‘small’ catalyst dot. It is apparent that the large catalyst formed a line of multiple CNTs which had a significant variation in diameter and height. In contrast, the array of small catalyst dots produced relatively uniform CNTs. The key difference is that at 700 °C, the large catalyst region coalesces to form multiple nanoclusters of different sizes which then catalyzes the growth of uneven CNTs. For isolated 200 nm catalyst dots in the array, a single nanocluster of fixed volume/size was formed from each dot which led to more identical CNTs [6]. Fig. 2 shows scanning electron microscopy (SEM) images of catalyst dots and MWCNTs arrays. As seen, a single MWCNT grows from each 200 nm square catalyst dot. The density of nanotubes can be defined as the number of catalyst dots per unit area. In addition, the diameter of the nanotube can be controlled by the initial thickness of catalyst and the size of catalyst dot. This technique shows how the density of CNTs should be managed for demanding applications.
In principle the high aspect ratio of MWCNTs will lead to high capacitance because of increased electrode area, but it also will introduce issues of the step coverage on MWCNTs. Chemical vapor deposition (CVD) methods will deliver better step coverage than physical vapor deposition (PVD) methods in general. In order to verify the step coverage with sputtered HfO2 and Al on MWCNTs, SEM images of MICntM capacitors were taken from the bottom (Fig. 3(a)) to the top (Fig. 3(b)) of device. Fig. 3 shows MWCNTs at this density were fairly well coated with HfO2 and Al using sputtering whilst there is some roughness. The capacitance and leakage current density for various MWCNT array pitches are shown in Fig. 4. Devices having two different pitches of dot patterns were fabricated to compare with a fundamental metalinsulator-metal (MIM) structure. One is where the catalyst was patterned in 200 nm wide square dots with 1000 nm perpendicular pitch and the other is with 600 nm perpendicular pitch. For both devices, the horizontal pitch was 600 nm. MWCNTs were vertically grown on both simultaneously in a single deposition. The average height and diameter of MWCNTs were 1.5 μm and 100 nm respectively. A 50 nm thick HfO2 layer was deposited on the substrate while 30 nm HfO2 was formed on the MWCNTs sidewall. Subsequently a 100 nm thick Al was sputtered as the top electrode (200 μm × 200 μm). The capacitance and leakage current density as a function of voltage are shown in Fig. 4(a) and (b). The capacitance of the 600 nm pitch pattern is about two times higher compared to an equivalent MIM structure. This is mainly due to the increased effective electrode
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Fig. 2. SEM pictures of 200 nm wide, 8 nm thick Ni catalyst dot arrays whose perpendicular pitches were (a) 1000 nm and (b) 600 nm respectively and the horizontal pitches were 600 nm for both. Ni dots have been transferred onto Si with 20 nm Nb using electron beam lithography. (c) and (d) are SEM images of as grown MWCNTs arrays from (a) and (b) respectively. The scale bar corresponds to 1 μm.
area achieved by incorporating MWCNTs. The details of the enhanced mechanism can be found in our previous work [16]. However, from a cylindrical capacitance model [17,18] we can estimate the possible maximum capacitances of MICntM structures. If all parameters are as stated above, the capacitance of one single MICntM capacitor is 1.335 fF and therefore the capacitance by connecting 11100 MICntM capacitors in parallel (200 μm × 200 μm/0.36 μm2) is about 0.150 nF. In addition there is a flat surface area (=(200 μm × 200 μm) − (200 nm × 200 nm × 11100) = 35.56 × 10− 9 m2) and its capacitance from a planar capacitor model is 0.048 nF. Hence the total capacitance of MICntM structures can be as high as 0.198 nF. The experimental value shows a total capacitance of 0.184 nF, only an 8% reduction compared to the possible maximum. The leakage current density is about two orders of magnitude higher than in MIM structure, however, it is less than 5 μA/cm2 at 1 V. The increase in the leakage current is likely to be associated with non-uniform conformal dielectric deposition on MWCNTs.
4. Conclusions
Fig. 3. SEM images of MICntM capacitors arrays (a) at the bottom and (b) at the top. It shows decent step coverage with sputtered HfO2 and Al layers on MWCNTs. The scale bar corresponds to 1 μm.
The MICntM structures using HfO2 showed high capacitance. The compatibility of using high-k dielectric material and its deposition process with vertically aligned MWCNT arrays is demonstrated. It is important to note that the individual CNTs are properly spaced to accommodate the dielectric and metal layers. In order to achieve this, fine patterns of catalyst dots have been produced by electron beam lithography. The high aspect ratio of MWCNTs increase the effective electrode area and HfO2 allows higher permittivity, hence, higher capacitance structures are realized. The MICntM structure is a potential candidate to replace the Si pillar structures in nanoelectronic applications.
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Y. Choi et al. / Diamond & Related Materials 19 (2010) 221–224
References [1] B. Nagaraj, T. Sawhney, S. Perusse, S. Aggarwal, V.S. Kaushik, S. Zafar, R.E. Jones, J.-H. Lee, V. Balu, J. Lee, Appl. Phys. Lett. 74 (1999) 3194. [2] S.J. Lee, C.R. Cho, M.S. Kang, M.S. Jung, K.Y. Kang, Appl. Phys. Lett. 68 (1996) 764. [3] S. Iijima, Nature 354 (1991) 56. [4] A.M. Morales, C.M. Liber, Science 279 (1998) 208. [5] M. Tanase, L.A. Bauer, A. Hultgren, D.M. Silevitch, L. Sun, D.H. Reich, P.C. Searson, G.J. Meyer, Nano Lett. 1 (2001) 155. [6] K.B.K. Teo, S.-B. Lee, M. Chhowalla, V. Semet, V.T. Binh, O. Groening, M. Castignolles, A. Loiseau, G. Pirio, P. Legagneux, D. Pribat, D.G. Hasko, H. Ahmed, G.A.J. Amaratunga, W.I. Milne, Nanotechnology 14 (2003) 204. [7] M.J. Esplandiu, E.M. Patrito, V.A. Macagno, Electrochim. Acta 40 (1995) 809. [8] M.J. Esplandiu, E.M. Patrito, V.A. Macagno, Electrochim. Acta 42 (1997) 1315. [9] K. Kukli, J. Ihanus, M. Ritala, M. Leskela, Appl. Phys. Lett. 68 (1996) 3737. [10] Y. Tsou, F.C. Ho, Appl. Opt. 35 (1996) 5091. [11] K. Kita, K. Kyuno, A. Toriumi, Appl. Phys. Lett. 85 (2004) 54. [12] Y.-S. Suh, H. Lazar, B. Chen, J.-H. Lee, V. Misra, J. Electrochem. Soc. 152 (9) (2005) F138. [13] C. Bower, O. Zhou, W. Zhu, D.J. Wender, S. Jin, Appl. Phys. Lett. 77 (2000) 2767. [14] V.I. Merkulov, D.H. Lowndes, Y.Y. Wei, G. Eres, E. Voelkl, Appl. Phys. Lett. 76 (2000) 3555. [15] M. Chhowalla, K.B.K. Teo, C. Ducati, N.L. Rupesinghe, G.A.J. Amaratunga, A.C. Ferrai, D. Roy, J. Robertson, W.I. Milne, J. Appl. Phys. 90 (2000) 5308. [16] J.E. Jang, S.N. Cha, Y. Choi, D.J. Kang, D.G. Hasko, J.E. Jung, J.M. Kim, G.A.J. Amaratunga, Appl. Phys. Lett. 87 (2005) 263103. [17] R. Martel, T. Schmidt, H.R. Shea, T. Hertel, Ph. Avouris, Appl. Phys. Lett. 73 (1998) 2477. [18] H.T. Ng, J. Han, T. Yamada, P. Nguyen, Y.P. Chen, M. Meyyappan, Nano Lett. 4 (2004) 1247.
Fig. 4. (a) Capacitance-voltage (C-V) characteristics and (b) leakage current density of MICntM capacitors.
Acknowledgements This work was funded in part by support from Intel Corporation, USA.