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Cascadable digital counting logic using a bipolar gate array
168
Nuclear Instruments and Methods in Physics Research A267 (1988) 168-170 North-Holland, Amsterdam
CASCADABLE DIGITAL COUNTING LOGIC USING A BIPOLAR GATE ARRAY A. IMANISHI, H. OKUNO and K. UKAI
Institute for Nuclear Study, University of Tokyo, Tanashi, Tokyo 188, Japan
Received 21 September 1987 A fast digital counting logic using a bipolar gate array has been developed. The chip accepts eight digital inputs and provides binary outputs for the number of input hits. Three additional inputs are available for cascaded use of these chips. The signal delay per chip is measured to be 35 ns. of hit channels is counted in this chip and the resulting number of hit channels is provided by a 4-bit binary 1. Introduction code . For a cascaded use of these chips, three additional inputs, IC1, IC2 and IC4, are available, which are to be In high energy physics experiments it is often reconnected to the outputs of the previous stage, 01, 02 quired to count the number of hits in a scintillation and 04. counter hodoscope or proportional and drift chambers for triggering purposes . In the TOPAZ detector [1] at the TRISTAN e + e- collider, an inner drift chamber 3. Internal logic (IDC) and time of flight counters (TOF) are used as the triggering devices for charged particle tracks. In this A block diagram of the digital counting logic is case, the number of tracks or the number of hits which shown in fig. 2. The internal circuits are composed of a satisfy the predetermined topology should be counted combination of four types of unit cells (binary adders), very quickly. U20, U21, U22 and U30, which are shown in fig. 3 To meet this requirement, we have developed a fast together with their logic diagrams . Each circuit has an digital counting logic by using a bipolar gate array. For X-output and an UP-output for a cascade connection . the purpose of counting the number of hit channels an These unit cells are made as macrocircuits in a gate analog-sum method has been developed as a standard is array. electronic technique. When the number of inputs small and is fixed at certain channels, the above analog method is quite suitable because of its speed and reliability. INPUTS OUTPUTS However, when the number of channels is increased, ( BINARY ) the relative sensitivity of the analog circuit becomes critical . For example, the IDC has 64 sectors as track Il finding elements so that the relative counting accuracy I2 should be better than 1.6%. In addition, these analog 0e circuits are not flexible for the variation of the different 13 04 COUNTING number of input channels which is often encountered in 14 a large-scale complex detector system such as TOPAZ. LOGIC 02 Therefore, we have proceeded to develop a fast dig15 USING O1 ital counting method which has a modular architecture Is BIPOLAR suitable for various applications. In the present paper, we describe the basic logic, the 17 GATE performance of the chips and possible applications of I8 ARRAY this method. IC4 ( 102 cells ) 2. Principle
By keeping in mind the use of these chips in the IDC rz-track finder in large quantities [2], we decided to make a chip with eight input channels . The basic function of the resulting chip is shown in fig. 1. The number 0168-9002/88/$03 .50 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)
IC2
ici Fig.
1.
Digital counting logic.
A . Imanishi et al. / Cascadable digital counting logic
169
Os 13 14 04 15 16 02 17 I9 01
IC4 IC2
Ici
Fig. 2 . A block diagram of the logic in the gate array. (a)
LOGIC U20 A
e
L
L L
L
H H
II
UP
H
L L L
L L
H
LOGIC U21
(C) LOGIC U22
AN 22 LOGIC U30
Fig . 3 . Macro-logic in the gate array . (a) U20 2-Input adder, (b) U21 2-Input adder, (c) U22 2-input adder and (d) U30 3-Input adder.
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A . Imanishi et al. / Cascadable digital counting logic
9
16
17 24
25 32
33 40
41 48
49 56
57 64
Fig. 4. Cascaded use of the digital counting logic for 64 input channels. 4. Gate array We have used a bipolar gate array, since this has a higher gate speed compared to the popular CMOS gate array. The gate array used is MB111K (Fujitsu Co. Ltd) with 240 gates whose average delay time is 1 .9 ns per gate . Packaging is made in a DIP plastic package with 20 pins . The total number of gates used in this layout is 102, which is about half of the available gates of this array. In this array, I/O cells are provided to convert the TTL signal to the bipolar signal and vice versa. We have used fifteen I/O cells. 5. Performance The characteristics of this chip are shown in table 1 . The delay time of the signal varies depending on the signal path in the gate array in the range from 20 to 35 ns . For a fine timing application, some timing synchronization would be necessary. In the IDC rz-track finder, 288 chips in total are used for triggering purposes . In this case, a single chip is used for counting the hit number out of eight input Table 1 Characteristics of the digital counting logic using the bipolar gate array Inputs Outputs Total number of cells Propagation delay Power consumption
8 channels +3 for cascaded use 4-bit binary 102 20-35 ns 113 mW
channels. The system has successfully worked in the actual colliding beam experiment at TRISTAN. For the application in cascaded use, a typical arrangement is shown in fig. 4, where the number of hit channels is counted out of 64 input channels. In this case, nine identical chips are used in a cascaded manner . In this arrangement, the total decision time is about 300 ns . When this delay is not acceptable, a much faster arrangement would be possible . 6. Conclusions We have developed a fast digital counting logic using a bipolar gate array. This chip is able to determine the number of hit inputs out of eight inputs within 35 ns . By cascading these chips, counting a large number of channels becomes possible within a reasonable resolving time . Acknowledgements We sincerely thank all members of the TOPAZ collaboration, especially those of the IDC group of the Institute for Nuclear Study, for continuous discussions . We also thank Fujitsu Co . Ltd for realizing the logic in the gate array. References [1] TOPAZ Collaboration, A proposal for TRISTAN, TRISTAN-EXP-002, KEK (1983) . [21 K. Shiino et al ., Institute for Nuclear Study, University of Tokyo, INS-T-476 (1987) in Japanese .
Nuclear Instruments and Methods in Physics Research A267 (1988) 168-170 North-Holland, Amsterdam
CASCADABLE DIGITAL COUNTING LOGIC USING A BIPOLAR GATE ARRAY A. IMANISHI, H. OKUNO and K. UKAI
Institute for Nuclear Study, University of Tokyo, Tanashi, Tokyo 188, Japan
Received 21 September 1987 A fast digital counting logic using a bipolar gate array has been developed. The chip accepts eight digital inputs and provides binary outputs for the number of input hits. Three additional inputs are available for cascaded use of these chips. The signal delay per chip is measured to be 35 ns. of hit channels is counted in this chip and the resulting number of hit channels is provided by a 4-bit binary 1. Introduction code . For a cascaded use of these chips, three additional inputs, IC1, IC2 and IC4, are available, which are to be In high energy physics experiments it is often reconnected to the outputs of the previous stage, 01, 02 quired to count the number of hits in a scintillation and 04. counter hodoscope or proportional and drift chambers for triggering purposes . In the TOPAZ detector [1] at the TRISTAN e + e- collider, an inner drift chamber 3. Internal logic (IDC) and time of flight counters (TOF) are used as the triggering devices for charged particle tracks. In this A block diagram of the digital counting logic is case, the number of tracks or the number of hits which shown in fig. 2. The internal circuits are composed of a satisfy the predetermined topology should be counted combination of four types of unit cells (binary adders), very quickly. U20, U21, U22 and U30, which are shown in fig. 3 To meet this requirement, we have developed a fast together with their logic diagrams . Each circuit has an digital counting logic by using a bipolar gate array. For X-output and an UP-output for a cascade connection . the purpose of counting the number of hit channels an These unit cells are made as macrocircuits in a gate analog-sum method has been developed as a standard is array. electronic technique. When the number of inputs small and is fixed at certain channels, the above analog method is quite suitable because of its speed and reliability. INPUTS OUTPUTS However, when the number of channels is increased, ( BINARY ) the relative sensitivity of the analog circuit becomes critical . For example, the IDC has 64 sectors as track Il finding elements so that the relative counting accuracy I2 should be better than 1.6%. In addition, these analog 0e circuits are not flexible for the variation of the different 13 04 COUNTING number of input channels which is often encountered in 14 a large-scale complex detector system such as TOPAZ. LOGIC 02 Therefore, we have proceeded to develop a fast dig15 USING O1 ital counting method which has a modular architecture Is BIPOLAR suitable for various applications. In the present paper, we describe the basic logic, the 17 GATE performance of the chips and possible applications of I8 ARRAY this method. IC4 ( 102 cells ) 2. Principle
By keeping in mind the use of these chips in the IDC rz-track finder in large quantities [2], we decided to make a chip with eight input channels . The basic function of the resulting chip is shown in fig. 1. The number 0168-9002/88/$03 .50 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)
IC2
ici Fig.
1.
Digital counting logic.
A . Imanishi et al. / Cascadable digital counting logic
169
Os 13 14 04 15 16 02 17 I9 01
IC4 IC2
Ici
Fig. 2 . A block diagram of the logic in the gate array. (a)
LOGIC U20 A
e
L
L L
L
H H
II
UP
H
L L L
L L
H
LOGIC U21
(C) LOGIC U22
AN 22 LOGIC U30
Fig . 3 . Macro-logic in the gate array . (a) U20 2-Input adder, (b) U21 2-Input adder, (c) U22 2-input adder and (d) U30 3-Input adder.
170
A . Imanishi et al. / Cascadable digital counting logic
9
16
17 24
25 32
33 40
41 48
49 56
57 64
Fig. 4. Cascaded use of the digital counting logic for 64 input channels. 4. Gate array We have used a bipolar gate array, since this has a higher gate speed compared to the popular CMOS gate array. The gate array used is MB111K (Fujitsu Co. Ltd) with 240 gates whose average delay time is 1 .9 ns per gate . Packaging is made in a DIP plastic package with 20 pins . The total number of gates used in this layout is 102, which is about half of the available gates of this array. In this array, I/O cells are provided to convert the TTL signal to the bipolar signal and vice versa. We have used fifteen I/O cells. 5. Performance The characteristics of this chip are shown in table 1 . The delay time of the signal varies depending on the signal path in the gate array in the range from 20 to 35 ns . For a fine timing application, some timing synchronization would be necessary. In the IDC rz-track finder, 288 chips in total are used for triggering purposes . In this case, a single chip is used for counting the hit number out of eight input Table 1 Characteristics of the digital counting logic using the bipolar gate array Inputs Outputs Total number of cells Propagation delay Power consumption
8 channels +3 for cascaded use 4-bit binary 102 20-35 ns 113 mW
channels. The system has successfully worked in the actual colliding beam experiment at TRISTAN. For the application in cascaded use, a typical arrangement is shown in fig. 4, where the number of hit channels is counted out of 64 input channels. In this case, nine identical chips are used in a cascaded manner . In this arrangement, the total decision time is about 300 ns . When this delay is not acceptable, a much faster arrangement would be possible . 6. Conclusions We have developed a fast digital counting logic using a bipolar gate array. This chip is able to determine the number of hit inputs out of eight inputs within 35 ns . By cascading these chips, counting a large number of channels becomes possible within a reasonable resolving time . Acknowledgements We sincerely thank all members of the TOPAZ collaboration, especially those of the IDC group of the Institute for Nuclear Study, for continuous discussions . We also thank Fujitsu Co . Ltd for realizing the logic in the gate array. References [1] TOPAZ Collaboration, A proposal for TRISTAN, TRISTAN-EXP-002, KEK (1983) . [21 K. Shiino et al ., Institute for Nuclear Study, University of Tokyo, INS-T-476 (1987) in Japanese .