Chapter 2 Ion Implantation and Materials for GaAs Integrated Circuits

SEMICONDUCTORS AND SEMIMETAU, VOL. 20

CHAPTER 2

Ion Implantation and Materials for GaAs Integrated Circuits C.A . Stolte NEWLETT-PACKARD LABORATORIES P A L 0 ALTO, CALIFORNIA

LISTOF ACRONYMS.. . . . . . . . . . . . . . . . I. INTRODUCTION .................... 11. MATERIALS PREPARATION. ............. 1. Semi-Insulating GaAs Ingot Growth . . . . . . . .

..

.. .. 2. Epitaxial BufferLayer Growth . . . . . . . . . . . . 3. Thermal Stability. . . . . . . . . . . . . . . . . .

111. ION IMPLANTATION ........ 4. Introduction . . . . . . . . . . .

.......... ......... 5 . Ion-Implant Conditions . . . . . . . . . . . . . . . 6 . Anneal Conditions . . . . . . . . . . . . . . . . . I . Substrate Influence . . . . . . . . . . . . . . . . .

8. High-Dose Implants. . . . . . . IV. DEVICE RESULTS.. . . . . . . . . 9. IC Fabrication . . . . . . . . . 10. IC Performance. . . . . . . . . I I . Backgating . . . . . . . . . . . V. SUMMARY.. . . . . . . . . . . . . REFERENCES. . . . . . . . . . . .

.......... .......... . . . . . . . . . . . . . . . . . . . . ......... ......... .........

89 90 93 93 103 106 109 109 111 119

125

134 143 143 146 148 151 154

List of Acronyms AES ASES BFL

c- v

CVD DLTS ECL FET IC

JFET LEC

Auger emission spectroscopy Arc source emission spectroscopy Buffered FET logic Capacitance- voltage Chemical vapor deposition Deep-level transient spectroscopy Emitter coupled logic Field effect transistor Integrated circuit

LPE LSI MBE MESFET MSI OMVPE

89

Junction field effect transistor Liquid-encapsulated Czochralski Liquid-phase epitaxy Large-scale integration Molecular beam epitaxy Metal-semiconductor field effect transistor Medium-scale integration Organo-metallic vapor-phase epitaxy

Copyright 0 1984 by Academic Press. Inc. All rights of reproduction in any form reserved. ISBN 0- 12-752 120-8

90 PBN PRBS

RBS

SDFL

C. A. STOLTE

Pyrolytic boron nitride Pseudorandom-bit-sequence generator Rutherford backscattering Schottky diode FET logic

SIMS

SSMS VLSI VPE

Secondary ion mass spectroscopy Spark source mass spectroscopy Very large-scale integration Vapor-phase epitaxy

I. Introduction The materials and implantation procedures used to produce high-quality regions for the fabrication of GaAsintegrated circuits (ICs) will be discussed in this chapter. The present state of the art in the preparation of materials, the ion implantation technology, the device processing procedures, the circuit design, and the evaluation of GaAs ICs has yielded circuits of the complexity of that shown in Fig. 1 (Liechti el al., 1982a).This circuit, which was designed, fabricated, and tested at the Hewlett-Packard Laboratories, is a 5-Gbit/sec data rate word generator that contains 400 transistors and 230 diodes on a 1.1 - by 1A-mm chip. The topics covered in this chapter are many-faceted. Therefore, specific topics considered important by some may not be addressed. The main experimental results included here are representative of the work of the author and his colleagues at Hewlett-Packard since 1975. Appropriate references are made to the literature to complement the information presented here with the results obtained in other laboratories. The intent of this chapter is to cover ( I ) the important aspects of the selection and characterization of the substrate materials that serve as the basis for all the work, including the investigation of ion implantation and the fabrication of ICs, and (2) the procedures used to produce the doped, active regions in the substrate material required to form the channel regions of MESFETs, the ohmic contact areas, and other active regions necessary for the production of ICS.

In Part 11, the important aspects of the growth, properties, characterization, and thermal stability of substrate materials are' presented. The basic requirement for the substrate material is that it provide electrical isolation between devices while at the same time allowing the formation of high-mobility controlled-doping regions in the areas where devices are to be fabricated. This requirement is met in most applications by selective region ion implantation into bulk substrate material of sufficientquality or by selective region ion implantation into high-purity epitaxial layers produced by liquid-phase epitaxy (LPE) or vapor-phase epitaxy (VPE). These active regions

FIG. 1. Photomicrograph of the 5-Gbit/sec GaAs MSI word generator. The chip measures 1.1 X 1.6 mm and contains over 600 active components and 32 contact pads.

92

C. A. STOLTE

can also be formed by the production of n-type layers by epitaxy combined with an alternative isolation technique such as mesa etching, proton bombardment, or oxygen ion implants. The use of epitaxial techniques for the active regions is, in general, limited to the production of discrete devices due to the nonuniformity of the layer thickness. The techniques used to produce Cr-doped and undoped semi-insulating GaAs ingots will be discussed, with emphasis on the 2-atm liquid-encapsulated Czochralski (LEC) technique used at Hewlett-Packard.The properties of substrate materials and the compensation mechanisms responsible for the high resistivity are presented. The thermal stability of these materials and the generally accepted model for the thermal conversion are reviewed. The growth and properties of high-purity epitaxial layers grown on semi-insulating substrates are discussed. The formation of electrically active regions by ion implantation is discussed in Part 111. Recent review articles by Donnelly (1977) and Eisen (1980) present background material on ion implantation, including numerous references to the literature. In this chapter, only the procedures used for the formation of n-Iayers, for the active regions of MESFETs and diodes, and for the formation of n+ regions for the ohmic contact regions of the circuits will be discussed. The discussion will be limited to the conditions necessary to produce normally on depletion mode MESFETs and will not address the production of normally off enhancement mode FETs. For a discussion of the relative merits of depletion mode versus enhancement mode devices and extensive references to the literature, see Liechti ( 1976), Bosch ( 1979), and Lehovec and Zuleeg ( 1980). Descriptions of the fabrication and characteristics of ion-implanted, normally OR,junction FET ICs are given in Zuleeg et al. (1 978), Kasahara et al. (198 l), and Troeger et al. (1979). Recent developments in MBE growth of GaAs-AlGaAs heterojunctions have led to the development of advanced devices with higher speed capabilities. The high mobility, modulation-doped FET (Mimura et al., 1980; Tsui et al., 1981; Judaprawira et al., 1981; Tung et at., 1982; DiLorenzo et al., 1982; Drummond et al., 1982) has been developed and is being integrated (Abe et al., 1982) for high-speed applications. The heterojunction bipolar GaAs-AlGaAs transistor (Asbeck et al., 1982; Su et al., 1983) is another candidate for high-speed integrated circuits. These devices are now being incorporated in integrated circuits in many laboratories and will have an impact on future GaAs integrated circuits. A discussion of these devices and their fabrication is beyond the scope of this chapter. The discussions of the material characteristics and requirements presented below do, however, apply to these devices.

2.

ION IMPLANTATION AND MATERIALS

93

The conditions of ion implantation discussed include the choice of the ion species, the temperature during implantation, the orientation of the substrate during implantation, and the use of through-dielectric-layerimplantation. The effect of these conditions on the resulting properties of the layers is presented in a systematic way to indicate the importance of each. The conditions required to anneal the damage produced by implantation and to electrically activate the implanted species are discussed. The anneal conditions include the techniques used to protect the surface of the substrate during the high-temperature anneal by the use of dielectric caps as well as by capless anneal techniques. The influence of the time and temperature of the anneal on the electrical properties of the implanted layers are presented. The application of transient annealing, using electron beams or laser beams, for the production of n+ regions with sufficiently high-doping concentration to produce ohmic contacts with nonalloyed metals is presented and its use for ICs is discussed. The influence of the substrate materials on the electrical properties of the implanted and annealed regions, as well as the characteristics of the devices fabricated in these layers, will be discussed. In Part IV of this chapter, the production of medium-scale integration (MSI) GaAs ICs is discussed, with emphasis on the influence of the implantation conditions, the anneal conditions, and most importantly, the influence of the starting substrate material on the properties of the devices and circuits. In particular, the phenomenon of backgating is discussed, and the influence of the substrate material on the magnitude of this effect is documented. Finally, in Part V, the state of the art is summarized and the necessary improvements in materials, ion implantation, and processing to advance GaAs IC technology are discussed.

11. Materials Preparation

1. SEMI-INSULATING GAASINGOTGROWTH

The material used as the substrate for the fabrication of GaAs ICs falls into two general classes. The first is bulk semi-insulating material grown by the LEC, gradient-freeze, or Bridgman techniques. The review article by Lindquist and Ford (1982) contains an extensive list of references as well as a summary of the growth and characterization of semi-insulating GaAs. The compensation mechanisms responsible for the semi-insulating behavior of

94

C . A. STOLTE

GaAs are discussed by Martin et al. (1980) and Johnson et al. (1983). The second class is a high-purity epitaxial buffer layer grown on the bulk substrate material by LPE, VPE, or molecular beam epitaxy (MBE). Both types of material produce satisfactory results, as will be discussed below. The production of semi-insulatingGaAs by the horizontal Bridgman and gradient-freeze techniques is well documented in the literature (Mullin, 1975). In the horizontal techniques, GaAs is synthesized in an evacuated tube by the vapor transport of As from an elemental source to Ga contained in a quartz boat. The As is held at a temperature of 607°C to produce a 1-atm As pressure, and the Ga is held at 1238°C. The stoichiometry of the resulting GaAs melt is controlled by the relative amounts of As and Ga loaded into the tube and by the temperature of the components in the system. The crystal growth is initiated by producing a temperature gradient to cool the GaAs melt such that the freezing interface travels along the length of the boat. With the Bridgman technique, the moving interface is produced by moving the boat with respect to the furnace. In the gradient-freeze technique, the freezing interface is produced by lowering the temperature profile. The main advantage of these techniques is that the ingots produced have appropriately a factor of 10 lower dislocation density as compared to those grown by the LEC technique. The main disadvantage is that the ingots are the shape of the boat and are smaller than the cylindrical, large-diameter ingots pulled using the LEC technique. Recent work (Lagowski et al., 1982; Kaminska et al., 1982) has produced material with improved electrical properties using the Bridgman technique. The production of GaAs ingots by the LEC technique was developed by Mullin et al. (1968) using the techniques demonstrated by Metz et al. ( 1962). The use of the LEC technique to produce high-quality material has received increased emphasis in many laboratoriesin the last few years. Most laboratories use a high-pressure LEC puller (AuCoin et al., 1979); results obtained using this material are reported in other chapters of this book (Kirkpatrick et al., Chapter 3 ; Thomas et al., Chapter 1). The commercial high-pressure (30 atm) LEC technique was developed by the Royal Radar and Signals Establishment and put into commercial use by Metals Research Ltd., Cambridge, England, which supplies bulk-grown LEC material as well as marketing the high-pressure pullers-the Malvern puller for 2-in.-diam ingots and the Melbourn puller for 3-in.-diam ingots. Several companies, including Rockwell International, Westinghouse, Hughes, and Microwave Associates, have purchased the Melbourn puller for their in-house production of semi-insulating GaAs. The characteristics of this material and the results obtained using it as substrate material will be presented below as part of a comparison of the different materials available for use in ICs. Recent investigations at Laboratoires d’Electronique et de Physique Appliqu6e in

2.

ION IMPLANTATION A N D MATERIALS

95

France (Jacob et al., 1980)have compared the gradient-freeze grown material with the high-pressure LEC-grown material. The technique we have used (Ford and Larsen, 1975) for the production of semi-insulating GaAs ingots since 1974 is the low-pressure, 2-atm LEC procedure. This technique has been used to produce standard Cr-doped (Cronin and Haisty, 1964),semi-insulating substrates. This material is used as the substrate material for epitaxial growth of the n-type layers used to fabricate discrete FETs as well as for the substrate material used for the growth of high-purity buffer layers, which is the starting material for the formation of n-type layers by ion implantation. Since 1978, this technique has also been used to produce nonintentionally doped, high-purity, semi-insulatingGaAs ingots suitable for use as substratesfor epitaxial growth as well as for the production of n-type regions by direct ion implantation into the bulk substrate material. A cutaway view of the LEC puller employed for the 2-atm technique is shown in Fig. 2. The apparatus consists of a resistively heated crucible, either quartz or pyrolytic boron nitride (PBN), which holds the GaAs melt. The GaAs starting material is either compounded externally to the puller in a standard quartz ampoule by a standard As vapor transport technique (Mullin, 1975) or by the injection of As into the Ga melt (Pekarek, 1970),as will be discussed below. These methods for the synthesis of GaAs eliminate the need for the high-pressure LEC pullers. The appropriate dopants, if any, are added and the melt is covered with a layer of boric +SEED GATE VALVE

ROD GaAs SEED

CRUCIBLE

Bzo3 (L) GsAr (L) PEDESTAL

FIG.2. Schematic diagram ofthe 2-atm LEC puller. The gate valve is used to isolate the melt while the seed crystal or the injection cell is attached to the seed rod.

96

C. A. STOLTE

oxide (B203)which acts.as a protective encapsulant to eliminate the loss of the volatile constituentsat the growth temperature of 1238°Cand to isolate the melt from the crucible. The GaAs crystal is pulled by inserting a seed of the proper orientation to the surface of the melt, which is held at 1238"C, and extracting it at a controlled rate while the seed and the melt are rotated in opposite directions. By careful and judicious control of the rotation rates and the pull rate, ingots with good crystallographic properties and reasonably controlled diameters are produced using this technique. The melt charge is typically 2 kg, which produces ingots of approximately 65 mm in diameter and 100 mm in length. The ingot can be pulled in either the [ 11 11 or the [ 1001direction; in the past, the majority of the ingots were grown in the [ 1 1 11 direction. In the case of the [ 1 1 11ingots, the (100)oriented wafers used for device fabrication are cut from the ingot and the typical D-shaped wafer is produced. The control of background impurities in the crystals is of utmost importance, independent of the type of crystal being pulled. In the case of undoped high-purity ingots, this need is obvious. In the production of Cr-doped ingots, it is just as important since the Cr added to compensate the background shallow donor diffuses during the required anneal procedures following implantation (Evans et d., 1979). This diffusion can lead to inconsistencies since the decrease in the Cr concentration reduces the degree of compensation, and layers with inferior electrical properties are obtained, as discussed below. A novel and proven technique for in situ synthesis of the GaAs in the 2-atm LEC puller has been refined and is used to produce substrate material for our use (Puttbach et al., 1981).The apparatus used for this technique is shown in Fig. 3. In this procedure, the Ga and dopant species are loaded in the crucible, which can be either quartz or PBN, and the B203encapsulantis placed over the melt. The furnace is heated and the Ga melt brought to the growth temperature, during which time the B203encapsulatesthe melt. The injection cell, either quartz or PBN, is lowered to position the injection stem through the B,03 into the Ga melt. Arsenic is injected into the melt by a vapor-transport process driven by the controlled temperature of the As injection cell. After the As has been incorporated in the melt, the injection cell is extracted through an air lock and the seed crystal, mounted on the control rod, inserted into the melt in the usual manner. The advantage of this system is that the melt is compounded in situ, eliminating the need for external synthesis and the potential of impurity incorporationin the melt. In addition, if all the parts, including the injection cell and the crucible, are fabricated from PBN, the contamination by Si from the quartz parts is eliminated. In practice, the use of PBN is not necessary; high-purity crystals have been grown in all quartz systems, as documented

97

HE!

! HIELO

.L

FIG. 3. Schematic diagram of the LEC puller showing the A injector cell used fa the synthesis of GaAs.

below. The crucial conditions required to produce high-quality semi-insulating GaAs by these techniques include the use of very high-purity starting material, at least six 9s. A recent investigation by Oliver et al. ( 198 1 ) ha\ demonstrated the role of H,O in the BZO3encapsulant, which acts as a gettel for Si. For their growth conditions, in a quartz crucible, an HzO content ot approximately 1000 ppm was necessary to reduce the Si concentration and obtain semi-insulating GaAs. The importance of the control of the As/Ch ratio during the growth of non-Cr-doped semi-insulating ingots has been demonstrated by Holmes ( 1982). The LEC technique has historically produced ingots with higher disloca tion densities than the Blidgman or gradient-freeze technique. The densit ICY are in the 1 X lo4- 1 X lo5cm-2 range, depending on the dopant concc'n tration and manufacturer. The paper by Holmes et al. (1983) presentj experimental distributions of the dislocation densities, and the EL2 l e (4~

98

C. A. STOLTE

concentration, observed in a high-purity semi-insulatingwafer grown using the high-pressure LEC technique. Early results by Grabmaier and Grabmaier ( 1972)indicated that low dislocation material could be pulled by the LEC techniques by a necking-in procedure. The ingots pulled, however, were small in diameter (< 15 mm). Recent work in our laboratories (Hiskes et al., 1982) has produced large-diameter, 65-mm, LEC material with dislocation densities under 200 cm-2 over 80% of a wafer cut from the tail region of the ingot for Si-doped material. The typical dislocation density for semi-insulatingmaterial is in the low 1 X 104-cm-2range with regions in the 1 X 103-cm-2range near the axis of the ingot. The importance of dislocation density on the quality or yield of high-density GaAs ICs has not been demonstrated but could be expected to become important as the area of critical regions of the circuit, e.g., the gate regions, occupy a significant fraction of the chip area. The 2-atm LEC technique has routinely produced high-quality Cr-doped semi-insulating GaAs since 1974. The necessary conditions for the production of high resistivity material is that the dopants satisfy the following relations: if ND> NA,then NDA - NDD > (ND- NA) (Lindquist, 1977)

(four-level model)

or (three-level model) if NA > ND, then NDD > ( N A - ND) (Swiggard et al., 1979), where NsDand NSAare the concentration of shallow donors and acceptors, respectively, and NDDand NDA are the concentration of deep donors and acceptors, respectively. The energy levels of these dopants, shown in Fig. 4, have been measured by many laboratories. See the recent paper by Martin (1 980) for an overview of these results. The shallow donors are believed to be due to S and Si as unintentional dopants or to Te as an intentional dopant used to prevent ptype conversion of the Cr-doped material when it is used as a substrate for epitaxial growth (Swiggard et al., 1979). The addition of Te for this purpose is no longer necessary with the improved purity of the growth conditions possible today. The shallow acceptors are believed to be due to C, Mn, or other impurities in the melt. The deep acceptors are due to the Cr intentionally added to the melt to compensate the shallow donors in order to assure semi-insulating material with resistivitiesgreater than 1 X lo* R cm. The deep donor, the EL2 level, was originally ascribed to oxygen (Milnes, 1973); however, Huber et al. (1979) demonstrated that the EL2 level is not due to oxygen. It is believed

2.

ION IMPLANTATION A N D MATERIALS

99

Cr" ? A'

1.43 eV

C.B.

ND

o,9 eV

Cr" ? A '

E,,

N m 0 . 7 eV 0.62 eV 0.45 eV

0.15 eV

CrZf

EL (')

AEF

&

0.7 eV N,

Cr3* A'

cr4+

D+ NA

-

= 0.825

V.B.

FIG.4. Electron energy diagram of semi-insulating GaAs showing the shallow ND and NA levels and the deep traps, Crz+and EL2, along with the charge state of Cr in GaAs.

that the EL2 level is due to a native defect, As on a Ga site, formed during the post-growth cooling of the crystals (Lagowski et al., 1982a). Recent results by Holmes et al. (1982) demonstrated that the EL2 concentration is related to the stoichiometry of the LEC melt and therefore can be controlled to some degree. The growth of nonintentionally doped ingots which are semi-insulating and thermally stable has been a production process since 1978. Because there is no Cr added to the melt, the semi-insulatingproperty of this material is described by the three-level model. It is essential to minimize the concentration of the shallow donors and to control the concentration of the shallow acceptors relative to the concentration of the deep donor level EL2. This control can be maintained, as was demonstrated by our consistent results obtained over a three-year period. An indication of the practicality of the production of this high-purity bulk material is the routine operation of a second facility of Hewlett-Packard (the Santa Rosa Technology Center), which has successfully constructed a 2-atm LEC puller and is pulling high-purity semi-insulating GaAs ingots. In addition, as indicated above, several companies have installed the Melbourn puller manufactured by Metals Research, and they are successfully growing high-purity semi-insulating material. The quantitative determination of impurities in GaAs substrate material is a difficult problem and it is not difficult to obtain erroneous results. The techniques used for impurity analysis include secondary ion mass spectros-

100

C . A. STOLTE

copy (SIMS) (Clegg, 1982), Auger emission spectroscopy (AES) (Holloway, 1980),spark source mass spectroscopy (SSMS)(Brown el al., 1962), and arc source emission spectroscopy (ASES) (Wang, 1968). The use of AES is limited due to the lack of sensitivity. ASES has been successfully used in these investigations for the determination of impurities such as Cr, with a detection limit of 1 X 1015~ m - Si, ~ ;with a detection limit of 1 X 1015~ m - ~ ; and Mg, with a detection limit of 4 X loL5~ m - ~ SIMS . analysis has been used by many laboratories to evaluate the redistribution of Cr and to measure the background impurity concentration. In this application, extreme care must be taken in the interpretation of results due to matrix and background effects. The most sensitive technique for the analysis of impurities is SSMS. This technique requires precise preparation and use of calibration sources and careful operation of the apparatus to avoid instrumental background levels which can lead to erroneous results. The data presented in Table I were obtained by SSMS at three different facilities from samples taken from the same regions of two different high-purity semi-insulating ingots grown in our facilities. For comparison purposes, results obtained using ASES in these laboratories are included. There are large discrepancies in the magnitudes of the impurities measured by the three different SSMS facilities for important species such as Cr, Si, S, and 0.The most consistent and reliable results, and those which are in agreement with the measured electrical behavior, thermal stability, and implant and anneal resuIts, are those obtained by facility A. It is interesting to note that although emission spectroscopy lacks sensitivity, it is in agreement with the SSMS analysis of facility A. The data in Table I1 were obtained by SSMS in facility A for a number of different samples from different ingots produced by the 2-atm LEC technique at Hewlett-Packard, F402 and F450, and by the high-pressure Melbourn puller at Metals Research using in situ synthesis. Using the three-level model described above, and assuming that C is the dominant shallow acceptor (Brozel et al., 1978) and that Si and S are the dominant shallow donors, the concentration of the EL2 level to produce semi-insulating material can be calculated. From the impurity analysis given in Table 11, it is seen that these materials will be semi-insulating if an EL2 level concentration of about 4 X 10l6cm-3 is assumed for the LEC materials. This is the concentration of the EL2 level that is quoted in the literature for materials grown by this technique (Martin, 1980). The properties of these bulk materials, both the Cr-doped and the nonintentionally doped, high-purity semi-insulating materials, are discussed in detail in the sections that follow and are compared with the properties of bulk material from other sources and grown by other techniques. In addition, the properties of these bulk materials will be compared with the properties obtained using very high-purity buffer layers.

TABLE I SPECTROGRAPHIC ANALYSIS OF HIGH-PURITY BULKG a s

Ingot HP F402 Element

B C N 0 Na Mg A1

Si S Ca Cr Mn Fe cu Zn Te

ASES hp labs (cm-%)

SSMS facility A (~rn-~) 6.6 X

IOl5

18.9 x 1015 53.1 X 10l6

=

4.0 x 1014 < 1.2 x 1015 < i . i x 1015 <8.0 x 10'5 a . 2 x 1014

< 1.7 x 1015 1.5 x 1014 ~3.x 8 1017

1.1 x 1016 <2.2 x 1015 <3.5 x 1014 3.1 x 1014 8.9 x 1014 a . 7 x 1014 2.2 x 1015 <3.5 x 1014 a . 7 x 1014 <3.i x 1014 <4.4 x 1014 <6.6 X IOl4

a . 9x

1014

Ingot HP F450

SSMS facility B (~rn-~) 4.0 X lo1* 1.3 x 1017 4.0 X 10l8

1.3 X 10l6 2.7 x 1015

1.3 X lot6 1.3 X 10I6 4.4 X loL5 8.9 x 1015 8.9 x 10'4 1.3 x 1015 <4.4 x 1014

<8.9 X < 1.3 x

IOI4

1015

SSMS facility C (cm-3) 1.3x

1015

SSMS facility A (~rn-~) 4.4 x 1015 51.5 X loi6

a . 1 x

<4.4 x 1015 1.3 X <4.4 X 10l6 < 1.3 X lot6

1.3 x 1015 <4.4 x 1014 <4.4 x 1015

< 1.8 x 1015

1015

SSMS facility B (~rn-~) 4.4 x 4.0 x 4.0 X 1.3 x 2.2 x

1015

1017 loL6

5 1.5 X ~ 4 .x 4 7.9 x 2.6 x 1.3 X

1014

~3.x 1

1014

2.2 x 1015 4.4 x 1015

1014

1014

10l6 1014

1014 loB5 8.8 X loi4 1 . 1 x 1015 a . 6 x 1014 <2.2 x 1014 <2.2 x 10'4 <4.4 x a.2x

1014

10'8 10'6

1.8 x 1015 8.9 x 1015

1.3 X 10l6 4.4 x 1015 4.4 x 1015 2.2 x 1015

8.9 x

TABLE I1

SSMS ANALYSIS OF HIGH-PURITY G A SINWTS HP F450 Element

B C N 0 Na Mg

Al Si

S ca

Cr Mn Fe cu Zn

Te

MR-A (SiO, cruc.) (cm-)) 6.6 X lOI5

54.4 x 10’6 53.1 X 10”

59.7 x 10”

c 1.3 x 1015 4.4 x

1014

1.3 x 1014 4.4 x 1015 4.4 x 1015 4.4 x 10’6 < 1.3 x 1014 ~ 8 . x9 1013 1.3 x 1014 < 1.8 x 1014 <4.4 x 1014 <3.5 x 1014

MR-B (PBN cruc.)

MRC

(Cm-))

(m-?

x 1015 x 10’6 x 10’6 x 10” ~ 8 .x 9 1014 3.5 x 1014 < 1.8 x 1014

1.3 x 1015 1.1 x 1015 55.5 x 1015 53.1 x 1017 <6.6 X lof4 1.3 x 1015 1.8 x 1014 4.4 x 1014 2.2 x 1015 3.1 x 1015 <2.2 x 1014 < 1.8 X IOl4 <2.2 x 1014 ~ 2 .x 7 1014 <4.4 x 1014 <4.4 x 1014

4.4 54.4 54.4 54.4

3.1 X lo1‘ 6.6 X 10l5 1.3 X lot6 ~ 2 .x 2 1014 < 1.8 x 1014 ~ 2 .x 2 1014 a . 7 x 1014 6.6 X 1014 <4.4 x 1014

5

HP F402 (m-’) 6.6 X 58.9 x 53.1 X 5 1.1 x <2.2 x <3.5 x

Head

Tail

(m-’)

1015 4.4 x 1015 1015 5 1.5 X 10I6 1016 53.1 x 1015 10’6 5 1.5 X 10I6 10” <4.4 x 1014 1014 7.9 x 1014 a . 1 x 1014 2.6 x 1014 8.9 x 1014 1.3 x 1015 e . 7 x 1014 8.8 X 1014 2.2 x 1015 1.1 x 1015 <3.5 x 1014 ~ 2 . x 6 1014 a . 7 x 1014 <2.2 x 1014 a . 1 x 10’4 ~ 2 . x 2 1014 ~ 4 .x 4 1014 a . 1 x 1014 <6.6 X lot4 ~ 4 . x 4 1014 a . 9 x 1014 a . 2 x 1014

(cm-’) 2.2 x 1015 1.5 X 10l6 53.1 x 1015 54.4 x 10’6 ~ 4 .x 4 1014 6.2 x 1014 <2.2 x 1014 3.5 x 1014 2.2 x 1015 6.6 X lOI4 ~ 2 .x 6 1014 <2.2 x 1014 3.5 x 1014 ~ 3 .x 5 1014 3.1 x 1015 <6.6 X loL4 5

2.

103

ION IMPLANTATION A N D MATERIALS

2. EPITAXIAL BUFFERLAYERGROWTH The growth of high-purity epitaxial layers has been accomplished by VPE [using the AsCl, system, the ASH, system, and the organometallic vaporphase epitaxy (OMVPE)] by LPE, and by molecular beam epitaxy (MBE). These growth techniquesare discussed,with emphasison the LPE technique used in our investigations. A recent paper by Abrokwah d al. (1981) lists numerous references to literature describing techniques used to grow LPE layers. In that paper, procedures are described to obtain high-purity buffer layers by LPE. The technique requires prolonged (24 - 96 hr), high-temperature(775 "C)baking of the melt and substrate prior to the growth at 700°C. The results of Morkoc and Eastman ( 1 976) indicate that a prebake of the graphite boat at a high temperature, greater than the 700°Cgrowth temperature, in H, before growth is necessary for the growth of low camer concentration layers, These high-temperaturetreatments are not used in the procedures described below for the production of high-purity buffer layers. The growth of high-purity GaAs buffer layers by the LPE technique in these laboratories has provided consistently high-quality substrates for the investigation of ion implantation and for the production of GaAs ICs. This LPE material has been the standard against which the properties ofimplants into other materials have been compared. The growth of these materials has been routine since 1974 using the techniques of sample preparation determined by Vilms and Garrett (1972). Layers with consistent properties have been available for our investigationssince 1975 (Stolte, 1975). The layers are produced using the system illustrated schematically in Fig. 5, which shows the horizontal graphite slider system. The Ga, six 9s (0.999999) purity, is loaded in the slidinggraphitebin to a depth of about 5 mm. The source of As HIGH-PURITY GaAs WAFER

PUSH ROO

/

M A I N BLOCK

I

(1UARTZ THERMOCOUPLE SHIELD

FIG.5 . Schematic diagram of the horizontal graphite slider system used to grow high-purity liquid-phase epitaxial GaAs buffer layers.

104

C. A. STOLTE

is a 500-pm-thick,high-purity GaAs wafer placed on top of the Ga melt, as shown. The source wafer is the high-purity material pulled by the LEC process described earlier. The Ga melt, with the source wafer in place, is inserted into the reactor and baked for four to five days at a temperature of 700°C under a hydrogen flow of 4 liter/sec. The substrate used for the growth is prepared using a chemical-mechanical polish with bromine-methanol to produce a mirrorlike finish, free from any surface irregularities. The final thickness of the substrateis controlled to produce the appropriate wiping clearance between the slider bin and the substrate surface. This control is necessary to eliminate Ga carryover on the surface of the epitaxial layer at the termination of the epitaxial layer growth. The polished wafer is loaded into the LPE reactor under a N, purge. The system is then baked under an H, atmosphere for 4 hr at 7OO0C,with the substrate wafer exposed, to saturate the melt. Prior to the growth, the melt temperature is reduced by 2°C to supersaturate the melt. The growth is initiated by sliding the melt over the substrate and continuing the temperature drop rate of l"C/min for the time required to grow the desired thickness. The melt and source wafer are changed after approximately 30 epitaxial layers have been grown. These 30 layers include approximately 26 thin, 3-pm layers used for implant substratesand four thick, 20-pm layers used for electrical characterization of the epitaxial layers. It has been observed that after approximately 30 layers have been grown, the layers begin to show an increased pit density, greater than 10 cm-2, and that the uniformity of the layer thickness decreases. The pits are believed to be due to a buildup of Ga,O, with time or to an accumulation of graphite particles from the graphite slider. The thickness nonuniformity is due to a depletion of the GaAs source wafer. The thick layers are used to measure the electrical propertiesof the layersby Hall measurements using the van der Pauw ( I 958) geometry. The criteria used for the acceptance of the buffer layers for use in implant or device investigations are that the Hall mobility measured at room temperature must be approximately 8000 cm2V 1 sec-' and that the Hall mobility measured at 77°K must be greater than 120,000 em2 V-I sec-l. The epitaxial layers are always n-type, with a net carrier concentration The analysis of Wolfe el a/. (1 970), using the Hall less than 1 X lOI4 mobility measured at 77"K, indicates that ND NA is in the range of 1 - 4 X loL4 cmb3and that the material is very closely compensated with ND in the same low I X 1014-cm-3range. The thickness uniformity of the 3-pm layers is adequate for the production of ICs with a 1-0 standard deviation of the thickness of about 20% over a single wafer, and a wafer-to-wafer uniformity of the average thickness of 10%. The surface morphology is of utmost importance in the fabrication of ICs,

+

2.

ION IMPLANTATION A N D MATERIALS

105

especially in contact printing lithography, and extreme care is taken to minimize the typical surface imperfections such as meniscus lines, terraces, pits, and Ga carryover. The best surface conditions are obtained using substratesoriented to within 0.2" ofthe (100) surface to minimize terracing. High-purity buffer layers have been grown by VPE using the AsCl, system (Cox and DiLorenzo, 1980);by the ASH, hydride system (Stringfellow and Horn, 1977); and by the OMVPE (Dapkus et al., 1981). These systems consist of a reactor, either horizontal or vertical, which contains a substrate heater and internal components that can serve as sources of Ga and/or dopants and also as getters for impurities. The reaction gases are introduced via a gas manifold. The systems are operated either at 1 atm or at a reduced pressure, depending on the particular technique used. The epitaxial layers are grown by the reaction of the appropriate vapors at the substrate which is held at a growth temperature of 600-700°C. The advantage of this technique over the LPE technique is the capability to grow large-area layers with very uniform thickness. The OMVPE system has produced layers with total impurity concentrations of 5 X loL4cm-, and mobility, measured at 77"K, of 125,000 cm2V-l set+ (Dapkus et al., 1981). The layers grown by the AsC1, system have net camer concentrations in the mid- 1014-cm-2range and show evidence of Cr diffusion from the substrate into the epitaxial layer when grown on Crdoped substrates (Cox and Dihrenzo, 1980). The hydride system buffer layers have been evaluated as part of our material investigation. The properties of the implanted and annealed layers are comparable to those obtained using the LPE buffer layers. The layers grown in the hydride system are high purity for the first 2 - 3 pm of growth, but for thicker layers the camer concentration increases (Stringfellow and Horn, 1977). This limits the usefulness of these layers in applications where thicker buffer layers are desired, e.g., to reduce backgating (see Part IV). The inability to grow thick layers also precludes the determination of the purity of these layers by a Hall measurement. These limitations of the VPE buffer layer material reduce the value of this material in an investigation of ion implantation or device studies. The growth of high-purity buffer layers by MBE has been demonstrated (Morkoc and Cho, 1979; Calawa, 1981). In this technique the layers are grown at 500 - 640°Cby the impingement of molecular beams of Ga and As on the substrate in ultrahigh vacuum (< Tom). Buffer layers have been grown using this technique with net camer concentrations in the mid1014-cm-3range, with mobilities, measured at liquid nitrogen temperature, greater than 100,000 cm2 V-I sec-'. These buffer layers are expected to be important when used in conjunction with the unique properties of MBE layers.

106

C. A. STOLTE

3. THERMAL STABILITY The use of bulk material as the substrate for ion implantation or as the substrate for epitaxial growth requires that the properties of the substrate material remain unchanged during the required thermal cycles. When the material is used as a substrate for epitaxial growth, it must remain semi-insulating during the growth cycle. In the case of the LPE growth described, this includes a 4-hr period at 700°C under a flowing H, atmosphere. The semi-insulating material produced by the 2-atm LEC technique using controlled doping with Cr-Te, as described, always meets the criterion that the sheet resistance after this heat treatment is greater than 1 X lo8 Q/sq. The high-purity, undoped, substrate material produced by the 2-atm LEC process meets this same criterion. It should be noted, however, that some material, both Cr-doped and high-purity, purchased from outside vendors has failed to satisfy this criterion. The ability of both the Cr-doped and the undoped semi-insulatingsubstrates to meet this thermal stability criterion, required for epitaxial growth, provides greater flexibility in the choice of the materials systems. This has aided in the investigation of backgating, as described later. Since the preferred technique used to produce the active layers used for the production of GaAs ICs is ion implantation, it is crucial that the substrate material be stable under the anneal conditions used to activate the implanted species. The condition used for the anneal, described in Part I11 of this chapter, is a heat treatment at temperatures up to 900°Cfor periods up to 30 min in an Ar atmosphere with the GaAs surface protected by a Si3N., cap. The second stability condition imposed on any material to be used for ion implantation is, therefore, that it retains its high resistivity under these conditions of anneal. In the case of the epitaxial layers, this means that they retain their high mobility and low carrier concentration during the anneal cycle. The LPE buffer layers, produced as described above, are stable and show no decrease in quality under these anneal conditions. The bulk material must meet these same criteria if it is to be used as a substrate material for direct ion implantation. A large percentage of the Cr-doped material produced a few years ago and a significant percentage of recent high-purity, as well as Cr-doped, materials exhibit a thermal conversion during the anneal cycle which in extreme cases reduces the sheet resistance from lo8 Q/sq to less than 300 Q/sq. The magnitude of the decrease in resistivity is determined by the impurity concentration in the substrate material. This conversion process, due to the out-diffusion of Cr during the anneal cycle, has recently been examined by many investigatorsusing direct measurement techniques such as SIMS analysis (Evans et al., 1979) and

2.

ION IMPLANTATION A N D MATERIALS

107

SU BSTAATE 1-1 0 1-2 * 1-3 x 1-4 3-1 0

3-2

NSi (cm-?

FIG.6. Sheet carrier concentration N, versus Si impurity concentration, Nsifor unimplanted semi-insulating GaAs substrates that have been annealed at 900°C for 15 min with a Si,N4 anneal cap.

radiotracer analysis (Tuck et al., 1979), as well as by inferring the mechanisms of the conversion from electrical measurements (Asbeck et al., 1979). Early work at Hewlett-Packard (Stolte, 1975) demonstrated the effect of Cr diffusion in a fairly crude but definitive experiment. The results of this experiment, with additional, more recent data, are shown in Fig. 6. The sheet carrier concentration of unimplanted Cr-doped material, which had been subjected to a 900°C anneal temperature for 30 min with a Si,N, cap, is plotted as a function of the background concentration of Si, measured by ASES on material from the same area of the ingot. These data represent material from several different suppliers; each sample was semi-insulating prior to the anneal cycle. This material was typical of the Cr-doped material available at the time of these experiments (Stolte, 1975). The Cr concentration in these materials, measured by emission spectroscopy, is greater than the Si concentration by a factor of at least 2. The carrier concentration profiles, measured by the capacitance- voltage (C- V ) technique, for these converted samples are shown in Fig. 7. The background Si concentration of the samples and the mobilities measured after the anneal are indicated on the figure. Based on these measurements, a simple model of Cr out-diffusionwas postulated to describe the conversion process. The decrease of the Cr concentration reduces the degree of compensation of the background donors, and this produces the thermal conver-

108

C. A. STOLTE 1017

-

8-

-

6-

-I

4-

'

2-

?

&..,,(

1

-3

4 2

z

10'6 8-

64-

:

2-

1015~

0.2

Substrate

0.4

0.6

lLm (OK)

(cm2V-I sec-I)

0.8

1.0

1.2

Nsi

(~rn-~)

1-4 3580 2.4 X 1016 2.3 x 1015 3-1 5840 1-2 4350 3.5 x 10'6 3.0 X loL6 1-3 4120 3-2 5 160 8.0 X lof5 FIG.7. Camer concentration profiles for different unimplanted semi-insulatingGaAs substrates that have been annealed at 900°C for 15 min with a Si,N, anneal cap.

sion seen in these substrates. The diffusion constant inferred from the data of Fig. 7, based on a simple diffusion model of Cr, is approximately 1 X lo-" cmz sec-l at 900°C. This value is in good agreement with the more recent value determined by Asbeck et al. (1979). The early work of Sat0 (1973) proposed a similar model; in that investigation, the conversion was dependent on the cap material used during the anneal cycle. The high-purity semi-insulating material is compensated by an excess of the EL2 electron trap, as described earlier. In this case, the decrease in resistivity can occur via a change in the surface stoichiometry.The loss of As by evaporation would produce donors while the loss of Ga via diffusion into the cap material, if used, would produce acceptors (Stolte, 1977)in addition to changing the relative donor to acceptor ratio of amphoteric species such

2.

ION IMPLANTATION A N D MATERIALS

109

as C, Si, and Sn. The degree of conversion will depend on the relative concentration of the EL2 level and the shallow-donor and -acceptor concentration in the surface region following the anneal. Recent investigations (Makram-Ebeid et a!., 1982; Lagowski et al., 1982b) have demonstrated a decrease in the concentration of the EL2 level at the surface during thermal treatments. This can produce a surface-conduction layer by reducing the degree of compensation of the background acceptors. In addition to these basic materials-related mechanisms of conversion, there is the possibility of incorporating impurities during the anneal cycle. These impurities can be introduced by the cap material or in the ambient used during the anneal and can lead to surface conduction for improperly annealed samples. An additional technique used to evaluate the stability of substrate material under implant and anneal conditions is Kr ion implantation (Higgins et al., 1978)to the same dose and depth as that of the dopant ion implant. This Kr implant produces the equivalent damage profile to simulate the diffusion and/or other effects which may be damage-dependent. This technique was used for a period in these investigations; the results obtained using the Kr-implanted samples always agreed with the unimplanted samples in the investigation of the thermal stability of the samples. As described below, a part of our substrate evaluation includes the use of a standard Se implant, and the effects of the implantation damage are evaluated as part of that procedure. The experiments prior to 1976 indicated a serious problem in the interpretation of results obtained from the implant and anneal experiments using standard Cr-doped substrates. This included greater than 100% doping efficiency in an implant experiment and carrier concentration profiles dependent on the particular substrate used. The decision was made to avoid the use of Cr-doped substrates for direct implantation and to concentrate on the use of the LPE buffer layers as the standard implant substrate. Because this was viewed as a necessary, but not a practical, solution in the long term, sources of high-quality bulk material were evaluated to lay the basis for the use of this material when it became available in reliable quantities. As demonstrated below, it is now possible to produce bulk material that has sufficient purity and stability under the required process temperatures to produce high-quality layers by direct ion implantation. 111. Ion Implantation

4. INTRODUCTION

The topic of ion implantation is broad and diverse, with many interdependent parameters. In this part, the importance of the implant and anneal

110

C. A. STOLTE

parameters on the electrical properties of the implanted and annealed regions is presented. In addition, the conditions necessary for the production of regions with optimal electrical characteristicsare given. The implant and anneal conditions were investigated using high-purity buffer material, described earlier. This material is ideal for this purpose since it is of very high purity and does not convert during the anneal process. Using this starting material, the properties of the implanted and annealed layers are evaluated independent of inconsistenciesof the material properties. The influence of the starting implant material on the properties of implanted and annealed layers, produced using standard implant and anneal conditions, will be presented. As a result of the investigation to be described, a set of standard implant and anneal conditions has been established for the production of active layers for the fabrication of GaAs ICs as well as for the evaluation of materials. In the discussion to follow, it will be assumed that these standard conditions are used in the investigation. If one or more of the implant and/or anneal parameters are varied, it will be specifically noted. The standard conditions are as follows: (1) Implant conditions. The substrate is oriented at a tilt angle of 10" between the beam and the normal to the ( 100)substrate surface and rotated 30 deg with respect ot the (1 10)cleavage plane to eliminate axial and planar channeling. The substrate is held at a temperature of 350°Cduring the implantation. The wafers are implanted bare, with no dielectric coatings, and are cleaned in a sulfuric acid/hydrogen peroxide etch prior to loading into the implant machine. (2) Anneal conditions. The implanted layers are annealed for 15 min at 850°C under flowing Ar. The surface of the wafer is protected with 1500 A of silicon nitride, which is deposited by a pyrolytic reaction of silane and ammonia at 650°C.The Si,N., deposition rate is 100A/min; the heat-up time prior to the deposition is 3 min with the wafer under flowing hydrogen. The wafer is given a very light surface etch in a sulfuric acid/hydrogen peroxide etch prior to loading into the chemical vapor deposition (CVD) reactor. A discussion of the implant and anneal conditions and the experiments which led to the adoption of the standard conditions is presented below. The electrical characterization of the implanted and annealed layers includes the determination of the sheet resistance p8, the effective mobility pe, the sheet camer concentration N,, and the carrier concentration and mobility profiles. The values of ps and p e are measured using Hall-effect measurements employing the van der Pauw geometry (van der Pauw, 1958) with the sample at room temperaure or liquid nitrogen temperature. The ohmic contacts are formed by alloying a standard NiCr-Au-Ge-Au

2.

ION IMPLANTATION AND MATERIALS

111

metallization system. The majority of the mobility measurements were made with a magnetic field of 1 150 G, and good agreement was obtained with measurements at 5000 G. The measurement of ps and ,uein conjunction with a layer-removal technique allows the determination of the carrier concentration and mobility profiles of the implanted and annealed layers (Mayer et al., 1967). The samples are thinned using a dilute etch,l00: 1 : 1 (H20:H202:H2S0,), which removes approximately 400 A/min. The sample geometry is designed to permit Taly Step measurements of the layer removed at each step. The carrier concentration profile is more conveniently measured using the standard Schottky barrier C- V technique. The ohmic contact used for this technique is the NiCr- Au-Ge - Au alloyed contact, which is coplanar with the evaporated A1 Schottky barrier contacts. The measurements are performed using an automatic LCR meter in conjunction with a calculator to measure the C- V and plot the carrier concentration as a function of depth. The depth range of the measurements is increased by etching a series of steps in the sample before the A1 Schottky barriers are deposited. With this technique, the series of concentration profiles obtained on the different etch steps are plotted together using horizontal, depth, displacements corresponding to the etch step heights. 5. ION-IMPLANT CONDITIONS The species used for ion implantation depends on the desired properties of the resulting layer. This discussion is limited to n-type implants since the GaAs ICs discussed in this chapter use MESFETs; the topic of normally off FETs, which are fabricated by p-type implants or very low-dose n-type implants, will not be discussed. The most crucial implantation procedure for GaAs ICs is that used to form the active channel region for the metalsemiconductor field effect transistors (MESFETs). The requirements for the channel region are a shallow-doping profile, approximately 0.1 -0.2 pm, a ~ , the highest mobilpeak concentration of approximately 1 X 10'' ~ m - and ity consistent with this doping concentration (approximately 4500 cm2V-' sec- ). The discussion to follow will first concentrateon the production of n-type layers suitable for channel regions; the topic of the formation of n+ regions to produce low resistivity regions and n2+ regions to form nonalloyed contacts is discussed later. The choice of the implant species for a particular application is dependent on many factors, including the availability of the ion species in the implantation machine available for use. The majority of the studies of n-type implants into GaAs have used Se, Si, S, Te, Sn, and Ge. Gibbons et al. ( 1975) have published implant range data in tabular form, which allows the

112

C. A. STOLTE

TABLE 111 RANGE AND STANDARD DEVIATION FOR

IONS IMPLANTED INTO GAAV

Energy

200 keV Ion species

Se Si

S

Te

Sn

Ge

R, (pm) 0.0695 0.174 0.151 0.0498 0.051 1 0.0735

400 keV

A R, ( p m )

-~

0.0313 0.0753 0.0667 0.0207 0.0216 0.0334

800 keV

R, (pm) A R, (pm) R, ( ~ m )AR, (pm) ~

0.137 0.351 0.307 0.0917 0.0950 0.1463

~

~~

0.0557 0.121 0.1 10 0.0364 0.0381 0.0594

0.280 0.675 0.600 0.179 0.186 0.300

0.0982 0.178 0.166 0.0654 0.0684 0.104

From Gibbons ef al. (1975).

calculation of the predicted carrier concentration profile for a large number of species in different substrate materials. The data shown in Table 111 give the range and standard deviation for some of the more useful implant species into GaAs at the maximum energies readily available in commercial machines. It should be noted that a 200-keV machine can produce an ion beam with an equivalent 400-keV ion energy by using the doubly ionized species, and a implanter can produce an 800-keV equivalent ion energy. The early investigations of n-type implantation into GaAs employed Te since it is the only useful n-type species that is heavier than the GaAs substrate. This allows the use of Rutherford backscattering (RBS)analysis (Chu et ul., 1978; Gamo et al., 1975; Eisen, 1975) to investigate the crystallineproperties of the implanted regions. These measurements include a determination of the implant-induced damage and the efficiency with which the dopant species is located on lattice sites. The use of Te as an implant species for the formation of channel regions is limited since the projected range of Te at 400 keV, the maximum energy available using singly ionized Te in a 400-keV machine or doubly ionized Te in a 200-keV machine, is just 0.092 pm and for doubly ionized Te in a 400-keV machine it is 0.179 pm. An example of the electrical properties obtained for results of Te implants into GaAs under the standard conditions, annealed at 900°C for 15 min, is shown in Fig. 8. Here, the carrier concentration profiles measured by the C- I/ technique are shown and compared with the predicted results using the published range and deviation data.This theoretical curve is adjusted in magnitude to determine the doping efficiency q and in the width of the profile to determine the diffusion coefficient. This fit to the experimental profile is discussed in more detail below. The difference

2.

113

ION IMPLANTATION A N D MATERIALS

Te + GaAs 4-

2-

101786-

J za

4-

I

L"

2-

10'6 8 -

64-

I

0.1

I

0.2

1

0.3

I

0.4

I

0.5

I

0.6

I

0.7

d (rm) FIG.8. Carrier concentrationprofiles for Te-implanted Cr-doped and LPE buffer substrates to a dose of 6 X 10l2cm-' at 500 keV and 350"C, annealed at 900'C for 15 min with a Si,N4 cap. Theoretical profile: 0 = 50%; R, = 0.1 13 pm; A R, = 0.044pm; and D = 1.1 X cm2 sec-'.

between the two experimental profiles is due to thermal conversion of the Cr-doped substrate. The species most often used for the channel-region implants are Se, Si, and S. These species have sufficient range to produce the necessary carrier concentration depth for the channel regions for MESFETs. The choice of the implant species in a particular application is determined by the electrical properties obtained with that species and on the preference of the organization established during the development of their implant and anneal technology. Sulfur produces high-mobility layers with good doping efficiencies, but during the anneal cycle can exhibit undesirable fast diffusion rates as illustrated in Fig. 9. The profile for S implanted into LPE buffer substratesis anomalous at the surface, and the implant into the Cr-doped substrate does not resemble the predicted gaussian profile. The best fit that can be made to the theoretical profile is that which uses a low q and ignores the surface

114

C. A. STOLTE

Cr -Doped Substrats

0

2

l"

f

Buffar LPE Theoretical Profile

1015L---i-

0

0.1

I

0.2

I

0.3

-A,

0.4

Substrate

0.5

I

0.7

0.6

d (pm)

FIG.9. Carrier concentration profiles for S-implantedCr and LPE buffer substrates to a dose of 5 X lo'* cm-2 at 250 keV and 350"C,annealed at 900°C for 15 min with a Si,N, cap. cm2sec-I. Theoretical profile: q = 1394; R, = 0.190 prn; A R , = 0.078 pm; D 2.2 X =i

region. The inconsistent profile shape limits the usefulness of S as an implant species. The camer concentration profile for Si implanted into a buffer layer, shown in Fig. 10,illustrates the good fit to the theoretical profile with an activation efficiency of 80%.Data for a Se implant into a buffer layer substrate are shown in Fig. 11. The predicted profile is shown and agrees with the experimental data assuming the diffusion coefficient and doping efficiency indicated on the figure. The influence of the anneal conditions on the doping efficiency and on the carrier concentration profiles is discussed below. The conditions used during the implantation of the dopant species into the substrate influence the properties obtained after the anneal process. The important parametersare the implant energy; implant dose; substrate material; orientation of the substratewith respect to the beam; temperature of the substrate; and the purity, uniformity, and the dose accuracy of the implant beam. This discussion will assume that the implant machine is capable of a

2. 2 -

-

115

ION IMPLANTATION A N D MATERIALS

Si -+ CaAr

10”-

8 6 -

I

5

a

7 THEORETICAL PROFILE

2

I

s

BUFFER LPE

2 -

1ol6-

0

0.1

0.2

0.3

0.4

0.5 d

0.6

0.7

0.8

0.9

(m)

FIG. 10. Camer concentration profiles for a Si-implanted LPE buffer substrate to a dose of

1 X 10” cm-2 at 400 keV and 350°C, annealed at 850°C for 15 min with a SiO, cap. Theoretical profile: 4 = 80% R , = 0.351 pm; A R, = 0.121 pm; D = 3.3 X cm2 sec-*.

high-quality ion beam with good uniformity and dose accuracy. This is the case for properly maintained implant machines now available. The orientation of the implanted substrate with respect to the ion beam during the implantation influences the carrier concentration profile of the implanted species. This is illustrated in Fig. 12 for Se implants into GaAs at different substrate orientations, as indicated in the figure. The standard implant and anneal conditions are used, with the exception of the substrate orientation. The angles indicated on the figure are the tilt angle and the rotation angle. The orientations listed are accurate to k 1 deg and therefore the (0 deg, 0 deg) orientation is not precise enough to be a true channeling direction in the lattice. With the tilt angle at 0 deg there is significant axial channeling (Wilson, 1976) to produce an abnormally deep profile. The narrowing of the profile as the rotation angle is increased, with the tilt angle held at lo”,is shown in Fig. 12. A substrate rotation of 30-45 deg from the ( 1 10)direction is necessary to eliminate planar channeling. These results are in agreement with those of Wilson and Deline ( 1980), where an extensive investigation of these effects is reported for Se, Si, S, and Te implants into GaAs. Through-dielectric-layerimplantations have been investigated to evaluate the effect of these layers on the channeling phenomenon and to evaluate the electrical‘properties of this implant technique. Results of this investiga-

116

C. A. STOLTE 10" 8 6

sa + GlA¶

4

2

10':

-B "I

8

6 4

4

z *

I D

2

10" 8

6 4

2

10" 0

0.1

0.2

0.3

0.4

d

0.5

0.6

0.7

(won)

FIG. 1 1. Camer concentration profiles for a Se-implantedLPE buffer substrate to a dose of 6 X loi2 cm-2 at 500 keV and 350'C, annealed at 850°C for 15 min with a Si,N, cap. Theoretical profile: q = 67%;R , = 0.172 pm; ARp = 0.067 pm;D = I. I X lo-" cm2 sec-I.

tion are shown in Fig. 13, where camer concentration profiles produced by Se implants through Si,N, are shown. One effect of the nitride film is to randomize the ion beam direction before it enters the GaAs substrate. This produces a profile corresponding to the random orientation implant direction even for the nominal (0 deg, 0 deg) direction. The decrease in the range of the implanted ion with increasing film thickness is due to the loss of ion energy as the beam travels through the nitride film. The doping efficiency of

2. 8

117

ION IMPLANTATION A N D MATERIALS

-

6 -

Sa-+GsAr

4 -

ROTATION)

(0.0)

/

1015 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

d (pd

FIG.12. Camer concentrationprofiles for Se implanted into LPE buffer substratesoriented as indicated on the illustration. The Se implant was to a dose of 6 X 10I2cm-2 at 500 keV and 350"C,annealed at 850°C for I5 min with a Si,N, cap.

the implant decreases for nitride thicknesses of 300 and 500 A as a result of Se implanted in the nitride film. There is a slight increase in the doping efficiency at the 800-A film thickness. This is believed to be due to the knock-on of the Si atoms from the nitride into the GaAs substrate, as predicted by the calculations of Christel et al. ( 1980). Through-dielectric implants are used in the fabrication of GaAs ICs by Rockwell International (Welch et al., 1980) with good results, and there seems to be no significant evidence of knock-on dopants in the implanted layers. The temperature of the substrate during implantation has an effect on the

118

C. A. STOLTE 10'8

8

6

Se +GaAn

4

2

1017 8

-

m

5

c

6

4

4: E

I

0

=

2

10l6 8

6 800 A

4

\ \

2

10''

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

d (wnun)

FIG. 13. Camer concentration profiles for Se-implanted through Si,N, layers, with the thicknessesindicated on the illustrationwith the substratesoriented in the nominal channeling cm-* at 500 keV and 350°C,annealed at direction. The Se implant was to a dose of 6 X 850°C for 15 min with a SIN, cap.

properties of the layers, which is dependent on the implanted species and the dose. For high-dose implants, > 1 X loL4cm-2, the combination of the incident ion flux and the substrate temperature determine the degree of implant-induced damage and, in extreme cases, whether or not the implanted region is driven amorphous. It is generally agreed that the subsequent activation of the layer is less if the sample is driven amorphous during the implant (Harris et al., 1972). At moderate implant doses, in the range 1 X loL2-1 X lOI3 cm-2, the effect of the implant temperature on the

2.

119

ION IMPLANTATION AND MATERIALS

characteristics of the implanted and annealed samples is dependent on the species implanted. This is illustrated in Fig. 14, where the doping efficiency and mobility are plotted as functions of the implant temperature for S and Se implants. In the case of the S, there is a significant effect above an implant temperature of 300°C; in the case of Se, the effect of the implant temperature is minimal. The majority of the Se implants reported in these investigations were performed at an implant temperature of 350°C. This is our standard condition. It should be emphasized, however, that for the implant dose required for formation of the channel regions by Se and Si implants, the properties of the annealed layer following a room-temperature implant are essentially the same as those produced by an elevated temperature implant. This is of practical significance due to the complexity of the apparatus required to heat the substrate during implantation.

6. ANNEALCONDITIONS It is necessary to anneal the implanted regions to remove the damage produced during the implant process to obtain layers with useful electrical properties. This requires anneal temperatures in excess of 800°C for n-type implants into GaAs. At these temperatures, it is necessary to control the loss

- 5000

-

r

- 4000

5 n

-6

N

-

3000

c

::I U

W

20

1'"O '0W

100

200

300

IMPLANT TEMPERATURE

400

500

O

("C)

FIG. 14. The influence of the substrate temperature during implantation on the doping efficiency r] and the effective Hall mobility p for Se and Si implants into LPE buffer substrates. The Se implants were to a dose of 3 X 10l2cm-2 at 500 keV, and the Si implantswere to a dose of 1 X lOI3 cm+ at 250 keV, annealed at 900°C for 15 min with a Si,N, cap.

120

C. A. STOLTE

of As from the surface during the anneal and at the same time avoid the in-diffusion of contaminates or the out-diffusion of the dopant species. There are numerous techniques reported in the literature to minimize the loss of As during the anneal, including the use of dielectric layers, capless and/or proximity anneal and transient anneal techniques. The technique used by a given organization is determined by the specific technology which each has developed. In the work reported in this chapter, the standard cap is the chemical vapor deposition (CVD) Si,Ni, dielectric layer described earlier. Other cap materials have been evaluated during this investigation including reactively sputtered AlN and Si3N, and CVD Si02. The A1N films had a very low oxygen concentration (lessthan 2%) as compared to the high oxygen content films reported in the literature (Pashley and Welch, 1975). It is believed that poor adhesion observed is due to the lack of oxygen. Reactively sputtered Si3N, films yielded good adherence but produced inferior electrical properties. This is due to a high ( 15%)oxygen concentration in these films. Thick, 7000-A CVD SiOz films grown in a Silox reactor at 450°C give better results for Si implants than the standard CVD Si3N, cap. The influence of the anneal cap for Si implants is illustrated in Fig. 15. The increased doping efficiency for Si implants using Si02 caps is due to the out-diffusion of Ga through the cap (Vaidyanathan et al., 1977), which produces Ga vacancies near the surface. These vacancies yield a higher Si on a Ga-site concentration compared to the Si on an As-site concentration, which results in a net increase in the n-type concentration for the amphoteric Si dopant (Bhattacharya et al., 1983).Although the doping efficiencyis higher using the oxide cap, as compared to the nitride cap, there can be a problem with the reproducibility of results if the Ga out-diffusion is not consistent from run to run. In the case of the nitride cap, there is no Ga out-diffusion; therefore, more consistent results can be expected. The opposite effect of the cap material is observed in the case of Se implants, as is illustrated in Fig. 16. In this case, the nitride cap gives better doping efficiencyas compared to the efficiency obtained with the oxide cap. The nitride cap used in these investigations has been very reproducible and has produced reliable results since the initiation of the work in 1975. The thermal expansion mismatch between the nitride film and GaAs produces cracks in the nitride for films thicker than approximately 2000 A. The surface quality of the samplesis unchanged during the anneal cycle using the standard 1500-A-thick cap. The nitride films produced are pinhole free; there is rarely evidence of a thermal etch pit due to a pinhole in the nitride film. An indication of the integrity of the nitride films is the successful annealing of samples with nitride films as thin as 300A with excellent surface properties and electrical characteristics. The through-nitride-im-

2.

121

ION IMPLANTATION AND MATERIALS

4t

Si + GaAs

2 -

I

? I

-

1017 8 6 -

e 4 -

ic

I D

2

2 -

10'8

-

0

I

1

I

I

I

1

I

I

I

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

d

Anneal cap

tlw

(mum)

p (cm2 V-l sec-l)

1500-A Si3N, 64 4250 7000-A Si02 95 4300 FIG. 15. Carrier concentration profiles for Si implants into LPE buffer substrates. The Si implants were to a dose of 1 X 10" cm-, at 400 keV and 350"C,annealed at 850°C for 15 min with 1500-A Si,N, or 7000-A SiO, cap, as indicated on figure.

planted layers represented by the data of Fig. 13 were annealed with the thin nitride films. The standard nitride films are deposited in a small research-type CVD reactor. Recent experiments using a commercial Si CVD reactor have produced nitride films with properties comparable to those produced in the small reactor. In the commercial reactor, the cap and anneal are done in one load by first depositingthe nitride film at 650"C, using silane and ammonia, and then ramping the temperature up to 850°C under H, and holding that temperature for 15 min to anneal the sample. This cap and anneal technique, capable of batch-annealing of large-diameterwafers, is a production process as opposed to the limited throughput of the small research CVD nitride reactor. The Santa Rosa Technology Center of Hewlett-Packard uses a Si02 anneal cap to anneal Si-implanted GaAs layers in a high-yield integrated circuit fabrication process (Van Tuyl et al., 1982).

122

C. A. STOLTE

8

-

6

-

4

-

Ss + GaAs

2 -

1017

-

8 -

-6

6

-

0

I

4

-

4

z I

2210'6

-

8 -

6 -

4 -

2 -

10'51 0

I

0.1

I

0.2

I

I

0.4

0.3

I

0.5

I

0.6

1 0.7

d (mn)

Anneal cap

r](W

,u (cm2V-1 sec-I)

1500-A Si,N4 67 4590 7000-A SiO, 57 4270 FIG.16. Carrier concentrationprofiles for Se implants into LPE buffer substrates. The Se implants were to a dose of 4.5 X lo1, cm-* at 500 keV and 35OoC,annealed at 850°C for 15 min with a 1500-A Si,N4 or 7000-A SiOz cap as indicated on the figure.

The use of capless (Kasahara et al., 1979; Kasahara and Watanabe, 1980), proximity (Immorlica and Eisen, 1976; Molnar, 1980), and/or controlled As pressure (Malbon et al., 1976) anneal procedures has proven useful in producing good results in many laboratories. These anneal procedures are similar to those used to protect the GaAs surface during the diffusion of

2.

123

ION IMPLANTATION A N D MATERIALS

dopants in a sealed ampoule or flowing gas technique. With these anneal techniques, it is necessary to eliminate the loss of As from the surface by an As overpressure. These techniques can yield better results since the stoichiometry of the sample can be controlled during the anneal. This flexibility can, however, lead to potential problems with the uniformity and consistency of the results if the process is not under complete control. One of the most significant parameters in the production of high-quality layers is the anneal temperature. This is illustrated for the case of Se in Fig. 17, where the doping efficiency and mobility are plotted as functions of the anneal temperature. The standard anneal temperature, 85OoC,used in these investigations is more than adequate to anneal the moderate-dose-implant layers used for the channel region of MESFETs. The situation is much

-c

P

<

100-

Se + GaAs

80 -

V

9u

60-

0

40-

U U W

2 0

,

20-

0

dl 9

1000

/'

.d

700

I

I

800

750

ANNEAL TEMPERATURE

I

850

I

900

,

(%I

(b) FIG. 17. Influence of the anneal temperature on the (a) doping efficiency q and (b) effective mobility ,n for Se implants into LPE buffer substrates to the dose indicated on the figure at 500 keV and 350"C,annealed at the indicated temperatures for 15 min with a Si,N, cap.

1 24

C. A. STOLTE

different when higher-dose implants are used, for example, for ohmic contact formation, as discussed below. An additional consideration in the selection of the anneal time and temperature cycle is the diffusion of the implanted species, and the diffusion of Cr, if Cr-doped substrates are employed, during the anneal process. The effect of diffusion of the implanted dopant is illustrated in Fig. 18, for the case of Se implants in GaAs. The carrier concentration profiles are calculated using the range and deviation data of Gibbons et al. (1975) and the diffusion of implanted ions. The starting condition is the assumed gaussian lo’* 8 6

Se -t GaAs

4

2

10”

8 6

F 4

-I c

2

10’6 8

6 4

2

1015 ._

0.00

0.10

0.20

0.30

0.40

0.60

0.60

0.70

d (CM)

FIG.18. Calculated atomic profiles for Se implanted into GaAs. The calculation assumes a gaussian profile with a projected range R, of 0.172 pm and projected deviation A R , of 0.067 pm, corresponding to an energy of 500 keV; and a dose of 3 X lot2cm-*. The values of Dt, the diffusion coefficient times the time, are given in the figure.

2.

125

ION IMPLANTATION AND MATERIALS

profile; a diffusion bamer at the interface between the GaAs and the anneal cap layer is assumed in the calculations. The anneal cycle has the effect of increasingthe A R, of the implant profile to A RpeW = (A Rz 21)t)1/2, where A R, is the profile standard deviation without diffusion, D is the diffusion coefficient at the anneal temperature, and t is the time duration of the anneal. Analysis of the experimental carrier concentration profiles, shown in Figs. 8- 11, yields diffusion coefficients of approximately 2.2 X cm2 sec-l for S and 1.1 X cm2 sec-I for Te at 900°C. The value for Si is 3.3 X cm2sec-', and for Se the value is 1.l X cm2sec-' at 850°C. The value of the diffusion coefficient for S is derived for S implanted into buffer material; S implanted in other types of material yields larger values. In order to minimize diffusion, the anneal time must be held as short as possible, consistent with good electrical characteristics. There is minimal improvement in the electrical properties for anneal times greater than 10 min under our anneal conditions; therefore, 15 min is the standard anneal time used in these investigations. In addition to these techniques, the use of transient annealing (Sealy, 1982)has been demonstratedin the laboratory for implants of Se (Chapman et al., 1982), Si (Kuzuhara et al., 1982; Arai, 1981), and for Zn and Si (Davieset al., 1982).This technique, in which the temperature ofthe sample is raised as high as 900°C in a matter of seconds and in which the entire temperature cycle is less than a minute, produces good activation and mobilities for concentrations up to the mid-1018range. The use of pulsed e-beam and laser annealing for higher-dose implants will be discussed in Section 8. In summary, the standard conditionsof implant and anneal were selected on the basis of the experiments described here. These conditions have been used in our implant investigations and in the preparation of materials for the investigation of GaAs ICs since 1975. This provides a consistent set of experimental procedures and allows meaningful comparisons of other parameters which influence the properties of the implanted and annealed regions and the performance of GaAs ICs.

+

7. SUBSTRATE INFLUENCE The formation of the channel region for the fabrication of GaAs MESFETs is a crucial step in the production of integrated circuits. The emphasis of the work described in this section will be on the comparison of various substrate materials used for the formation of active channel regions by ion implantation. The influence of the substrate material has been investigated using Se as the implant species and the standard implant and anneal conditions to allow meaningful comparisons of the different substrate mate-

126

C. A. STOLTE

rials. The influence of the starting material on the performance of circuits is discussed in Part IV. The standard material used in the majority of these investigations is the high-purity buffer layers grown on Cr-doped semi-insulating substrates. This starting material is the standard of comparison for the implant investigation as well as for the production of ICs. During the several years of this investigation,a large number ofdifferent substratesfrom a variety of sources have been evaluated, including material from outside vendors as well as materials synthesized at Hewlett-Packard. The electrical characteristics of the implanted and annealed layers to be considered are the doping efficiency, mobility, doping profile control, uniformity, and consistency of these characteristics as a function of the properties of the starting materials. The substrate material used for implantation can have a large influence on the profiles obtained. Substrate material that shows a significantthermal conversion during the anneal produces an abnormally high-concentration profile with a long tail region on the profile (see Fig. 8). This is the result of background donor impurities in the substrate material which become electrically active as a result of the Cr out-diffusion during the anneal cycle, as discussed in Part 11. An additional diffusion effect which also produces an abnormal profile is shown in Fig. 9. The long diffusion tail observed for S implanted into Cr-doped substrates is believed to be due to a vacancy-enhanced diffusion. In the case of S implants, the profile characteristics are very dependent on the substrate material. Another deviation from the predicted carrier concentration profile shape is observed using material grown under high-purity conditions, described in Part 11, with a small amount of Cr added to the otherwise high-purity melt to evaluate the influence of Cr. The profiles shown in Fig. 19 illustrate the changes produced by the addition of the amount of Cr indicated on the figure, The profiles for Se implants into the buffer layer and into high-purity, undoped materials are as expected; the implants into the Cr-doped substrates show anomalous behavior. The excess Cr incorporated in the substrate compensates the implanted donor, and the net effect is to decrease the magnitude of the profile in the tail regions. There is also a large decrease in the magnitude at the peak of the profile, which is larger than can be explained by the background concentration of Cr in the material. This discrepancy is due to the pileup of Cr in the damage region created during the implant, as observed using SIMS analysis (Evans et al., 1979). The profile data for the different substrate materials demonstrates that the choice of the substrate material is very important for the production of high-quality devices. The properties of the substrate material have a dramatic effect on the doping efficiency and on the camer concentration profile shape, as illus-

2.

ION IMPLANTATION A N D MATERIALS

127

Sa + GaAs

10151

0

I

I

1 0.4

0.2 d

I

0.6

(rd

FIG. 19. Carrier concentration profiles for Se implanted into the types of substrates indicated in the figure to a dose of 6 X 10l2cm-2 at 500 keV and 350"C,annealed at 850°C for 15 min with a Si,N, cap.

trated earlier. The properties of the substrate material also affect the mobility ofthe implanted and annealed layers, as reported in the literature (Stolte, 1975). The results of that experiment are summarized in Figs. 20 and 21. In Fig. 20, the experimental results used to obtain meaningful mobility measurements on implanted and annealed layers are shown. In this case, S was implanted into bulk GaAs, and the differentialvan der Pauw technique was used to measure the carrier concentration and Hall mobility profiles. This technique was used on a number of different substrate materials and provided the data to investigate the dependence of the mobility on the carrier concentration for different substrate types. The data from Fig. 20 are replotted in Fig. 21, where the mobility as a function of carrier concentration is plotted for this sample and for data obtained from other samplesin the same way. In Fig. 2 1, the results obtained for two implanted samples using the standard buffer material and four direct

128

C . A. STOLTE

10": 10";

-fi

P

C

1017:

- 6000 7 -4000

i,,,, -2000 2000

10160

O.'l

0:2

OI3

014

015

0:s

i L

5

N

a

0.71000 0.7

d (rm)

FIG.20. Carrier concentration and mobility profiles measured by the differential Hall technique for S implanted into a LPE buffer substrate to a dose of 2 X loL3cm-* at 250 keV and 350"C,annealed at 850°C for 15 min with a Si,N, cap.

implanted samples with different Cr concentrations are plotted; the Cr concentrations are indicated on the figure. Theoretical mobility versus carrier concentration curves (Rode and Knight, 1971) for the indicated compensation levels are plotted on the figure for comparison purposes. There is a large substrate influence on the mobility in the carrier concentration range of 1 X 10'' cm-3 due to the Cr concentration. This is the doping concentration used for MESFET channel implants. Thus, the excess Cr decreases the mobility and, therefore, will have a deleterious effect on the devices fabricated using this substrate material. These mobility results are in agreement with the calculations of Debney and Jay (1980). The influence of the substrate material on the mobility of implanted and annealed layers can be more conveniently measured using the surface van der Pauw technique to measure the Hall mobility on implanted and annealed samples. The mobility measured in this way is an effective mobility since it is measured on a nonconstant doping concentration. If the profile characteristicsfor the different substrates are reasonably consistent in shape and magnitude, the measured effective mobility is a meaningful indicator of

2.

129

ION IMPLANTATION A N D MATERIALS

1

S + GaAs

6000

c

I-

.?

4000

>

-

N

E

t

2000

0

0

0.8

1.6

2.4

3.2

4.0

n ( x 10’~crn-J)

FIG. 21. Hall mobility as a function of camer concentration for S implanted into the indicated GaAs substrates. The data are taken from Fig. 20 and from similar data obtained using the different substrates. The implant and anneal conditions in all cases are the same as indicated in Fig. 20. The dashed lines represent the theory of Rode and Knight (197 1).

material quality. Additional information is obtained when the Hall mobility measurements are extended to liquid nitrogen temperature. The results of an extensive investigation, spanning a time period of about three years (Stolte, 1980), of the properties of implanted and annealed layers in a large number of different substrate materials is summarized in Fig. 22. In this figure, the effective Hall mobility measured at room temperature and at 77°K for a large number of different substrate materials is plotted. In all cases, the standard implant and anneal conditions were used so that a meaningful interpretation of the results is possible. In this figure, the results are separated into regions representingthe different type substrates. The first three samples represent results obtained using high-purity LPE buffer material grown on Cr-doped material. These samples illustrate the desired mobility properties, namely, a high-room-temperature mobility, >4200 cm2V-I sec-I, and a significant increase in the mobility measured at 77°K. The next series of samples represent 17 ingots grown at the Optoelectronic Division of Hewlett-Packard using the 2-atm LEC technique described earlier. For each ingot, there are two data points: One represents the head of the ingot, the other the tail of the ingot. With the exception ofone sample, all the results show the desired mobility behavior. The sampleslabeled 9 and 10 were pulled using the in situ injection cell technique described in Part 11; the other ingots were compounded in a quartz ampoule and pulled from a quartz crucible. These 17 ingots were grown and processed over a 3-yr

I, , ,

, ,

,

1

,

,

I

,

,

, I L ,,I.,

I

,

'

L

2.

ION IMPLANTATION A N D MATERIALS

131

period and therefore demonstrate the consistencyof the growth technique as well as the consistency of the implant and anneal procedures. The next five samples of Fig. 22 represent ingots pulled by the same low-pressure LEC technique in a different facility of Hewlett-Packard, the Technology Center at Santa Rosa (SRTC). These samples show the desired mobility properties, with the exception of one sample. This demonstrates that the low-pressure technique is transferable and not unique to one reactor at one site. High-purity, undoped material from outside sources has also been evaluated using these standard implant and anneal techniques. The next three samples are from ingots grown in a Metals Research high-pressure LEC reactor using in situ synthesis. The next three samples represent ingots grown at the Naval Research Laboratory (Swiggard et al., 1979). These six samples have the desired mobility behavior and demonstrate that this semi-insulating material, produced without Cr doping, is of consistently high quality and is not restricted to one organization or to one technique. As noted in Part 11, other organizations have purchased the high-pressure LEC reactors and have pulled material of high quality, as has been reported in the literature (Fairman et al., 1981;Thomas et al., 1981;Hobgood et al., 1981). The effect of adding Cr to high-purity material is shown in the next series of 9 points in Fig. 22. In each case, the material wasgrown under high-purity conditions, except for the intentional addition of small, controlled amounts of Cr. The effect of the added Cr is to decrease the room-temperature mobility and also to produce a much lower 77°K mobility as compared to the high-purity material. The final six samples of Fig. 22 represent data obtained using Bridgman material from two different sources. These materials contain a small amount of Cryand this is reflected in the measured mobility for the implanted and annealed samples. The effect on the mobility of adding Cr to high-purity material is shown in Fig. 23, where the data of Fig. 22 are replotted as a function of the Cr concentration as measured by ASES. The sensitivityof this technique is 1 X lOI5~ m - those ~ ; samples with Cr below the detection limit are plotted to the left of the figure with no horizontal scale. From these data, it is seen that the addition of Cr, even in small amounts, degrades the mobility of the material in addition to influencing the carrier concentration profiles, as shown in Fig. 19. All the materials represented in Fig. 22 were thermally stable under the cap and anneal test conditions, with the exception of three of the commercial samples with low Cr concentrations. These showed a slight thermal conversion under the cap and anneal conditions. The consistency of the implanted and annealed layers produced in the high-purity ingots grown by the 2-atm LEC technique is very good. The data in Fig. 24 illustrate the consistency of the carrier concentration profiles for

132

C. A. STOLTE 5500 0

5000 -

r

b

-6

4000-

oo O

Lo

'

0

O

o o o o o

..

a

UNDOPED c-

I

2500

.

A A

0

3500-

3000 -

S,.* GaAn

0

08,

0

n o A'

Cr DOPED

.,

. 0

A 1

17

FIG.23. Hall mobility measured at 300°K (0,HP; other) and at 77°K(0,H P A, other) as a function ofthe Cr concentration measured in the substrate material by ASES. The samples represented on this figure are those of Fig. 22.

I

-

?

I

RANGE OF PROFILES FROM41 WAFERS

a

L

I

a

L

d (rm)

FIG.24. Carrier concentration profile uniformity for Se implanted and annealed under the standard conditions for 2 1 ingots grown using the 2-atm LEC technique. These samples are the HP high-purity LEC and the HP SRTC samples indicated in Fig. 22.

2.

ION IMPLANTATION AND MATERIALS

133

4 1 wafers taken from 2 1 high-purity LEC ingots. The carrier concentration profiles are very reproducible with a very small range of variation. These data, taken over a period of three years, also illustrate the consistency of the implant and anneal procedures. Another indication of the uniformity and consistency of the implant and anneal procedures in different materials is that provided by a measurement of the sheet resistance. The results presented in Table IV were obtained by a noncontact microwave absorption measurement of the sheet resistance. These data represent four samples implanted into four different substrate materials, including one buffer layer and wafers from three different highpurity ingots. The uniformity over a single wafer is very good, Q less than 3.1 %, and the wafer-to-wafer consistency is also very good, Q less than 3%. A more practical measurement of the uniformity and consistency of the implanted and annealed properties of layers produced for MESFETs is a measurement of the saturated source-drain current prior to the gate step in the circuit fabrication process. Data for 16 buffer layer implants and for 12 direct implants into high-purity material are given in Table V. There is good uniformity, Q less than 4%, on each wafer as well as good wafer-to-wafer consistency, Q less than 6.1%. In addition, there is good agreement in the values of the saturated source-drain current for the two different material types. This uniformity and consistency are also experienced in the integrated circuits fabricated using these materials and implant procedures, as described in Part IV. The preceding paragraphs have demonstrated the quality and consistency of implanted and annealed layers that are suitable for the formation of channel regions of MESFETs. The techniques used are compatible with a TABLE IV UNIFORMITY OF IMPLANTED WAFERS'

p-wave n1.q measurements Sample No.

Substrate

p, (Q/sq)

Se 320 Se319 Se318 Se 317

LPE Buffer F402No. 13 F403No.70 F405 No. 59

24 1 252 257 256 ~~

Ave

252

0

(96)

1.8 1.5 2.8 3.1 ~

2.9

a Implant: Se, 500 keV, 6 X 1OI2 cm-*; anneal: Si,N,, 850°C, 15 min.

134

C. A. STOLTE TABLE V UNIFORMITY OF MESFET IMPLANTS (Im,MEASUREMENTS)

Number of 1 X 1 in. wafers

Substrate ~

High-purity LPE buffer High-purity bulk

Average uniformity on wafer (%)

Wafer to wafer uniformity IDss(mA)

.(%)

~~

16 12

3.2

85.8

4.0

83.9

5.0 6.1

selective implant procedure as is needed, and used, for the production of complex integrated circuits. An example of the application of these techniques is the production of integrated circuits fabricated in both the high-purity buffer materials as well as in high-purity, undoped LEC material using the te.chniques described. The performance and properties of these circuits are described below in the device results section. 8. HIGH-DOSE IMPLANTS

High-dose implants can be classified into two types, depending on the intended application. The first includes those used to produce regions with low sheet resistance, less than 150 fJ/sq. The low sheet resistance regions are used to decrease the source -drain resistance of MESFETs and to produce low resistance passive components. The technology for the formation of these regions includes the use of high-temperature (greater than 9OO0C) anneal temperatures and special cap or capless techniques to preserve the surface at the higher anneal temperatures. Dual-speciesimplants (Ambridge et al., 1975; Stolte, 1977; Woodcock, 1976; Stoneham et al., 1980)designed to increase the doping efficiency of high-dose implants by stoichiometry control have been used to decrease the sheet resistance. Multienergy, singlespecies implants yield a reduction of the sheet resistance by producing an increased carrier concentration profile depth. In contrast to the requirements for channel-region implants, the profile control, mobility, and consistency of the implanted and annealed regions are of secondary importance to the requirement for low sheet resistance. The second application of high-dose implants is the formation of ohmic contacts by an implant and anneal procedure without the use of alloyed contacts. This application of ion implantation has been investigated, and good progress has been made using laser beam and e-beam annealing. The major improvement to be gained by nonalloyed contacts is that the same metal used for the MESFET gate can be used for the ohmic contacts. This simplifiesthe process and would improve the performance and reliability of

2.

135

ION IMPLANTATION A N D MATERIALS

the integrated circuits. The formation of these high carrier concentration regions is discussed below. Increasing the dose of the implant species to obtain lower sheet resistance decreases the doping efficiency, as indicated in the compilation of data shown in Fig. 25a. In this figure, the sheet carrier concentration, measured by the van der Pauw technique, is plotted as a function of the implant dose for three different species. The general trend in all the data is the same, i.e.,

4" 100

Sn

10 10'2

'

I

1013

1 I I I

1014

,N

I

1 1 1 1

1015

I

I l l 1

10'6

I

I

Ill 10"

bm-2)

(bl FIG.25. Total sheet camer concentration N, (a) and sheet resistivitypa(b) as a function of the implant dose for Si (50 keV), Se (100 keV), and Sn (250 keV) implanted into LPE buffer substrates at 35OoC,annealed at 850°C for 15 min with a SipN, cap.

136

C. A. STOLTE

the doping efficiency decreases to less than 1% at the high end of the dose range. Investigations of this effect have demonstrated (Lidow et al., 1978a) that the decrease in doping efficiencywith increasing dose is due to saturation solubility of the dopant in GaAs.The maximum camer concentration is limited to the solubility limit at the anneal temperature. The effect of increasing the implant dose on the sheet resistance of the implanted and annealed layers is demonstrated for the same set of samples in Fig. 25b. The decrease of the sheet resistance as the peak concentration approaches saturation is due to a broadening of the profile of the electrically active dopant, as demonstrated in Fig. 26. Here the camer concentration profiles for Si implants are plotted for differentimplant doses. These data were taken using the differential van der Pauw technique. The mobility for these implanted and annealed layers was very low at the surface, indicating a heavily damaged region, which results in a very low-doping efficiency in the near surface region. The maximum carrier concentration obtained at the anneal temperature used in these experiments, 85OoC,is 4 X lo1*~ m - and ~, the decrease in the sheet resistance with increasingdose is due mainly to the deeper carrier concentration profile at the higher dose. The atomic concentration profile, measured by Auger spectroscopy, for a dose of 2 X 10l6cm-2 is shown in the figure. The implanted dopant in excess of the saturation solubility is not electrically active. The more extensive experimental data and theory reported by Lidow et al. (1980) are in agreement with this simple model. The effect of increasing the anneal temperature on the sheet carrier concentration and sheet resistance is shown in Fig. 27 for Se implants. In these experiments,the dual dielectriccap developed by Lidow et al. (1978b) was used to prevent the deterioration of the GaAs surface at the elevated temperatures. The increase of N, with temperature agrees with the saturation solubility model proposed by Lidow et al. (1978a). The highest temperature used, 1 lOO"C, resulted in a peak carrier concentration of 1 X loL9 cm-) and a sheet resistance of 30 n/sq.The technological problems at these extreme temperatures preclude the technique as a practical solution for the production of high concentration regions. The doping efficiency at high-implant doses can be increased by controlling the stoichiometry of the substrate by dual-species implants. The data of Fig. 28, obtained in the investigation by Stoneham et al. ( 1980), illustrate the use of a dual-species implant, Se plus Ga, to increase the peak carrier concentration and therefore decrease the sheet resistance of the implanted and annealed layers. In the investigation of Stoneham, a sheet resistance of 9 Q/sq was obtained using a Si plus P dual-species implant annealed at 1000°Cfor 15 min. The most reproducible technique for the production of low sheet resist-

2.

137

ION IMPLANTATION A N D MATERIALS

r

2 -

1019

-

8 -

r 7 6 -

-ga r

4 -

I 0

z

2 -

10’8-

8 6 -

4 -

p

DOSE = 2 x

0

\ \

\ \

t

DOSE =q2=x3.2% 1014 cm-*\ \\

p*=3B5s2lSs

I

2 -

\

1

\

I

DOSE = 2 x 1015 Cm-f

A

L

q-1.2% p,=115~llx1 I

I

I

I

I

1

0.1

0.2

0.3

0.4

0.5

0.6

d (mm)

FIG.26. Camer concentrationprofiles and atomic concentration profile for Si implanted into LPE buffer substratesat 100 keV to the doses indicated on the figure, annealed at 850°C for 15 min with a Si,N, cap. The doping efficiency q and the sheet resistance p, measured for each dose are indicated on the figure.

ance regions is by implantation of a light species, e.g., Si, in multienergy steps to produce a high carrier concentration, near the solubility limit, which extends over a deep region. An example of this type of implant is shown in Fig. 29, where the results of triple-energy Si implants into buffer LPE and high-purity bulk substrates are shown. The sheet resistances for these im-

138

C. A. STOLTE

t

Se +GaAr

850

I

I

I

I

900

950

1000

1050

1100

ANNEAL TEMPERATURE ("C)

FIG.27. Sheet carrier concentrationN, and sheet resistance p,, as a function of the anneal temperature for Se implants into LPE buffer substratesto a dose of 1 X 10" cm-* at I50 keV and 350°C for 15-min anneal times with the dual dielectricSi,N,/SiO, anneal cap.

plants were less than 65 Q/sq. The integrated circuits produced for the MSI circuits described by Liechti et al. (1 98 1) employ a source-drain implant of 500-keV Si at dose of 1 X lOI3 cm-2 in the source and drain region in addition to the standard Se channel implant, 500 keV, 6 X loL2cm-2, to yield the doping profile shown in Fig. 30. The sheet resistance of this layer is 120 Q/sq. These results demonstrate that it is possible to routinely produce layers with sheet resistances less than 150 Q/sq using multienergy Si and/or multispecies implants and standard 850°C anneal procedures. The second application of high-dose implants, nonalloyed ohmic contact formation, has received increased attention over the last few years. The majority of this work has used transient annealing techniques, either e beam or laser beam, to activate the high-dose regions. The bibliography by Stevens (1978) contains references on the general topic of laser processing of semiconductorsprior to 1979. The investigationsat Lincoln Laboratories(Fan et al., 1979) and Hughes (Anderson et al., 1980) using cw irradiation indicated that the use of cw laser annealing of the implanted region was not promising.

2.

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a z I 0

z

1017

I

I

10'6

I

1

I

1.o

0.5

0

d (pm)

FIG.28. Camer concentration profiles measured by the differential Hall technique for Se and Se Ga implants into high-purity bulk substrates to a dose of 1 X 10l6cm-2 for each species at an energy of 200 keV, annealed at 1000°Cfor 15 min using a SiO, anneal cap. (Data supplied courtesy of Stoneham ef al., 1980.)

+

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BUFFER LPE

2 6 4 Si -+ GaAr

2 10'6-

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1

I

HIGH-PURITY BULK

-

-

140

C. A. STOLTE

So + Si --t GaAs

10'6' 0

I

0.1

I

0.2

I

0.3

I

0.4

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0.5

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0.6

0.7

0.8

I 0.9

1.0

d (run)

FIG.30. Camer concentration profile for dual species Se, 6 X lo1*cm-* at 500 keV, and Si, I X loi3cm-2 at 500 keV, implants, annealed at 850°C for I5 min using a Si,N, cap.

This is due to the narrow range of parameters over which reasonable dopant activation occurs without severe surface damage. Transient anneal techniques that result in good activation of the highdose implants employ Q-switched lasers (Barnes et af.,1978; Pianetta et af., 1980a; Sealy et af.,1978)or a pulsed e beam (Mozzi et af.,1979;Pianetta et af.,1980b) to produce short bursts of energy in the 0.5 - 1.O-J-cm-* range. The short burst of radiation melts a thin layer, less than 0.4 pm at the GaAs surface. This melt duration of less than 300 nsec is followed by a rapid regrowth of the GaAs. During the rapid regrowth, 85% of the implanted species is incorporated into the lattice, as demonstrated by RBS measurements using Te as the implant species (Amano et af., 1980); electrical measurements indicate that 20% of the implanted Te is activated. This low activation is accompanied by a mobility that is low by a factor of aproximately 2 compared to the value expected at the measured dopant concentration. It is possible to activate high-dose implants of Te, Se, Si, and Sn using either a pulsed e beam or a Q-switched ruby laser anneal technique. Typical results obtained using a pulsed e beam are shown in Table VI (Pianetta et al., 1980a), where the results for high-dose Se implants are shown. As indicated, the sheet resistance is less than 50 n/sqand, more importantly, the surface carrier concentration, measured using the differential van der Pauw method, is greater than 1 X 1019~ m - ~other ; samples have had surface concentrations as high as 6 X loL9~ m - The ~ . high values of surface carrier concentration have been verified by measuring the contact resistance of unalloyed metal contacts on the laser annealed layers that were formed by

2.

141

ION IMPLANTATION A N D MATERIALS

TABLE VI ELECTRICAL AND ALUMINUM CONTACT PROPERTIES OF GAASTRANSIENT ANNEALED LAYERS ~

van der Pauw Implant conditions

TLM

(Qlsq)

n, (cm-2)

n at surface (~m-~)

Pattern number

(Q/sq)

(Qcm2)

35

9.1 X 1014

> 2 X lOI9

1

39.6

5.8 X 10”

2

48.6

2.3 X lod

3

30.8

5.5 X 104

4

42.1

5.4 X lo4

PS

p,

rc

~

5 X lOI5 cm-2

250-keV Se

5

x loi5cm-2 50-keV Se

43

5.3 X loi4

> I X 1019

the evaporation of metal contacts at room temperature. The values in Table VI are in agreement with those predicted by the theory of Chang et al. ( 1971) assuming a bamer height of 0.6 eV and the measured surface concentration. Layers with contact resistances as low as 2 X 1O-’ IR cm2have been obtained using nonalloyed CrAu contacts to high-dose laser annealed GaAs. The sheet camer concentrationdecreases rapidly during post-laser anneal heat treatments, as illustrated in Fig. 3 1 for the case of high-dose Te implants

FIG. 3 1. The change in the sheet camer concentration as a function of the post-laser anneal isochronal heat treatment for a Te implant into an LPE buffer layer to a dose of 5 X IOl5 cm-2 at 250 keV.

142

C. A. STOLTE

into GaAs (Pianetta et al., 1980a). The stability of the carrier concentration of these layers has been investigated (Amano et al., 1980; Pianetta et al., 1981) to aid in the understanding of the anneal process. There is a two-step decrease in carrier concentration during the isochronal anneal following laser annealing. The first rapid drop is not accompanied by a major change in the lattice site occupancy of the implanted species in spite of the large decrease in the carrier concentration. The activation energy of the first step is 1.3 eV, suggesting a vacancy diffusion mechanism. The second decrease beyond 500°Cis accompanied by a decrease in the Te occupancy on lattice sites and the formation of dislocation loops and Ga,Te3 precipitates (Pianetta et al., 1981). The practical implications of this lack of thermal stability of the carrier concentration have been investigated in the laboratory by Pianetta. Results of that investigation are presented in Fig. 32, where the sheet carrier concentration N,, the sheet resistance ps, and the contact resistance R, are plotted as a function of time during a 250°C stability test. The contact

2x10" 10-6 G-

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10-7

t

101 0

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200

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400

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600

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800

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1000

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1200

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TIME Ihr I FIG.32. The change in the sheet camer concentrationN,, the contact resistanceR,, and the sheet resistance p,, as a function of time at 250°C for a ruby laser annealed sample implanted with Se in LPE buffer material to a dose of 5 X lOI5 cm-* at 250 keV.

2.

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143

resistance changes rapidly for short times and then increases with a time constant of about 5000 hr. This stability is better than that reported for e-beam annealed AuGe-Pt ohmic contacts (Lee et al., 1981). The values of contact resistance, maintained during the heat treatment, taken with the lOO-Q/sq value for the sheet resistance, indicate that these contacts would be acceptable for MESFET applications. To apply the laser mneal technique to the fabrication of circuits, it is necessary to laser anneal the contact regions selectively while protecting the channel regions. The laser annealing of channel region implants produces very high-resistivity regions due to a large defect density produced during the rapid regrowth during the laser anneal process. The techniques for selective laser annealing have been investigated in these laboratories. The procedure developed to provide this selective anneal uses an A1 mask to reflect the incident laser radiation to protect the quality of the channel regions. MESFETs employing selectively laser annealed source-drain nonalloyed contacts have been fabricated. The dc characteristicsof these devices are comparable to devices fabricated using standard alloyed ohmic contacts. The long-term stability of these devices is under investigation.

IV. Device Results 9. IC FABRICATION The materials and implantation technology described have been used to produce GaAs ICs of true MSI complexity. Examples of these circuits are the pseudorandom-bit-sequence generator (PRBS) (Fig. 33) operating at 2.5-Gbit/sec (Liechti et al., 1982b) and the MSI word generator (Fig. I), which operates at data rates as high as 5 Gbit/sec (Liechti et at., 1982a). These circuits employ selective ion implantation into high-purity LPE buffer layers, grown on Cr-doped substrates or grown on high-purity substrates, or implants directly into high-purity substrates. Figure 34 shows cross sections of a transistor, a diode, and interconnectionsas implemented in these circuits. Figure 35 illustrates schematically the process steps used in the fabrication of the ICs. The MESFET channel is formed by selective ion implantation of 500-keV Se ions into the substrate (heated to 350OC) to a dose of 6 X 10l2 cm-2 using an 0.8-pm-thick A1 mask to define the implanted regions. The substrates are implanted bare; no through-dielectric implants are used. A second selective Si ion implant is used in addition to the Se implant in the active area of diodes and under the ohmic contact regions of the transistors to lower the sheet resistance. For this purpose, Si is implanted at 500 keV to a dose of 1 X lOI3 cm-2 using an A1 mask with the substrate at room

144

C. A. STOLTE

FIG. 33. Photomicrograph of the 2.5-GHz PRBS generator. The chip measures 1 . 1 X 1 . 1 mrn and contains 400 MESFETS and 150 Schottky diodes.

S

0

,,

A

C

2.

ION IMPLANTATION AND MATERIALS

145

GaAs f UNDOPED SUBSTRATE

I

@

r

N-

Cr-Pt-Au-Ni

r-l

GATE CONTACT

I

T ,

,

SiO2 LAYER

I

y Ti-Pt-Au

FIG.35. Process steps used for the fabrication of the GaAs circuits shown in Figs. 1 and 33. The details of the fabrication process are discussed in the text.

temperature. After removal of the A1 mask, both implants are simultaneously annealed at 850°C for 15 min using the Si3N4cap. The resultant doping profile under the gate is shown in Fig. 11; this region has sheet resistance of 325 O / q . The dual species, Se plus Si, implant region profile is shown in Fig. 30. This region has a sheet resistance of 120 O/sq. The ohmic contacts used are processed in a conventional way by a multilayer evaporation of NiCr, Au, Ge, and Au, lifting of the excess metal outside the contact patterns, surface capping, and alloying. The resulting specific contact resistance is typically 2 X 10” $2cm2, and the sheet resist-

146

C. A. STOLTE

ance of the alloyed Au-Ge metal film is 1.3 n/sq.As indicated, ohmic and Schottky contacts have been produced during the same fabrication step by use of the very high doping concentration layers produced by laser annealing of high-dose implants. Laser-annealed contacts have not been used in the fabrication of the ICs described here. The gate processing step is by far the most crucial part of the processing sequence used to produce the integrated circuits. Here, high resolution is required in the lithography of thousands of l-pm gate lines printed on the wafer. This is a very complex procedure which, in summary, is as follows: The gate lines are fabricated by lifting evaporated metal with a combination of two positive resist layers. Prior to the gate-metal evaporation, the channel region is precisely etched to a depth of 0.12 pm,leaving a gate trench above the FET channel. This trench lowers the level of the Schottky contact below the unpassivated GaAs surface. This gate geometry yields a lower series resistance of the source and drain compared to a planar structure with the same gate-cutoff voltage. It also reduces the modulation of the drain current due to changing depletion layer widths at the free surface during switching transients. Finally, it allows adjustment of the gate-cutoff voltage during processing. The circuits are completed by an intermetal dielectric deposition, via patterning, and the deposition and patterning of the second metal. The circuits processed as described above, e.g., the PRBS circuit shown in Fig. 33, have a 30% functional yield. This process technology differs in some fundamental ways from that used at Rockwell International (Welch et al., 1980). In the Rockwell process they implant through a Si,N, dielectric layer and maintain that passivation throughout the process, except for metallization regions. They do not use the recessed gate process and therefore rely on a well-defined materials characterization and implant control to provide the needed control of the device parameters. This has produced a high-performance 8 X 8 multiplexer circuit that contains over 1000gates on a 2.7 X 2.25-mm chip (Lee et a/., 1980). 10. IC PERFORMANCE The 5-Gbit/sec GaAs word generator IC shown in Fig. 1 consistsofan 8 : 1 parallel-to-serial converter, timing generator, control logic, and emitter coupled logic (ECL) interface networks. The circuit generates multiple 8-bit words whose number can be dynamically controlled. In the circuit, data from eight parallel input channels are amplified and applied to a tree of 2 : 1 multiplexers that connects the eight inputs to a single output in a time-multiplexed sequence. The key featuresof the 2 : 1 GaAs multiplexer used in the circuit are its speed and its capability of generating clean waveforms with fast transition times. Even at a 5-Gbit/sec data rate, the circuit is perfectly

2.

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stable; the waveforms are very clean, with no glitches and with negligible overshoot, ringing, and time jitter. The voltage rises and falls with 100-psec transition times. By changing the clock frequency, the output data can be varied from 1 kbitlsec up to 5 Gbitlsec while maintaining perfect stability at all frequencies. This circuit is described in detail by Liechti et al. (1982a). The PRBS generator (Fig. 33) is based on a 10-stage shift register whose seventh- and tenth-stage outputs are fed back to the first-stage input via an exclusive OR gate. The circuit generates the maximum-length sequence of 1023bits. The shift register stages are complementary-clockedmaster - slave flip-flops. The 10-stage PRBS generator operates in a stable and reliable mode for clock frequencies ranging from several kHz out to 2.5 GHz. Transition times of the pulses generated are 1 10 psec, and the output voltage swing into 50 R is 1 V. The waveforms generated by this circuit are shown in Fig. 36. For a detailed discussion of this circuit, see Liechti et al. (1982b). These circuits all use buffered FET logic (BFL),which allows the maximum speed of operation for a given geometry, e.g., a propagation delay, measured with a 5-stage ring oscillator, of 56 psec for a fan out of one with a power dissipation of 15 mW/stage, power - speed product equal to 850 f J/gate. Additional information on the design, fabrication, and operation of these and other digital IC circuits is contained in the report by Liechti et al. (1982~). The 8 X 8 multiplier circuit fabricated at Rockwell International (Lee et al., 1982b) has a multiplier speed of 5.3 nsec. The gate circuits used in this

c:

0 Ul

PRBS (2,5 Gbit /sec)

SYNC. PULSE

TIME (2 nseddiv) FIG.36. Output waveforms of the synchronization pulse (bottom) and PRBS at 2.5-Gbit/sec

data rate (top).

148

C. A. STOLTE

circuit have a propagation delay of 150 psec and a speed- power product of which 3 10 fJ/gate. This circuit employs Schottky-diodeFET logic (SDFL), operates a lower-power dissipation and requires less total gate area than BFL (Eden et al., 1979). This decrease in power dissipation is offset by the increase in the propagation delay for this type logic, as presented in Lehovec and Zuleeg (1980). Analog monolithic GaAs ICs have been fabricated, which operate in the gigahertz frequency range, including a 4-GHz amplifier (Van Tuyl, 1978), a 4-GHz frequency divider (Van Tuyl et al., 1977), and a 1.5-GHz signal generator (Van Tuyl, 1980). The review article by Bosch (1 979) contains a review of GaAs microwave devices and an extensive list of references on this topic. 1 1. BACKGATING

One of the problems encountered in the design, fabrication, and successful reduction to practice of complex circuits has been the phenomenon of backgating (Itoh and Yanai, 1980; Kitahara et al., 1980; Immorlica et al., 1980). This effect can be described as a change in the drain current of a MESFET caused by the application of a negative potential on a pad in the vicinity of the transistor (Bimttella et al., 1982). The effect is caused by a change in the depletion width of the channel, which is not controlled by the gate on the surface of the channel region but by a space-chargelayer (Hower et al., 1969)present at the interface between the active layer (the implanted channel region) and the substrate material. The degree of backgating typically varies with location on a single wafer and changes from wafer to wafer. This variation results in major problems in circuit design due to the uncertainty of the source-drain current under different circuit bias conditions. It has been demonstrated by Kocot and Stolte (1982) that backgating is caused by an excess negative charge on the substrate side of the interface between the active layer and the semi-insulating substrate and a corresponding net positive charge on the active layer side. The origin of these charges is illustrated in Fig. 37, where the band diagram for Cr-doped and for high-purity substrates is shown. In the case of high-purity material, the deep level is the EL2 electron trap. In the bulk region remote from the interface, the EL2 level is partially ionized since the Fermi level is near mid-gap and slightly above the trap level, as required for the material to be semi-insulating. In the region of the interface, the EL2 level traps electrons from the shallow donors in the active layer and therefore produces a negative charge region in the substrate, which induces a positive charge layer in the active region as shown in Fig. 37. It is this space-chargeregion that is modulated to reduce the drain current when a negative voltage is applied to the back side of the channel. The case for the Cr-doped material is similar; in this case, the Cr level, a

2.

ION IMPLANTATION A N D MATERIALS

149

SPACE CHARGEREGION

--

SUBSTRATE

I

I

-

I+ 1

I 1

IMPLANTED ACTIVE LAYER

CrZ+

-&-*-&*&-&-A&-

F.L. -&I--L-*.L--cI-A EL 2

V.B.

II

I

I

I

I

I 1I

I

t

1

FIG.37. Band diagram for the backchannel region of a MESFET illustratingthe origin ofthe space charge region responsible for the phenomenon of backgating.

deep hole trap, is only partially occupied in the bulk; therefore, in the interface region, electrons are captured by the Cr2+level to form a negative space-charge region in the substrate and the positive region in the active layer. In the case of buffer layers on either kind of substrate material, the same model holds except that the electrons that fill the traps originate in the buffer layer and produce a much wider depletion width. The use of buffer layers will reduce the magnitude of backgating, but if the depletion layer in the buffer reaches the active layer under the biased condition, the devices will still show backgating. The conductance deep-level transient spectroscopy (DLTS) technique (Borsuk and Swanson, 1980; Alderstein, 1976) has been used in our investigations to analyze the long-time constant change of the source-drain current following the application of a negative backgate bias. The levels detected in these experiments are consistent with the activation energiesand capture cross sections reported in the literature for these levels (Martin, 1980). This technique is being used in the continuing investigation of the phenomenon of backgating. Measurements of the spectral response of the source-drain current with a backgate bias also support the model and, in addition, explain the light sensitivity observed. The type of substrate material used and the concentration of deep traps will determine the magnitude and the spectral dependence of backgating. The data of Fig. 38, obtained by Diesel et al. (1980), show the dependence of the back-side channel-depletion width on the Cr concentration. These experimental data were obtained by measuringthe change in the width, A W, of the space-charge region, using the standard C- V profile technique, as a

150

C. A. STOLTE

25 x

0

0.5

1.0

1.5

2.0

2.5

3 . 0 10” ~

CHROMIUMCONCENTRETION (cm-3)

FIG.38. The change of the depletion width of the backchannel space charge region per volt of applied potential to the back side of the semi-insulatingsubstrate as a function of the Cr concentration in the substrate. (Data supplied courtesy of Diesel et al., 1980.)

function of a change of the back-side voltage A I/ on samples of different Cr concentration. A survey of the results obtained in different substrate material types is summarized in Fig. 39, where the average and standard deviation of the magnitude of backgating are presented. As predicted by the model, the buffer layer devices produced the least backgating, with the exception of the Cr-doped sample, which was chosen to be closely compensated to test the validity of the backgating model. The model predicts that if the substrate material is very closely compensated, the number of excess negative charges in the interface region between the active area and the substrate will be very small. In this case, no appreciable space-charge region will be present at the interface, and hence the backgating effect will be small. This has been experimentally verified (Kocot and Stolte, 1982), and additional experiments are in progress to further evaluate the effect of closely compensated material. The magnitude of backgating has been reduced by DAvanzo (1982) through the use of proton-bombardment isolation in the insulating regions of the circuits. The proton bombardment improved the isolation between components of circuits produced by direct implantation into high-purity material and, as an additional effect, decreased the magnitude of backgating. This reduction of backgating is interpreted to be the result of decreasing the

2. ISD 2 mA @Vs=OV

> ? "

-2 a

I

1.2

-

1.0

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0.8

-

0.6

-

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0.2

-

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HIGH PURITY

BUFFER ON CR

CR

0.4 -

0

151

ION IMPLANTATION AND MATERIALS

I 1

1 ~

It 1

1

1

1

1

1

1

1

1

1

1 I I I 1 1 1 l 1

UFFEP ON HIGH 'URITY

I

I I

SAMPLE NUMBER

FIG. 39. The change of the source-drain current as a result of the application of -4V potential applied 15 pm from a MESFET for the different substrate types indicated in the figure. The average value of the change measured for about 30 devices on each wafer is indicated by the point on the figure; the standard deviation of the measured values is indicated by the bars.

potential which appears at the back side of the channel for a given sidegate potential by changing the trap-fill-limit voltage (Lee et al., 1982a). The degree of backgating has been linked to the light sensitivity of the drain current by Diesel (1980). He showed that the light sensitivity was dependent on the Cr concentration in the same way as the magnitude of backgating. In addition, it is reasonable to expect that the effect of gain compression seen in high-power devices is related to the charging and slow emission from the deep traps in the substrate material. Other effects are observed in the performance of GaAs ICs. For example, lag effect and premature power saturation are dependent on the deep trap density in the substrate material (Immorlica et al., 1980)as well as by the effects of surface charging. These observations indicate that it is necessary, in addition to producing stable semi-insulating material, to control the presence and relative concentration of the deep traps in the substrate material. V. Summary

The work reported here has demonstrated the current state of the art in materials preparation and ion implantation technology required for the

152

C . A. STOLTE

production of MSI GaAs ICs. The materials technology has made great strides during the last four years; there is now available an ample supply of high-quality materials to provide the necessary starting materials for the further advancement of IC technology. In the area of ion implantation, the necessary techniques and procedures are available to allow the production of selectively implanted regions, with adequate quality and reproducibility to satisfy the needs of today’s ICs. The growing degree of complexity and the increased degree of integration, beyond the several hundred transistor level that is now being integrated on a chip, will require further improvementsin the materials and implantation technology. In the area of materials, the question of the importance of the dislocation density has not been resolved. Dislocations in the channel region could, for example, result in increased gate current leakage, a decrease in the gate breakdown voltage, and produce diffusion spikes of the implanted species during the anneal cycle. These effects will become increasingly important as the relative area of the channel region increases. It is expected that, as the density of the devices increases, it will be necessary to reduce the dislocation density from the 1 X lo4to 1 X 10s-cm-2range, which is now available by at least an order of magnitude in order to provide reasonable yields at higher integration levels. At the present time, it appears that the dislocation density is not the limiting factor on yield, but that can be expected to change in the future. Another requirement for the realization of large-scale integration (LSI) will be the availability of large, at least 76-mm diameter, wafers grown in the [ 1001direction, with an orientation flat, to allow the use of modem processing equipment. Wafers with these characteristics have been successfully pulled by several laboratories with the desired high purity (Thomas et al., Chapter 1, this volume; Kirkpatrick et al., Chapter 3, this volume). Additional concerns now being formulated are rapidly becoming firstorder effects rather than second-order effects. These problems include the influence of the starting material and the implant and processing procedures on the phenomena of backgating, noise, gain compression, light sensitivity, and the reliability of GaAs ICs. As the technology matures, these and other as yet unidentified problems will occupy the efforts of the research laboratories. In the past two years, great strides have been taken to increase the technology of GaAs ICs in all phases of its development: The production of improved quality material in quantities that will support the development efforts; the maturing of the implant and anneal technology to the point where it is more than a laboratory technology; and sophisticated IC design, where true MSI complexity circuits have been demonstrated with practical yields. Finally, the process technology necessary to produce these circuits has been demonstrated.

2.

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153

The MSI, < 1 X lo3 gate/chip, circuits described in this chapter were fabricated using depletion-mode MESFETs in BFL and in SDFL circuit configurations. The device structures and circuit types that can be used to extend the level of integration are described in detail in the articles by Eden et al. (1979), Eden (1 982), Lehovec and Zuleeg (1980), and Bosch (1980). It is generally agreed that the next step to LSI, 1 X lo3 to 1 X lo4gates/chip, can be accomplished using depletion mode MESFETs and SDFL when improvements in materials and active layer uniformity, which are well within the realm of possibility, are implemented. These circuits should operate in the 2 - 3-GHz/sec clock frequency range, lower than those demonstrated with BFL but with increased complexity. The use of enhancement mode MESFETs could increase the gate count into the very large-scale integration (VLSI)range, > 1 X lo4gates/chip, with clock frequencies greater than 1 GHz/sec. These devices will require a very stringent control of the doping profile in the active channel region in order to produce a totally depleted channel region for zero gate bias and still provide a good device transconductance for gate voltages less than about 0.5 V, the maximum gate voltage which can be applied without drawing excessivegate current. Another candidate for use in the VLSI regime is the enhancement mode junction field effect transistor (JFET). In this device, the channel-region doping is somewhat less stringent than the e-MESFET since the p - n junction characteristic allows a larger gate voltage swing. However, the investigations to date on this device have indicated problems with the control of the geometry of the device due to the lateral diffusion of the p-type dopant during the anneal cycle, in the case of implanted devices, or during the diffusion of the dopant for diffused junction devices (Dohsen et al., 1981). In order to penetrate the regime of VLSI complexity, there are several improvements which must be made. First, the materials used as substrates will have to have improved uniformity of electrical characteristics and improved dislocation densities. Second, the production of the n-type regions for enhancement mode MESFET devices or the p-type regions for JFET devices will require improved control of the doping profiles produced by ion implantation. In this area, alternate techniques such as organo-metallic vapor-phase epitaxy (OMVPE) and molecular beam epitaxy (MBE), with appropriate isolation techniques, will be evaluated as an alternative to ion implantation. Finally, the process techniques used to produce these complex circuits will have to be compatible with the materials and active-region - formation techniques in order to produce practical yields of functional circuits. It is the author’s judgment that the decade of the 1980s will see the practical production of GaAs circuits of LSI complexity operating with

154

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clock frequencies in the 2 - 3-GHz/sec range. The competition from smallgeometry Si devices (Lepselter, 1980, 1981)will be a factor in the high-speed LSI devices. However, the inherent advantagesofGaAs over Si, namely, the higher electron mobility and electron velocity at low fields and the availability of semi-insulating substrates, makes possible much higher switching speeds for GaAS ICs as compared to Si. The future for GaAs indeed looks bright, and we can look forward to the time when GaAs is no longer the material of the future but the material of the present. ACKNOWLEDGMENTS The author extends his thanks to his colleagues at Hewlett-Packard who contributed to the work reported in this chapter. In particular, to Grant Elliot, Bill Ford, and Dick Putback, who grew most of the substrate material used; to Simone Malcolm and Mane Amistoso, who grew and characterized the LPE buffer layers; to Jim Hansen, for his expertise in ion implantation; and to Vibeke Bitsch and Jessie Kafia for the processing of samples. The inclusion of results supplied by Ed Stoneham, Chris Kocot, Piero Pianetta, and Joe Diesel added to the breadth of the chapter content and is acknowledged. The excellentcooperation of Charles Liechti and his IC group, including Elmer Gowen, Ruth Noll, Ruth Devereaux, Rod Lanick, and Falke Hennig has aided in all phases of the work reported. The substrate materials supplied by Ed Swiggard of Naval Research Laboratory, Roland Ware of Metals Research, and Ian Sanders of Plessey Research (Caswell) Ltd. increased the scope of the materials evaluation. The enthusiastic support during the course of these investigations,the useful and stimulating discussions, and the constructive comments regarding the content of this chapter by Bob Archer, Charles Bittmann, and Charles Liechti are appreciated and acknowledged. Finally, the assistance by Soyla Ybarra and JoAnn Hill in the preparation of the illustrations and the manuscript is appreciated.

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