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Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications
Microelectronic Engineering 86 (2009) 1692–1695
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Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications Chien-Wei Liu a, Chin-Lung Cheng b,*, Kuei-Shu Chang-Liao c,*, Jin-Tsong Jeng d, Bau-Tong Dai a, Chen-Pang Tsai b a
National Nano Device Laboratories, Tainan 74147, Taiwan, ROC Institute of Mechanical and Electro-Mechanical Engineering, National Formosa University, Huwei, Yunlin 63201, Taiwan, ROC c Department of Engineering and System Science, National Tsing Hua University, 101, Sec. 2, Kuang-Fu Rd., Hsinchu 30013, Taiwan, ROC d Department of Computer Science and Information Engineering, National Formosa University, Huwei, Yunlin 63201, Taiwan, ROC b
a r t i c l e
i n f o
Article history: Received 3 March 2009 Received in revised form 4 March 2009 Accepted 4 March 2009 Available online 11 March 2009 Keywords: Nanoparticles TiOxNy HfOxNy Charge trapping nodes Nonvolatile memory devices
a b s t r a c t Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiOxNy metal oxide NPs embedded in the HfOxNy high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O2/N2 ambient. Well-isolated TiOxNy NPs with a diameter of 5–20 nm, a surface density of 3 1011 cm 2, and a charge trap density of around 2.33 1012 cm 2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction Silicon-oxide–nitride-oxide–silicon (SONOS) device with the nanoparticles (NPs) as charge trapping nodes (CTNs) is a promising candidate to provide enhanced device performance [1–6]. Recently, significant researches, such as CdSe, CoxMoyO, CoxNiyO, Si, Pt, Au, Co, TiSi2, and Ni1 xFex NPs, have been demonstrated to meet the urgent need of the CTNs for advanced nonvolatile memory (NVM) device applications [1–13]. The silicon NPs with average size of 5 nm and density of 2 1012 cm 2 embedded in the Gd2O3 exhibit charge storage capacity with promising retention (107 s) and endurance (105 write/erase cycles) characteristics [1]. The reduced CoxMoyO bimetallic oxide nanoparticles (BONPs) with a charge trap density (CTD) of 1.1 1012 cm 2 and a flatband voltage shift (DVfb) of 700 mV embedded in the HfON high-k dielectric have been developed by means of the chemical vapor deposition (CVD) method [3]. The work compares CoxMoyO, CoxFeyO and FexMoyO BONPs that were individually embedded in HfOxNy high-k dielectric as CTNs [5]. The CoxNiyO BONPs with a CTD of 8.96 1011 cm 2 and a DVfb of 500 mV embedded in the HfOxNy high-k dielectric as CTN of the
* Corresponding authors. Tel.: +886 5 6315396; fax: +886 5 6315397 (C.-L. Cheng), tel.: +886 3 5742674; fax: +886 3 5720724 (K.-S. Chang-Liao). E-mail addresses: [email protected] (C.-L. Cheng), [email protected] (K.-S. Chang-Liao). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.032
NVM devices have been formed via the CVD using the Co/Ni acetate calcined and reduced in the Ar/NH3 ambient [7]. Self-assembled cobalt nanocrystals with around 3–4 nm in diameter and the dot density of about 1 1012 cm 2 embedded in the SiO2 dielectric were achieved by in situ annealing Co ultrathin films [11]. Compared with Si nanocrystal in memory devices, the TiSi2 NPs with a dot diameter of around 13 nm and a dot density of around 5 1011 cm 2 as the CTNs in the NVM devices show higher writing saturation level, faster writing/erasing speed, longer retention, and larger memory window [12]. Self-assembled Ni1 xFex NP arrays with a 4–6 nm thickness and a DVfb of 2 V were periodically inserted in the polyimide layers [13]. Additionally, the metal gate and the high-dielectric-constant (high-k) gate oxides with identical equivalent-oxide thickness (EOT) are promising for reducing the gate tunneling leakage current in advanced metal-oxide-semiconductor (MOS) devices applications [14–19]. Therefore, NPs embedded in the high-k gate dielectric are attractive technological options for NVM device applications. Thus, a considerable investigation on the TiOxNy NPs embedded in HfON high-k dielectric will be addressed in this work. 2. Experimental details Metal-oxide-semiconductor (MOS) capacitors with and without TiOxNy NPs as CTN were fabricated. Prior to HfON deposition, all
C.-W. Liu et al. / Microelectronic Engineering 86 (2009) 1692–1695
wafers were cleaned by a wet cleaning process (APM/HPM/DHF). The process used an NH4OH/H2O2/H2O mixture (APM) in a ratio of 1:4:20 (volume) at 75 °C and an HCl/H2O2/H2O mixture (HPM) in a ratio of 1:1:6 (volume) at 75 °C to remove residues and contaminants. The dipping time in all processes was 10 min. Diluted HF (DHF) with HF and H2O in a ratio of 1:100 (volume) was used to remove native oxide. Following the wet processes, all wafers were rinsed with deionized water for 10 min. The HfON tunneling dielectric with EOT of the 1.8 nm thicknesses was thermally evaporated on the cleaned N-type Si (1 0 0) substrates. Next, a Ti with 1 nm thickness was deposited on the surface of the HfON/Si stacked substrate. Then, the Ti/HfON/Si stacked structure was performed at 600 °C for 10 min in a mixed O2/N2 = 1.5/3.0 SLM ambient to form TiOxNy NPs. Subsequently, the HfON dielectric with an EOT of 7.0 nm was deposited onto the top surface of the TiOxNy/ HfON/Si stacked structure to serve as the blocking oxide. The metal gate electrodes with 500 nm Al film were deposited via a sputtering and were patterned by a liftoff technique. The backsides of all samples were also deposited with a 500 nm thick Al film by thermal evaporation following the oxide stripping. Finally, a sintering was conducted in a N2/H2 ambient at 420 °C for 30 min. The morphology analyses were performed by scanning electron microscopy (SEM). The capacitance–voltage (C–V) measured by an HP 4284A precision LCR meter and a bipolar pulse train from a HP 81110A pulse generator were performed to study the charging and discharging effects of the TiOxNy NPs. 3. Results and discussion To investigate the charge trapping characteristics of the MOS devices due to the TiOxNy NPs, the typical C–V hysteresis sweep of the MOS devices with and without the TiOxNy NPs were investigated as shown in Fig. 1. Fig. 1 shows that no clear hysteresis shift between the forward (from inversion to accumulation) and the reverse (from accumulation to inversion) C–V curve is observed for the sample without TiOxNy NPs under 7 to +7 V sweep. The hysteresis-free C–V in the MOS device without TiOxNy NPs confirms the quality of the gate oxide. On the contrary, the DVfb of 1.2 V was obtained for the TiOxNy NPs sample. Therefore, it is concluded that the memory effect mainly results from charge injection into the TiOxNy NPs. The capacitance of the MOS device without TiOxNy NPs is larger than that of the MOS device with TiOxNy NPs ones due to thin HfON/NPs/HfON stacked dielectrics. Moreover, the charge trapping in the dielectric bulk is responsible for the DVfb of the
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MOS device. Therefore, Fig. 1 suggests that the DVfb can be achieved by the TiOxNy NPs embedded in the HfON high-k dielectrics. In addition, compared to without TiOxNy NPs sample, the C– V curves of the TiOxNy NPs sample shift to the left, indicating that the positive charges (hole trapping) are generated in the gate dielectric bulk due to the TiOxNy NPs as CTLs of the NVM devices. Fig. 2 shows the morphology of the TiOxNy NPs detected by SEM. The SEM image in Fig. 2 displays that the TiOxNy NPs with a diameter of around 5–20 nm and a surface density of 3 1011 cm 2 were obtained. To estimate the CTD of the TiOxNy NPs, the following equation was adopted: N = (Ceff/qA) DVfb, where Ceff is the capacitance of the MOS devices with the HfON/TiOxNy/HfON stack dielectric, q is the electronic charge and equal to 1.6 10 19 C, and A is the area of the MOS devices [10]. For the MOS devices with Ceff = 610 pF, A = 0.001963 cm2, and DVfb = 1.2 V, the CTD is estimated to be around 2.33 1012 cm 2 under 7 to +7 V sweep. According to the CTD measured under 7 to +7 V sweep, the average charge collection in each TiOxNy NPs can be estimated around 7.8 electrons or equivalent hole charges. The results shown in Fig. 1 suggest that the flatband voltage has a left shift, indicating that holes are easy to be trapped into the TiOxNy NPs. Since the mechanism is mainly resulted from the hole trapping, the program/erase speed of the devices with the TiOxNy NPs was addressed and shown in Fig. 3. During a positive biased at the control gate, the electrons directly tunnel from the Si substrate through the HfON tunnel oxide, and they are trapped in TiOxNy NPs. On the contrary, as a negative biased at the control gate, the holes are injected into TiOxNy NPs or the electrons detrap back to the Si substrate. The substrate is in depletion when the substrate was biased at small negative voltage. The holes are not easily trapped into NPs. Therefore, during writing operations in this work, the memory devices with the TiOxNy NPs under various writing times (WTs) were biased at a 10 V resulting in inversion layer in the substrate. With a Vprogram at 10 V, a 1 ms speed programming performance can be achieved with a memory window of about 1 V as shown in Fig. 3a. Erase properties of the MOS devices with TiOxNy NPs under various programming times by +10 V were shown in Fig. 3b. An erase speed of around 100 ls can be obtained. Compared with program speed, the MOS devices with TiOxNy NPs have a much faster erasing speed.
Sweep loop: -7V to +7V then +7V to -7V
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Fig. 2. The morphology of the TiOxNy NPs detected by SEM. The CTD in TiOxNy NPs was extracted from N = (Ceff/qA) DVfb, where Ceff is the capacitance of the MOS devices with the HfON/TiOxNy/HfON stacked dielectric, q is the electronic charge and equals 1.6 10 19 C, A is the area of the MOS devices, and DVfb is the flatband voltage shift due to hysteresis sweep.
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Time (s) Fig. 3. (a) Program properties of the MOS devices with the TiOxNy NPs under various program times by 10 V. (b) Erase properties of the MOS devices with the TiOxNy NPs under various programming times by +10 V.
The charge retention tests of the memory devices with TiOxNy NPs using ±5 V, respectively, programming voltages were performed at room temperature. The capacitance variations as the function of the retention times after the electron or hole injection were shown in Fig. 4. The capacitance variation (C/C0) biased near flatband voltage indicates DVfb. The variation of the flatband voltage in MOS device is as the following equation: Vfb = ums Qtotal/ Cox, where ums is the difference of the work function between the gate electrode and the Si substrate, Qtotal is the charge in the dielectric, and Cox is the capacitance of dielectric. Therefore, the
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variations of the capacitance indicate the DVfb resulting in threshold voltage shift. The results of Fig. 4 show that the memory window was stable during hole injection. Moreover, the programmed holes have a longer retention time than the electrons because they have a larger effective mass [20]. In this work, the NVM device programmed by hole injection has better the retention characteristics than the NVM device programmed by electron injection. The results are consistent with researches report [20]. Fig. 5 shows endurance characteristics of the MOS devices with the TiOxNy NPs using ±3, ±5 and ±10 V as the erase/programming voltages, respectively, performed at room temperature. The endurance properties after 106 P/E cycles were shown. The results suggest that a 30% memory window narrowing after 106 P/E cycles was demonstrated by performing at ±10 V P/E for 100 ms. Thus, the TiOxNy NPs embedded in the HfON high-k dielectric as charge trapping nodes due to the hole trapping mechanism are promising candidate for the advanced NVM device applications.
4. Conclusions The memory characteristics of the TiOxNy nanoparticles embedded in the HfOxNy as charge trapping nodes of the nonvolatile memory devices were investigated. Based on the C–V curve measurement and the morphology detected by SEM, the TiOxNy NPs with a diameter of 520 nm, a surface density of 3 1011 cm 2, and the charge trap density of around 2.33 1012 cm 2 were obtained. The TiOxNy NPs embedded in the HfON high-k dielectric as charge trapping nodes due to the hole trapping mechanism are promising candidate for the advanced NVM device applications.
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Acknowledgments
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The authors would like to thank the National Science Council of the Republic of China for the financial support under Contract Nos. NSC 96-2221-E-492-012-MY3, NSC 97-2221-E-150-072 and NSC 96-2221-E-150-070-MY3. Technical support from National Nano Device Laboratories (NDL) of the ROC is also acknowledged.
Bias at Vg=0.4V near flatband voltage
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Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications Chien-Wei Liu a, Chin-Lung Cheng b,*, Kuei-Shu Chang-Liao c,*, Jin-Tsong Jeng d, Bau-Tong Dai a, Chen-Pang Tsai b a
National Nano Device Laboratories, Tainan 74147, Taiwan, ROC Institute of Mechanical and Electro-Mechanical Engineering, National Formosa University, Huwei, Yunlin 63201, Taiwan, ROC c Department of Engineering and System Science, National Tsing Hua University, 101, Sec. 2, Kuang-Fu Rd., Hsinchu 30013, Taiwan, ROC d Department of Computer Science and Information Engineering, National Formosa University, Huwei, Yunlin 63201, Taiwan, ROC b
a r t i c l e
i n f o
Article history: Received 3 March 2009 Received in revised form 4 March 2009 Accepted 4 March 2009 Available online 11 March 2009 Keywords: Nanoparticles TiOxNy HfOxNy Charge trapping nodes Nonvolatile memory devices
a b s t r a c t Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiOxNy metal oxide NPs embedded in the HfOxNy high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O2/N2 ambient. Well-isolated TiOxNy NPs with a diameter of 5–20 nm, a surface density of 3 1011 cm 2, and a charge trap density of around 2.33 1012 cm 2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction Silicon-oxide–nitride-oxide–silicon (SONOS) device with the nanoparticles (NPs) as charge trapping nodes (CTNs) is a promising candidate to provide enhanced device performance [1–6]. Recently, significant researches, such as CdSe, CoxMoyO, CoxNiyO, Si, Pt, Au, Co, TiSi2, and Ni1 xFex NPs, have been demonstrated to meet the urgent need of the CTNs for advanced nonvolatile memory (NVM) device applications [1–13]. The silicon NPs with average size of 5 nm and density of 2 1012 cm 2 embedded in the Gd2O3 exhibit charge storage capacity with promising retention (107 s) and endurance (105 write/erase cycles) characteristics [1]. The reduced CoxMoyO bimetallic oxide nanoparticles (BONPs) with a charge trap density (CTD) of 1.1 1012 cm 2 and a flatband voltage shift (DVfb) of 700 mV embedded in the HfON high-k dielectric have been developed by means of the chemical vapor deposition (CVD) method [3]. The work compares CoxMoyO, CoxFeyO and FexMoyO BONPs that were individually embedded in HfOxNy high-k dielectric as CTNs [5]. The CoxNiyO BONPs with a CTD of 8.96 1011 cm 2 and a DVfb of 500 mV embedded in the HfOxNy high-k dielectric as CTN of the
* Corresponding authors. Tel.: +886 5 6315396; fax: +886 5 6315397 (C.-L. Cheng), tel.: +886 3 5742674; fax: +886 3 5720724 (K.-S. Chang-Liao). E-mail addresses: [email protected] (C.-L. Cheng), [email protected] (K.-S. Chang-Liao). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.032
NVM devices have been formed via the CVD using the Co/Ni acetate calcined and reduced in the Ar/NH3 ambient [7]. Self-assembled cobalt nanocrystals with around 3–4 nm in diameter and the dot density of about 1 1012 cm 2 embedded in the SiO2 dielectric were achieved by in situ annealing Co ultrathin films [11]. Compared with Si nanocrystal in memory devices, the TiSi2 NPs with a dot diameter of around 13 nm and a dot density of around 5 1011 cm 2 as the CTNs in the NVM devices show higher writing saturation level, faster writing/erasing speed, longer retention, and larger memory window [12]. Self-assembled Ni1 xFex NP arrays with a 4–6 nm thickness and a DVfb of 2 V were periodically inserted in the polyimide layers [13]. Additionally, the metal gate and the high-dielectric-constant (high-k) gate oxides with identical equivalent-oxide thickness (EOT) are promising for reducing the gate tunneling leakage current in advanced metal-oxide-semiconductor (MOS) devices applications [14–19]. Therefore, NPs embedded in the high-k gate dielectric are attractive technological options for NVM device applications. Thus, a considerable investigation on the TiOxNy NPs embedded in HfON high-k dielectric will be addressed in this work. 2. Experimental details Metal-oxide-semiconductor (MOS) capacitors with and without TiOxNy NPs as CTN were fabricated. Prior to HfON deposition, all
C.-W. Liu et al. / Microelectronic Engineering 86 (2009) 1692–1695
wafers were cleaned by a wet cleaning process (APM/HPM/DHF). The process used an NH4OH/H2O2/H2O mixture (APM) in a ratio of 1:4:20 (volume) at 75 °C and an HCl/H2O2/H2O mixture (HPM) in a ratio of 1:1:6 (volume) at 75 °C to remove residues and contaminants. The dipping time in all processes was 10 min. Diluted HF (DHF) with HF and H2O in a ratio of 1:100 (volume) was used to remove native oxide. Following the wet processes, all wafers were rinsed with deionized water for 10 min. The HfON tunneling dielectric with EOT of the 1.8 nm thicknesses was thermally evaporated on the cleaned N-type Si (1 0 0) substrates. Next, a Ti with 1 nm thickness was deposited on the surface of the HfON/Si stacked substrate. Then, the Ti/HfON/Si stacked structure was performed at 600 °C for 10 min in a mixed O2/N2 = 1.5/3.0 SLM ambient to form TiOxNy NPs. Subsequently, the HfON dielectric with an EOT of 7.0 nm was deposited onto the top surface of the TiOxNy/ HfON/Si stacked structure to serve as the blocking oxide. The metal gate electrodes with 500 nm Al film were deposited via a sputtering and were patterned by a liftoff technique. The backsides of all samples were also deposited with a 500 nm thick Al film by thermal evaporation following the oxide stripping. Finally, a sintering was conducted in a N2/H2 ambient at 420 °C for 30 min. The morphology analyses were performed by scanning electron microscopy (SEM). The capacitance–voltage (C–V) measured by an HP 4284A precision LCR meter and a bipolar pulse train from a HP 81110A pulse generator were performed to study the charging and discharging effects of the TiOxNy NPs. 3. Results and discussion To investigate the charge trapping characteristics of the MOS devices due to the TiOxNy NPs, the typical C–V hysteresis sweep of the MOS devices with and without the TiOxNy NPs were investigated as shown in Fig. 1. Fig. 1 shows that no clear hysteresis shift between the forward (from inversion to accumulation) and the reverse (from accumulation to inversion) C–V curve is observed for the sample without TiOxNy NPs under 7 to +7 V sweep. The hysteresis-free C–V in the MOS device without TiOxNy NPs confirms the quality of the gate oxide. On the contrary, the DVfb of 1.2 V was obtained for the TiOxNy NPs sample. Therefore, it is concluded that the memory effect mainly results from charge injection into the TiOxNy NPs. The capacitance of the MOS device without TiOxNy NPs is larger than that of the MOS device with TiOxNy NPs ones due to thin HfON/NPs/HfON stacked dielectrics. Moreover, the charge trapping in the dielectric bulk is responsible for the DVfb of the
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MOS device. Therefore, Fig. 1 suggests that the DVfb can be achieved by the TiOxNy NPs embedded in the HfON high-k dielectrics. In addition, compared to without TiOxNy NPs sample, the C– V curves of the TiOxNy NPs sample shift to the left, indicating that the positive charges (hole trapping) are generated in the gate dielectric bulk due to the TiOxNy NPs as CTLs of the NVM devices. Fig. 2 shows the morphology of the TiOxNy NPs detected by SEM. The SEM image in Fig. 2 displays that the TiOxNy NPs with a diameter of around 5–20 nm and a surface density of 3 1011 cm 2 were obtained. To estimate the CTD of the TiOxNy NPs, the following equation was adopted: N = (Ceff/qA) DVfb, where Ceff is the capacitance of the MOS devices with the HfON/TiOxNy/HfON stack dielectric, q is the electronic charge and equal to 1.6 10 19 C, and A is the area of the MOS devices [10]. For the MOS devices with Ceff = 610 pF, A = 0.001963 cm2, and DVfb = 1.2 V, the CTD is estimated to be around 2.33 1012 cm 2 under 7 to +7 V sweep. According to the CTD measured under 7 to +7 V sweep, the average charge collection in each TiOxNy NPs can be estimated around 7.8 electrons or equivalent hole charges. The results shown in Fig. 1 suggest that the flatband voltage has a left shift, indicating that holes are easy to be trapped into the TiOxNy NPs. Since the mechanism is mainly resulted from the hole trapping, the program/erase speed of the devices with the TiOxNy NPs was addressed and shown in Fig. 3. During a positive biased at the control gate, the electrons directly tunnel from the Si substrate through the HfON tunnel oxide, and they are trapped in TiOxNy NPs. On the contrary, as a negative biased at the control gate, the holes are injected into TiOxNy NPs or the electrons detrap back to the Si substrate. The substrate is in depletion when the substrate was biased at small negative voltage. The holes are not easily trapped into NPs. Therefore, during writing operations in this work, the memory devices with the TiOxNy NPs under various writing times (WTs) were biased at a 10 V resulting in inversion layer in the substrate. With a Vprogram at 10 V, a 1 ms speed programming performance can be achieved with a memory window of about 1 V as shown in Fig. 3a. Erase properties of the MOS devices with TiOxNy NPs under various programming times by +10 V were shown in Fig. 3b. An erase speed of around 100 ls can be obtained. Compared with program speed, the MOS devices with TiOxNy NPs have a much faster erasing speed.
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Fig. 2. The morphology of the TiOxNy NPs detected by SEM. The CTD in TiOxNy NPs was extracted from N = (Ceff/qA) DVfb, where Ceff is the capacitance of the MOS devices with the HfON/TiOxNy/HfON stacked dielectric, q is the electronic charge and equals 1.6 10 19 C, A is the area of the MOS devices, and DVfb is the flatband voltage shift due to hysteresis sweep.
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Capacitance ( F/cm )
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2
Gate Voltage (V)
-0.3
-0.5 -0.6
Vprogram=-10 V
(a)
-1.0 1x10
-5
10
-3
10
-0.9
-1
0
10
Time (s)
1
10
2
10
3
10
4
10
5
10
6
10
Number of P/E cycles
1.0 VErase= +10 V
Fig. 5. Endurance characteristics of the MOS devices with the TiOxNy NPs using ±3, ±5 and ±10 V as the erase/programming voltages, respectively, performed at room temperature.
0.5
Vfb
0.0 -0.5 -1.0
Initial Program -10 V, 100 ms
-1.5 -7 10
(b) -5
-3
1x10
10
10
-1
Time (s) Fig. 3. (a) Program properties of the MOS devices with the TiOxNy NPs under various program times by 10 V. (b) Erase properties of the MOS devices with the TiOxNy NPs under various programming times by +10 V.
The charge retention tests of the memory devices with TiOxNy NPs using ±5 V, respectively, programming voltages were performed at room temperature. The capacitance variations as the function of the retention times after the electron or hole injection were shown in Fig. 4. The capacitance variation (C/C0) biased near flatband voltage indicates DVfb. The variation of the flatband voltage in MOS device is as the following equation: Vfb = ums Qtotal/ Cox, where ums is the difference of the work function between the gate electrode and the Si substrate, Qtotal is the charge in the dielectric, and Cox is the capacitance of dielectric. Therefore, the
1.2
Al/HfOxNy/TiOxNy/HfOxNy/N-Si 1.0
+5 V, 10 s programmed
variations of the capacitance indicate the DVfb resulting in threshold voltage shift. The results of Fig. 4 show that the memory window was stable during hole injection. Moreover, the programmed holes have a longer retention time than the electrons because they have a larger effective mass [20]. In this work, the NVM device programmed by hole injection has better the retention characteristics than the NVM device programmed by electron injection. The results are consistent with researches report [20]. Fig. 5 shows endurance characteristics of the MOS devices with the TiOxNy NPs using ±3, ±5 and ±10 V as the erase/programming voltages, respectively, performed at room temperature. The endurance properties after 106 P/E cycles were shown. The results suggest that a 30% memory window narrowing after 106 P/E cycles was demonstrated by performing at ±10 V P/E for 100 ms. Thus, the TiOxNy NPs embedded in the HfON high-k dielectric as charge trapping nodes due to the hole trapping mechanism are promising candidate for the advanced NVM device applications.
4. Conclusions The memory characteristics of the TiOxNy nanoparticles embedded in the HfOxNy as charge trapping nodes of the nonvolatile memory devices were investigated. Based on the C–V curve measurement and the morphology detected by SEM, the TiOxNy NPs with a diameter of 520 nm, a surface density of 3 1011 cm 2, and the charge trap density of around 2.33 1012 cm 2 were obtained. The TiOxNy NPs embedded in the HfON high-k dielectric as charge trapping nodes due to the hole trapping mechanism are promising candidate for the advanced NVM device applications.
C/C0
0.8
Acknowledgments
0.6
The authors would like to thank the National Science Council of the Republic of China for the financial support under Contract Nos. NSC 96-2221-E-492-012-MY3, NSC 97-2221-E-150-072 and NSC 96-2221-E-150-070-MY3. Technical support from National Nano Device Laboratories (NDL) of the ROC is also acknowledged.
Bias at Vg=0.4V near flatband voltage
0.4 0.2
-5 V, 10 s programmed
0.0 1
10
2
10
3
10
4
10
5
10
6
10
Retention time (sec) Fig. 4. Charge retention properties of the MOS devices with the TiOxNy NPs using ±5 V, respectively, programming voltages performed at room temperature.
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