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Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory
Current Applied Physics 14 (2014) 232e236
Contents lists available at ScienceDirect
Current Applied Physics journal homepage: www.elsevier.com/locate/cap
Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory Jer-Chyi Wang*, Chih-Ting Lin, Chi-Feng Chang Department of Electronic Engineering, Chang Gung University, Kweishan 333, Taoyuan, Taiwan, ROC
a r t i c l e i n f o
a b s t r a c t
Article history: Received 20 August 2013 Received in revised form 18 November 2013 Accepted 19 November 2013 Available online 28 November 2013
The characteristics of hybrid gadolinium oxide nanocrystal (Gd2O3-NC) and gadolinium oxide charge trapping (Gd2O3-CT) memories were investigated with different Gd2O3 film thickness. By performing the rapid thermal annealing on Gd2O3 films with different thickness, the Gd2O3-NCs with the diameter of 6 e9 nm for charge storage, surrounded by the amorphous Gd2O3 (a-Gd2O3) layer, were formed. The a-Gd2O3 layer was considered to be the charge trapping layer, resulting in the large memory window of Gd2O3-NC/CT memories with thick Gd2O3 film. The charge trapping energy level of the Gd2O3-NCs and a-Gd2O3 layer was extracted to be 0.16 and 0.45 eV respectively by using the temperature-dependent retention measurement. Further, after a 106 program/erase cycling operation, the memory with thin Gd2O3 film can be predicted to sustain a 94% memory window of the first cycling one while the memory with thick Gd2O3 film suffered from a 30% charge loss because of the traps within the a-Gd2O3 layer. The Gd2O3 film thickness of 10 nm was optimized to exhibit superior performances of the Gd2O3-NC/CT memory, which can be applied into the nonvolatile memory. Ó 2013 Elsevier B.V. All rights reserved.
Keywords: Nanocrystal memory Gadolinium oxide Charge trapping energy level
1. Introduction As the charge storage capacity of the conventional floating gate (FG) nonvolatile memory increases, the feature size of the device needs to be shrunk. The scaling of the floating gate structure approaches high difficulty beyond 32 nm node technology, primarily due to the high charge leakage current resulted from the conductive poly-silicon charge storage layer and the thin tunneling oxide [1e3]. To solve this, one promising candidate is to adopt the discrete charge storage nodes like the nanocrystals (NCs) embedded in the bottom and top dielectrics for the replacement of the poly-silicon layer [4e6]. The lateral charge leakage current can be effectively suppressed by the discontinuous storage nodes, thus enhancing the immunity of the vertical leakage current through the tunneling oxide. It is reported that the NC memories can be fabricated by lots of materials and formation strategies, which have high potential to be applied in the charge storage devices by taking the advantages over the conventional FG nonvolatile memory [7,8]. Recently, the Ge and Si NCs are proposed for the nonvolatile memory use because of the simple fabrication and complementarymetal-oxide-semiconductor (CMOS) compatible process [9e11]. The metal NCs such as Au, Pt, WSi2, and Ni embedded in the
* Corresponding author. E-mail address: [email protected] (J.-C. Wang). 1567-1739/$ e see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.cap.2013.11.019
dielectric layers can exhibit long data retention owing to the high work function [12e17]. In addition, the metal-oxide NC memory fabricated by HfO2-NCs embedded in a SiO2 matrix have been presented to have superior memory characteristics, especially for the large memory window and good data retention and endurance properties [18,19]. It is found that the presence of charge traps within the metal-oxide NCs as well as the surrounding dielectrics can provide the high charge storage capacity, thus the high tolerance for charge loss can be achieved [20]. Previously, the gadolinium oxide nanocrystal (Gd2O3-NC) has been reported to be the probable candidate as nonvolatile memories [21,22]. The Gd2O3-NCs can be formed by rapid thermal annealing (RTA) of the Gd2O3 film at an optimized temperature. The crystallized Gd2O3 (c-Gd2O3) with low energy band-gap (5.44 eV) surrounded by the amorphous Gd2O3 (a-Gd2O3) layer with high energy band-gap (6.19 eV) has been found to realize the Gd2O3-NCs [21,23]. The band-gap offset to achieve the electrons stored in Gd2O3-NCs is responsible for the charge storage of Gd2O3-NC memories, which is different from any other NC memory proposed before [4e19]. Furthermore, the charge trapping energy level of the Gd2O3-NCs can be extracted from the data retention characteristics [23]. It is expected that there may be some traps within the surrounding a-Gd2O3 layer, and some literature pointed out that the traps within the surrounding dielectric layer will affect the reliability behaviors of the NC memories [24,25]. To solve the problem, the CF4 plasma treatment on the Gd2O3-NC memory has been
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Fig. 1. Schematic structure and HRTEM image of the Gd2O3-NC/CT memory with the Gd2O3 film thickness of (a) 10 and (b) 20 nm. The tunneling oxide (TO), blocking oxide (BO), Gd2O3-NC, and a-Gd2O3 layer were indicated in the figures.
proposed to passivate the defects and modify the energy band diagram of the Gd2O3 film, efficiently improving the memory characteristics [25]. Nevertheless, the charge trapping characteristics of the a-Gd2O3 layer within the Gd2O3-NC memory has not yet been understood. In this paper, the thickness of the Gd2O3 film was varied to investigate the effect of charge storage dielectric thickness on hybrid Gd2O3 nanocrystal (Gd2O3-NC) and Gd2O3 charge trapping (Gd2O3-CT) memory. It can be found that with the increase of Gd2O3 film, the large memory window was obtained for the Gd2O3NC/CT memory due to the thick a-Gd2O3 layer for charge trapping. Further, the charge trapping energy level of the a-Gd2O3 layer was found to be higher than that of Gd2O3-NCs, which will influence the memory properties such as the poor endurance characteristic of the memory with thick Gd2O3 layer after 106 program/erase (P/E) operation cycles. 2. Experimental The Gd2O3-NC/CT memory devices were fabricated on 4 inch n-type (100) silicon wafers. After the standard RCA clean, a 3-nmthick silicon dioxide film was thermally grown at 850 C in an N2 and O2 mixed ambience using a horizontal furnace as the tunneling oxide. Then, the gadolinium oxide (Gd2O3) film was deposited on the tunneling oxide by RF sputtering with a pure gadolinium (99.9% pure) target in oxygen (O2) and argon (Ar) mixture ambience at room temperature. The proportion of oxygen and argon ambient flow rate was 1:7, and the pressure of the chamber was 20 mtorr for amorphous Gd2O3 formation. The thickness of the Gd2O3 film was assigned to be 6, 10, 15, and 20 nm for the investigation of the charge storage dielectric thickness effect. After the charge storage dielectric films had been formed, the samples were subjected to the rapid thermal annealing (RTA) system at 900 C for 30 s in N2 ambient to form the Gd2O3-NCs surrounded by the a-Gd2O3 layer. Next, in order to form the blocking oxide, 8-nm-thick of SiO2, using mixed SiH4 and N2O gases, was deposited using plasma enhanced chemical vapor deposition (PECVD) at 300 C. The gas flow ratio of the SiH4 and N2O gases was set to be 5:200 in order to lower the deposition rate for better SiO2 quality. After that, a 300-nm-thick aluminum (Al) film was deposited by thermal evaporator with a pure Al ingot (99.9999% pure), and a gate was defined lithographically and etched. The NC dot size of the Gd2O3-NC/CT memories and the film thickness of surrounding a-Gd2O3 layer were examined by the high resolution transmission electron microscopy (HRTEM). For the electrical analysis, the high frequency (1 MHz)
capacitanceevoltage (CeV) curves were measured by HP4285 precision LCR meter and the program and erase characteristics were measured by HP8110 pulse generator to supply the gate pulse. 3. Results and discussion 3.1. Material analysis and basic memory characteristics Fig. 1(a) and (b) shows the schematic structure and the corresponding HRTEM image of the Gd2O3-NC/CT memories with the Gd2O3 film thickness of 10 and 20 nm, respectively. The crystallized Gd2O3-NC surrounded by the amorphous Gd2O3 (a-Gd2O3) layer can be observed in these images. The diameter of the Gd2O3-NCs was found to be approximately 6e9 nm regardless of the thickness of Gd2O3 film, which was identical to our previous study [19]. In addition, the Gd2O3-NCs were located at the top of the Gd2O3 film, which was due to the top lamp RTP system (JETFIRST 100 from AnnealSys). The heat was provided from the top of the process wafer and the Gd2O3-NCs were formed by the re-crystallization of the nuclei sites at the top side. Thus, large proportion of the thick Gd2O3 film was amorphous phase (a-Gd2O3) and located at the bottom of the dielectric film, as revealed in Fig. 1(b). Fig. 2 demonstrates the capacitanceevoltage (CeV) hysteresis memory window of the Gd2O3-NC/CT memories with different
Fig. 2. High frequency CeV characteristics of the Gd2O3-NC/CT memories with different Gd2O3 film thickness. The curves were measured by sweeping the gate voltage from 13 to 13 V and then swept back. The maximum capacitance and relative permittivity of the Gd2O3 film were shown in the inset figure.
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Gd2O3 film thickness. The CeV curves were measured by sweeping the gate voltage from 13 to 13 V and then swept back. The gate voltage was normalized by subtracting VFBf, the flat-band voltage of the forward-sweeping curve, to obtain the same potential drop across the memory devices. The largest hysteresis memory window was observed for the sample with the Gd2O3 film thickness of 6 nm. The large memory window can be explained by the high electric field of the tunneling oxide owing to the thin dielectric thickness at the same applied voltage. Further, the relative permittivity of the Gd2O3 film can be estimated from the following formula:
d 1 1 1 1 dBO dTO ¼ þ þ ¼ þ Gd2 O3 þ ; Cmax CBO CGd2 O3 CTO εSiO2 ε0 εGd2 O3 ε0 εSiO2 ε0 (1) where Cmax is the maximum capacitance measured by the high frequency CeV curve and shown in inset of Fig. 2, CBO is the capacitance of blocking oxide, CGd2 O3 is the capacitance of Gd2O3 film, CTO is the capacitance of tunneling oxide, dBO is the thickness of the blocking oxide, dGd2 O3 is the thickness of the Gd2O3 film, dTO is the thickness of the tunneling oxide, εSiO2 is the relative permittivity of silicon dioxide, εGd2 O3 is the relative permittivity of the Gd2O3 film, and ε0 is the vacuum permittivity of 8.854 1012 F/ m. The thickness of the blocking oxide, Gd2O3 film, and tunneling oxide can be obtained by the HRTEM images, and the relative permittivity of silicon dioxide is 3.9. Thus, the relative permittivity of Gd2O3 film can be calculated according to Eq. (1) and also displayed in inset of Fig. 2. It can be observed that the relative permittivity of the Gd2O3 film decreased with the increase of the Gd2O3 film thickness. Chaneliere et al. proposed that the permittivity of the amorphous Ta2O5 film is lower than that of the crystallized one [26]. Thus, it is expected that the existence of the large portion of a-Gd2O3 in the Gd2O3 film will lead to the small dielectric permittivity. To understand the program and erase characteristics of the samples with different dielectric thickness, it is necessary to apply the same electric field of the tunneling oxide to eliminate the Gd2O3 thickness effect. From the Gauss’s law, when two different dielectrics are joined together, the electric flux through both materials will be the same; i.e. ε1E1 ¼ ε2E2. Hence, the electric field of the tunneling oxide can be calculated and the program/erase (P/E) characteristics of the Gd2O3-NC/CT memories with different Gd2O3 thickness under the electric field of tunneling oxide at program and erase operation for 8 and 8 MV/cm respectively was shown in Fig. 3. For the program operation, the larger flat-band voltage shift (DVFB) of the memories with thicker Gd2O3 film was obtained. It can be suggested that the electrons were not only trapped in the
Fig. 3. Program and erase characteristics of the Gd2O3-NC/CT memories with different Gd2O3 film thickness. The devices were programmed and erased at the electric field of tunneling oxide for 8 and 8 MV/cm respectively.
Gd2O3-NCs but in the a-Gd2O3 layer of the Gd2O3-NC/CT memories. On the other hand, for the erase operation, more electrons were erased for the samples with thicker Gd2O3 film, which will be explained in the following part. 3.2. Reliability properties and possible energy band diagrams Fig. 4 presents the retention characteristics of the Gd2O3-NC/CT memories with different Gd2O3 film thickness. At room temperature measurement, the charge loss was increased as the Gd2O3 film thickness decreased. The increased charge loss was resulted from the decrease of the dielectric thickness between the Gd2O3-NCs and Si substrate. The temperature dependence of the retention properties of the Gd2O3-NC/CT memories was displayed in inset of Fig. 4. The measurement temperature was ranged from 25 to 115 C. Compared with the sample with the Gd2O3 film thickness of 10 nm, the Gd2O3-NC/CT memory with the thickness of 20 nm showed a significant increase of the charge loss percentage at high measurement temperature. Koh et al. proposed that the Ge-NCs with different charge trapping energy levels of the germanium nanocrystal memory will contribute to the change of retention behavior at high measurement temperature [27]. Thus, the charge trapping energy levels of the Gd2O3-NC/CT memories with different Gd2O3 film thickness can be obtained by conducting the following equation:
1=s ¼ AT 2 eEt =kT ;
(2)
where s is the emission time constant, T is the absolute temperature, Et is the charge trapping energy level, and k is the Boltzmann constant. By defining the emission time constant at a certain charge loss value; for instance, 90% in this study, the charge trapping energy level can be obtained. Fig. 5 depicts the relationship between ln(1/sT2) and 1/kT of the Gd2O3-NC/CT memories with different Gd2O3 film thickness, where the slope of the fitting straight line represents the charge trapping energy level. For the memories with the Gd2O3 film thinner than 10 nm, only one charge trapping energy level was observed. The extracted charge trapping energy level was 0.16 eV, nearly the same as the value of the Gd2O3-NCs proposed before [23]. Besides, there were two different slopes of 0.16 eV and 0.27e0.45 eV in the low and high temperature regions respectively for the memories with thick Gd2O3 film. The higher charge trapping energy level at higher measurement temperature indicates that the charges may be lost from the traps within the aGd2O3 layer, since the high charge trapping energy level was only observed for the memories with significant a-Gd2O3 layer of the thick Gd2O3 film. Consequently, we can suggest that the memory
Fig. 4. Retention characteristics of the Gd2O3-NC/CT memories measured at room temperature. The retention properties measured at elevated temperatures for the samples with the Gd2O3 film thickness of 10 and 20 nm were shown in the inset figure.
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Fig. 5. Relationship between ln(1/sT2) and 1/kT of the Gd2O3-NC/CT memories with different Gd2O3 film thickness, where the slope of the fitting straight line represents the charge trapping energy level. Two different charge trapping energy levels of the memories with thick Gd2O3 film were obtained.
Fig. 7. Gate current density versus electric field (JeE) characteristics of the Gd2O3-NC/ CT memories with different Gd2O3 film thickness. The negative bias was applied at the gate electrode. The inset shows the energy band diagrams of the memories for thick and thin Gd2O3 films to illustrate the erase operation.
structure is composed of the Gd2O3-NCs and the Gd2O3 charge trapping layer (Gd2O3-CT), denoted as Gd2O3-NC/CT memory. Based on the analysis, possible energy band diagrams of the Gd2O3NC/CT memories with thick and thin Gd2O3 layer were proposed in Fig. 6. The energy band-gap of crystallized and amorphous Gd2O3 film is 6.19 and 5.44 eV respectively, and the conduction band offset between a-Gd2O3 and Gd2O3-NC is 0.38 eV in our previous study [23]. For the thick Gd2O3 film in Fig. 6(a), the a-Gd2O3 layer with the high charge trapping energy level of 0.45 eV presented a high charge loss at high measurement temperature. In contrast, for the thin Gd2O3 film, the electrons stored in Gd2O3-NCs with low charge trapping level (0.16 eV) will lose gradually with the increase of measurement temperature. Therefore, the retention behaviors in Fig. 4 can be well explained by the energy band diagrams in Fig. 6. The energy band diagrams in Fig. 6 can also be used to explain the erase characteristics shown in Fig 3. Fig. 7 shows the gate current density versus electric field (JeE) characteristics of the Gd2O3-NC/CT memories with different Gd2O3 thickness. The negative voltage was applied at the gate electrode and the electric field of the tunneling oxide was obtained by using the Gauss’s law as mentioned above. As a constant electric field was applied on the Gd2O3-NC/CT memories, the higher gate leakage current density of the samples with thicker Gd2O3 film, i.e. thicker a-Gd2O3 layer, was observed. The traps-assisted-tunneling (TAT) current with large electron transmission probability of the a-Gd2O3 layer is responsible for the high leakage current of the Gd2O3-NC/CT memories
with thick Gd2O3 film [28], as illustrated in the inset energy band diagrams of Fig. 7, leading to the high erase speed in Fig. 3. Fig. 8 presents the endurance characteristics of the Gd2O3-NC/CT memories with the Gd2O3 film thickness of 10 and 20 nm. Even after 106 P/E cycles, the Gd2O3-NC/CT memory with the Gd2O3 film thickness of 10 nm can be predicted to sustain a 94% memory window of the first cycling one. However, the sample with the Gd2O3 film thickness of 20 nm suffered from approximately 30% charge loss after 106 P/E cycles. It can be concluded that the Gd2O3-NC/CT memories without a-Gd2O3 layer can exhibit more reliable performance because the large amount of traps within the surrounding a-Gd2O3 layer will lead to some reliability issues. To obtain an optimized memory performance of the Gd2O3-NC/CT memory, the Gd2O3 film thickness of 10 nm was chosen to be suitable for future nonvolatile memory application.
Fig. 6. Possible energy band diagrams of the Gd2O3-NC/CT memories with (a) thick and (b) thin Gd2O3 film. The charge trapping energy level of Gd2O3-NCs and a-Gd2O3 layer was 0.16 and 0.45 eV respectively obtained from Fig. 5.
4. Conclusion The Gd2O3 film thickness dependence on the memory characteristics of the Gd2O3-NC/CT memory was investigated. After the rapid thermal annealing of Gd2O3 film, the Gd2O3-NCs were formed and surrounded by the a-Gd2O3 layer. The memories with thick Gd2O3 film can exhibit large memory window because of the formation of thick a-Gd2O3 layer for additional charge trapping. By using the temperature-dependent retention measurement, the charge trapping energy level of the Gd2O3-NCs and a-Gd2O3 layer was extracted to be 0.16 and 0.45 eV respectively. The energy band
Fig. 8. Endurance characteristics of the Gd2O3-NC memories with the Gd2O3 film thickness of 10 and 20 nm. After a 106 P/E cycling operation, the remaining memory window of the memories with the Gd2O3 film thickness of 10 and 20 nm can be predicted to be 94% and 70% respectively compared with that of the first cycling operation.
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diagrams were proposed to explain the memory characteristics of the Gd2O3-NC/CT memories such as the superior endurance property after a 106 P/E cycling operation of the memory with thin Gd2O3 film. Acknowledgments The authors thank the National Science Council, R.O.C. under the contract No. of NSC 102-2221-E-182-063. References [1] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, D. Buchanan, Tech. Dig. Int. Electron Devices Meet. (1995) 521. [2] D. Kahng, S.M. Sze, Bell Syst. Tech. J. 46 (1967) 1288. [3] P. Normand, P. Dimitrakis, E. Kapetanakis, D. Skarlatos, K. Beltsios, D. Tsoukalas, C. Bonafos, H. Coffin, G. Benassayag, A. Claverie, V. Soncini, A. Garwal, C. Sohl, M. Ameen, Microelectron. Eng. 73e74 (2004) 730. [4] J.D. Blauwe, IEEE Trans. Nanotechnol. 1 (2002) 72. [5] A. Chandra, B.M. Clemens, Appl. Phys. Lett. 87 (2005) 253113. [6] W.R. Chen, T.C. Chang, Y.T. Hsieh, S.M. Sze, C.Y. Chang, Appl. Phys. Lett. 91 (2007) 102106. [7] C.T. Chang, F.Y. Jian, S.C. Chen, Y.T. Tsai, Mater. Today 14 (2011) 608. [8] J.S. Lee, Phys. E Low Dimens. Syst. Nanostruct. 51 (2013) 94. [9] R. Aluguri, S. Das, R.K. Singha, S.K. Ray, Curr. Appl. Phys. 13 (2013) 12. [10] C.Y. Ng, T.P. Chen, J.I. Wong, M. Yang, T.S. Khor, C.L. New, C.M. Li, A.D. Trigg, S. Li, J. Nanosci. Nanotechnol. 1 (2007) 329.
[11] M. Kanoun, A. Souifi, T. Baron, F. Mazen, Appl. Phys. Lett. 84 (2004) 5079. [12] Y. Zhou, S.T. Han, Z.X. Xu, V.A. Roy, Nanotechnology 23 (2012) 344014. [13] J.Y. Tseng, C.W. Cheng, S.Y. Wang, T.B. Wu, K.Y. Hsieh, R. Liu, Appl. Phys. Lett. 85 (2004) 2595. [14] K.B. Seo, D.U. Lee, S.J. Han, E.K. Kim, H.-W. You, W.-J. Cho, Curr. Appl. Phys. 10 (2010) e5. [15] D. Panda, A. Dhar, S.K. Ray, Semicond. Sci. Technol. 24 (2009) 115020. [16] J.S. Lee, Gold Bull. 43 (2010) 189. [17] P.K. Singh, R. Hofmann, K.K. Singh, N. Krishna, S. Mahapatra, IEEE Trans. Electron Dev. 56 (2009) 2065. [18] Y.H. Lin, C.H. Chien, C.T. Lin, C.Y. Chang, T.F. Lei, IEEE Trans. Electron Dev. 53 (2006) 782. [19] Y.H. Lin, C.H. Chien, C.T. Lin, C.Y. Chang, T.F. Lei, IEEE Electron Dev. Lett. 26 (2005) 154. [20] S.K. Samanta, P.K. Singh, F.J. Ma, M.T. Yoo, R. Yonghan, W.J. Yoo, IEEE Trans. Electron Dev. 54 (2007) 3177. [21] J.C. Wang, C.S. Lai, Y.K. Chen, C.T. Lin, C.P. Liu, Michael R.S. Huang, Y.C. Fang, Electrochem. Solid-State Lett. 12 (2009) H202. [22] Michael R.S. Huang, C.P. Liu, J.C. Wang, Y.K. Chen, C.S. Lai, Y.C. Fang, L. Shu, Thin Solid Films 520 (2012) 5579. [23] J.C. Wang, C.T. Lin, P.C. Chou, C.S. Lai, Microelectron. Reliab. 52 (2012) 635. [24] C.C. Lin, T.C. Chang, C.H. Tu, W.R. Chen, C.W. Hu, S.M. Sze, T.Y. Tseng, S.C. Chen, J.Y. Lin, Appl. Phys. Lett. 94 (2009) 062106. [25] J.C. Wang, C.T. Lin, J. Appl. Phys. 109 (2011) 064506. [26] C. Chaneliere, S. Four, J.L. Autran, R.A.B. Devine, Electrochem. Solid-State Lett. 2 (1999) 291. [27] B.H. Koh, E.W.H. Kan, W.K. Chim, W.K. Choi, D.A. Antoniadis, E.A. Fitzgerald, J. Appl. Phys. 97 (2005) 124305. [28] J. Wu, L.F. Register, E. Rosenbaum, in: Proc. International Reliability Physics Symp., 1999, p. 389.
Contents lists available at ScienceDirect
Current Applied Physics journal homepage: www.elsevier.com/locate/cap
Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory Jer-Chyi Wang*, Chih-Ting Lin, Chi-Feng Chang Department of Electronic Engineering, Chang Gung University, Kweishan 333, Taoyuan, Taiwan, ROC
a r t i c l e i n f o
a b s t r a c t
Article history: Received 20 August 2013 Received in revised form 18 November 2013 Accepted 19 November 2013 Available online 28 November 2013
The characteristics of hybrid gadolinium oxide nanocrystal (Gd2O3-NC) and gadolinium oxide charge trapping (Gd2O3-CT) memories were investigated with different Gd2O3 film thickness. By performing the rapid thermal annealing on Gd2O3 films with different thickness, the Gd2O3-NCs with the diameter of 6 e9 nm for charge storage, surrounded by the amorphous Gd2O3 (a-Gd2O3) layer, were formed. The a-Gd2O3 layer was considered to be the charge trapping layer, resulting in the large memory window of Gd2O3-NC/CT memories with thick Gd2O3 film. The charge trapping energy level of the Gd2O3-NCs and a-Gd2O3 layer was extracted to be 0.16 and 0.45 eV respectively by using the temperature-dependent retention measurement. Further, after a 106 program/erase cycling operation, the memory with thin Gd2O3 film can be predicted to sustain a 94% memory window of the first cycling one while the memory with thick Gd2O3 film suffered from a 30% charge loss because of the traps within the a-Gd2O3 layer. The Gd2O3 film thickness of 10 nm was optimized to exhibit superior performances of the Gd2O3-NC/CT memory, which can be applied into the nonvolatile memory. Ó 2013 Elsevier B.V. All rights reserved.
Keywords: Nanocrystal memory Gadolinium oxide Charge trapping energy level
1. Introduction As the charge storage capacity of the conventional floating gate (FG) nonvolatile memory increases, the feature size of the device needs to be shrunk. The scaling of the floating gate structure approaches high difficulty beyond 32 nm node technology, primarily due to the high charge leakage current resulted from the conductive poly-silicon charge storage layer and the thin tunneling oxide [1e3]. To solve this, one promising candidate is to adopt the discrete charge storage nodes like the nanocrystals (NCs) embedded in the bottom and top dielectrics for the replacement of the poly-silicon layer [4e6]. The lateral charge leakage current can be effectively suppressed by the discontinuous storage nodes, thus enhancing the immunity of the vertical leakage current through the tunneling oxide. It is reported that the NC memories can be fabricated by lots of materials and formation strategies, which have high potential to be applied in the charge storage devices by taking the advantages over the conventional FG nonvolatile memory [7,8]. Recently, the Ge and Si NCs are proposed for the nonvolatile memory use because of the simple fabrication and complementarymetal-oxide-semiconductor (CMOS) compatible process [9e11]. The metal NCs such as Au, Pt, WSi2, and Ni embedded in the
* Corresponding author. E-mail address: [email protected] (J.-C. Wang). 1567-1739/$ e see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.cap.2013.11.019
dielectric layers can exhibit long data retention owing to the high work function [12e17]. In addition, the metal-oxide NC memory fabricated by HfO2-NCs embedded in a SiO2 matrix have been presented to have superior memory characteristics, especially for the large memory window and good data retention and endurance properties [18,19]. It is found that the presence of charge traps within the metal-oxide NCs as well as the surrounding dielectrics can provide the high charge storage capacity, thus the high tolerance for charge loss can be achieved [20]. Previously, the gadolinium oxide nanocrystal (Gd2O3-NC) has been reported to be the probable candidate as nonvolatile memories [21,22]. The Gd2O3-NCs can be formed by rapid thermal annealing (RTA) of the Gd2O3 film at an optimized temperature. The crystallized Gd2O3 (c-Gd2O3) with low energy band-gap (5.44 eV) surrounded by the amorphous Gd2O3 (a-Gd2O3) layer with high energy band-gap (6.19 eV) has been found to realize the Gd2O3-NCs [21,23]. The band-gap offset to achieve the electrons stored in Gd2O3-NCs is responsible for the charge storage of Gd2O3-NC memories, which is different from any other NC memory proposed before [4e19]. Furthermore, the charge trapping energy level of the Gd2O3-NCs can be extracted from the data retention characteristics [23]. It is expected that there may be some traps within the surrounding a-Gd2O3 layer, and some literature pointed out that the traps within the surrounding dielectric layer will affect the reliability behaviors of the NC memories [24,25]. To solve the problem, the CF4 plasma treatment on the Gd2O3-NC memory has been
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Fig. 1. Schematic structure and HRTEM image of the Gd2O3-NC/CT memory with the Gd2O3 film thickness of (a) 10 and (b) 20 nm. The tunneling oxide (TO), blocking oxide (BO), Gd2O3-NC, and a-Gd2O3 layer were indicated in the figures.
proposed to passivate the defects and modify the energy band diagram of the Gd2O3 film, efficiently improving the memory characteristics [25]. Nevertheless, the charge trapping characteristics of the a-Gd2O3 layer within the Gd2O3-NC memory has not yet been understood. In this paper, the thickness of the Gd2O3 film was varied to investigate the effect of charge storage dielectric thickness on hybrid Gd2O3 nanocrystal (Gd2O3-NC) and Gd2O3 charge trapping (Gd2O3-CT) memory. It can be found that with the increase of Gd2O3 film, the large memory window was obtained for the Gd2O3NC/CT memory due to the thick a-Gd2O3 layer for charge trapping. Further, the charge trapping energy level of the a-Gd2O3 layer was found to be higher than that of Gd2O3-NCs, which will influence the memory properties such as the poor endurance characteristic of the memory with thick Gd2O3 layer after 106 program/erase (P/E) operation cycles. 2. Experimental The Gd2O3-NC/CT memory devices were fabricated on 4 inch n-type (100) silicon wafers. After the standard RCA clean, a 3-nmthick silicon dioxide film was thermally grown at 850 C in an N2 and O2 mixed ambience using a horizontal furnace as the tunneling oxide. Then, the gadolinium oxide (Gd2O3) film was deposited on the tunneling oxide by RF sputtering with a pure gadolinium (99.9% pure) target in oxygen (O2) and argon (Ar) mixture ambience at room temperature. The proportion of oxygen and argon ambient flow rate was 1:7, and the pressure of the chamber was 20 mtorr for amorphous Gd2O3 formation. The thickness of the Gd2O3 film was assigned to be 6, 10, 15, and 20 nm for the investigation of the charge storage dielectric thickness effect. After the charge storage dielectric films had been formed, the samples were subjected to the rapid thermal annealing (RTA) system at 900 C for 30 s in N2 ambient to form the Gd2O3-NCs surrounded by the a-Gd2O3 layer. Next, in order to form the blocking oxide, 8-nm-thick of SiO2, using mixed SiH4 and N2O gases, was deposited using plasma enhanced chemical vapor deposition (PECVD) at 300 C. The gas flow ratio of the SiH4 and N2O gases was set to be 5:200 in order to lower the deposition rate for better SiO2 quality. After that, a 300-nm-thick aluminum (Al) film was deposited by thermal evaporator with a pure Al ingot (99.9999% pure), and a gate was defined lithographically and etched. The NC dot size of the Gd2O3-NC/CT memories and the film thickness of surrounding a-Gd2O3 layer were examined by the high resolution transmission electron microscopy (HRTEM). For the electrical analysis, the high frequency (1 MHz)
capacitanceevoltage (CeV) curves were measured by HP4285 precision LCR meter and the program and erase characteristics were measured by HP8110 pulse generator to supply the gate pulse. 3. Results and discussion 3.1. Material analysis and basic memory characteristics Fig. 1(a) and (b) shows the schematic structure and the corresponding HRTEM image of the Gd2O3-NC/CT memories with the Gd2O3 film thickness of 10 and 20 nm, respectively. The crystallized Gd2O3-NC surrounded by the amorphous Gd2O3 (a-Gd2O3) layer can be observed in these images. The diameter of the Gd2O3-NCs was found to be approximately 6e9 nm regardless of the thickness of Gd2O3 film, which was identical to our previous study [19]. In addition, the Gd2O3-NCs were located at the top of the Gd2O3 film, which was due to the top lamp RTP system (JETFIRST 100 from AnnealSys). The heat was provided from the top of the process wafer and the Gd2O3-NCs were formed by the re-crystallization of the nuclei sites at the top side. Thus, large proportion of the thick Gd2O3 film was amorphous phase (a-Gd2O3) and located at the bottom of the dielectric film, as revealed in Fig. 1(b). Fig. 2 demonstrates the capacitanceevoltage (CeV) hysteresis memory window of the Gd2O3-NC/CT memories with different
Fig. 2. High frequency CeV characteristics of the Gd2O3-NC/CT memories with different Gd2O3 film thickness. The curves were measured by sweeping the gate voltage from 13 to 13 V and then swept back. The maximum capacitance and relative permittivity of the Gd2O3 film were shown in the inset figure.
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Gd2O3 film thickness. The CeV curves were measured by sweeping the gate voltage from 13 to 13 V and then swept back. The gate voltage was normalized by subtracting VFBf, the flat-band voltage of the forward-sweeping curve, to obtain the same potential drop across the memory devices. The largest hysteresis memory window was observed for the sample with the Gd2O3 film thickness of 6 nm. The large memory window can be explained by the high electric field of the tunneling oxide owing to the thin dielectric thickness at the same applied voltage. Further, the relative permittivity of the Gd2O3 film can be estimated from the following formula:
d 1 1 1 1 dBO dTO ¼ þ þ ¼ þ Gd2 O3 þ ; Cmax CBO CGd2 O3 CTO εSiO2 ε0 εGd2 O3 ε0 εSiO2 ε0 (1) where Cmax is the maximum capacitance measured by the high frequency CeV curve and shown in inset of Fig. 2, CBO is the capacitance of blocking oxide, CGd2 O3 is the capacitance of Gd2O3 film, CTO is the capacitance of tunneling oxide, dBO is the thickness of the blocking oxide, dGd2 O3 is the thickness of the Gd2O3 film, dTO is the thickness of the tunneling oxide, εSiO2 is the relative permittivity of silicon dioxide, εGd2 O3 is the relative permittivity of the Gd2O3 film, and ε0 is the vacuum permittivity of 8.854 1012 F/ m. The thickness of the blocking oxide, Gd2O3 film, and tunneling oxide can be obtained by the HRTEM images, and the relative permittivity of silicon dioxide is 3.9. Thus, the relative permittivity of Gd2O3 film can be calculated according to Eq. (1) and also displayed in inset of Fig. 2. It can be observed that the relative permittivity of the Gd2O3 film decreased with the increase of the Gd2O3 film thickness. Chaneliere et al. proposed that the permittivity of the amorphous Ta2O5 film is lower than that of the crystallized one [26]. Thus, it is expected that the existence of the large portion of a-Gd2O3 in the Gd2O3 film will lead to the small dielectric permittivity. To understand the program and erase characteristics of the samples with different dielectric thickness, it is necessary to apply the same electric field of the tunneling oxide to eliminate the Gd2O3 thickness effect. From the Gauss’s law, when two different dielectrics are joined together, the electric flux through both materials will be the same; i.e. ε1E1 ¼ ε2E2. Hence, the electric field of the tunneling oxide can be calculated and the program/erase (P/E) characteristics of the Gd2O3-NC/CT memories with different Gd2O3 thickness under the electric field of tunneling oxide at program and erase operation for 8 and 8 MV/cm respectively was shown in Fig. 3. For the program operation, the larger flat-band voltage shift (DVFB) of the memories with thicker Gd2O3 film was obtained. It can be suggested that the electrons were not only trapped in the
Fig. 3. Program and erase characteristics of the Gd2O3-NC/CT memories with different Gd2O3 film thickness. The devices were programmed and erased at the electric field of tunneling oxide for 8 and 8 MV/cm respectively.
Gd2O3-NCs but in the a-Gd2O3 layer of the Gd2O3-NC/CT memories. On the other hand, for the erase operation, more electrons were erased for the samples with thicker Gd2O3 film, which will be explained in the following part. 3.2. Reliability properties and possible energy band diagrams Fig. 4 presents the retention characteristics of the Gd2O3-NC/CT memories with different Gd2O3 film thickness. At room temperature measurement, the charge loss was increased as the Gd2O3 film thickness decreased. The increased charge loss was resulted from the decrease of the dielectric thickness between the Gd2O3-NCs and Si substrate. The temperature dependence of the retention properties of the Gd2O3-NC/CT memories was displayed in inset of Fig. 4. The measurement temperature was ranged from 25 to 115 C. Compared with the sample with the Gd2O3 film thickness of 10 nm, the Gd2O3-NC/CT memory with the thickness of 20 nm showed a significant increase of the charge loss percentage at high measurement temperature. Koh et al. proposed that the Ge-NCs with different charge trapping energy levels of the germanium nanocrystal memory will contribute to the change of retention behavior at high measurement temperature [27]. Thus, the charge trapping energy levels of the Gd2O3-NC/CT memories with different Gd2O3 film thickness can be obtained by conducting the following equation:
1=s ¼ AT 2 eEt =kT ;
(2)
where s is the emission time constant, T is the absolute temperature, Et is the charge trapping energy level, and k is the Boltzmann constant. By defining the emission time constant at a certain charge loss value; for instance, 90% in this study, the charge trapping energy level can be obtained. Fig. 5 depicts the relationship between ln(1/sT2) and 1/kT of the Gd2O3-NC/CT memories with different Gd2O3 film thickness, where the slope of the fitting straight line represents the charge trapping energy level. For the memories with the Gd2O3 film thinner than 10 nm, only one charge trapping energy level was observed. The extracted charge trapping energy level was 0.16 eV, nearly the same as the value of the Gd2O3-NCs proposed before [23]. Besides, there were two different slopes of 0.16 eV and 0.27e0.45 eV in the low and high temperature regions respectively for the memories with thick Gd2O3 film. The higher charge trapping energy level at higher measurement temperature indicates that the charges may be lost from the traps within the aGd2O3 layer, since the high charge trapping energy level was only observed for the memories with significant a-Gd2O3 layer of the thick Gd2O3 film. Consequently, we can suggest that the memory
Fig. 4. Retention characteristics of the Gd2O3-NC/CT memories measured at room temperature. The retention properties measured at elevated temperatures for the samples with the Gd2O3 film thickness of 10 and 20 nm were shown in the inset figure.
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Fig. 5. Relationship between ln(1/sT2) and 1/kT of the Gd2O3-NC/CT memories with different Gd2O3 film thickness, where the slope of the fitting straight line represents the charge trapping energy level. Two different charge trapping energy levels of the memories with thick Gd2O3 film were obtained.
Fig. 7. Gate current density versus electric field (JeE) characteristics of the Gd2O3-NC/ CT memories with different Gd2O3 film thickness. The negative bias was applied at the gate electrode. The inset shows the energy band diagrams of the memories for thick and thin Gd2O3 films to illustrate the erase operation.
structure is composed of the Gd2O3-NCs and the Gd2O3 charge trapping layer (Gd2O3-CT), denoted as Gd2O3-NC/CT memory. Based on the analysis, possible energy band diagrams of the Gd2O3NC/CT memories with thick and thin Gd2O3 layer were proposed in Fig. 6. The energy band-gap of crystallized and amorphous Gd2O3 film is 6.19 and 5.44 eV respectively, and the conduction band offset between a-Gd2O3 and Gd2O3-NC is 0.38 eV in our previous study [23]. For the thick Gd2O3 film in Fig. 6(a), the a-Gd2O3 layer with the high charge trapping energy level of 0.45 eV presented a high charge loss at high measurement temperature. In contrast, for the thin Gd2O3 film, the electrons stored in Gd2O3-NCs with low charge trapping level (0.16 eV) will lose gradually with the increase of measurement temperature. Therefore, the retention behaviors in Fig. 4 can be well explained by the energy band diagrams in Fig. 6. The energy band diagrams in Fig. 6 can also be used to explain the erase characteristics shown in Fig 3. Fig. 7 shows the gate current density versus electric field (JeE) characteristics of the Gd2O3-NC/CT memories with different Gd2O3 thickness. The negative voltage was applied at the gate electrode and the electric field of the tunneling oxide was obtained by using the Gauss’s law as mentioned above. As a constant electric field was applied on the Gd2O3-NC/CT memories, the higher gate leakage current density of the samples with thicker Gd2O3 film, i.e. thicker a-Gd2O3 layer, was observed. The traps-assisted-tunneling (TAT) current with large electron transmission probability of the a-Gd2O3 layer is responsible for the high leakage current of the Gd2O3-NC/CT memories
with thick Gd2O3 film [28], as illustrated in the inset energy band diagrams of Fig. 7, leading to the high erase speed in Fig. 3. Fig. 8 presents the endurance characteristics of the Gd2O3-NC/CT memories with the Gd2O3 film thickness of 10 and 20 nm. Even after 106 P/E cycles, the Gd2O3-NC/CT memory with the Gd2O3 film thickness of 10 nm can be predicted to sustain a 94% memory window of the first cycling one. However, the sample with the Gd2O3 film thickness of 20 nm suffered from approximately 30% charge loss after 106 P/E cycles. It can be concluded that the Gd2O3-NC/CT memories without a-Gd2O3 layer can exhibit more reliable performance because the large amount of traps within the surrounding a-Gd2O3 layer will lead to some reliability issues. To obtain an optimized memory performance of the Gd2O3-NC/CT memory, the Gd2O3 film thickness of 10 nm was chosen to be suitable for future nonvolatile memory application.
Fig. 6. Possible energy band diagrams of the Gd2O3-NC/CT memories with (a) thick and (b) thin Gd2O3 film. The charge trapping energy level of Gd2O3-NCs and a-Gd2O3 layer was 0.16 and 0.45 eV respectively obtained from Fig. 5.
4. Conclusion The Gd2O3 film thickness dependence on the memory characteristics of the Gd2O3-NC/CT memory was investigated. After the rapid thermal annealing of Gd2O3 film, the Gd2O3-NCs were formed and surrounded by the a-Gd2O3 layer. The memories with thick Gd2O3 film can exhibit large memory window because of the formation of thick a-Gd2O3 layer for additional charge trapping. By using the temperature-dependent retention measurement, the charge trapping energy level of the Gd2O3-NCs and a-Gd2O3 layer was extracted to be 0.16 and 0.45 eV respectively. The energy band
Fig. 8. Endurance characteristics of the Gd2O3-NC memories with the Gd2O3 film thickness of 10 and 20 nm. After a 106 P/E cycling operation, the remaining memory window of the memories with the Gd2O3 film thickness of 10 and 20 nm can be predicted to be 94% and 70% respectively compared with that of the first cycling operation.
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