Charge retention in scaled SONOS nonvolatile semiconductor memory devices—Modeling and characterization

Solid-State Electronics Vol. 36, No. 10, pp. 1401-1416, 1993

0038-1101/93 $6.00+ 0.00 Copyright © 1993PergamonPr'-=a~Ltd

Printed in Great Britain. All rights reserved

CHARGE RETENTION IN SCALED SONOS NONVOLATILE SEMICONDUCTOR MEMORY D E V I C E S - - M O D E L I N G A N D CHARACTERIZATIONS" YIN H u and MARVIN H. WroTE Sherman Fairchild Center for Solid State Studies, Department of Electrical Engineering and Computer Science, Lehigh University, Bethlehem, PA 18015, U.S.A. (Received 24 January 1993; in revised form 5 March 1993)

Abstraet--A new analytical model is developed to investigate the influence of the charge loss processes in the retention mode of the SONOS NVSM device. The model considers charge loss by the following processes: (I) electron back-tunneling from the nitride traps to the Si conduction band, (2) electron back-tunneling from the nitride traps to the Si/SiO2 interface traps and (3) hole injection from the Si valence band to the nitride traps. An amphoteric trap charge distribution is used in this model. The new charge retention model predicts that process (1) determines the short term retention, while processes (2) and (3) determine the long term retention. Good agreement has been reached between the results of analytical calculations and the experimental retention data on both surface channel and buried channel SONOS devices.

NOTATION C~ co co c~+ cf e° e° e+ e~

effective capacitance of the ONO dielectrics [F/cm2] capture coefficient of electrons in the D Ostate [l/s] capture coefficient of holes in the D Ostate [l/s] capture coefficient of electrons in the D + state [l/s] capture coefficient of electrons in the D - state [l/s] emission coefficient ofelectrons in the D Ostate [I/s] emission coefficient of holes in the D 0 state [l/s] emission coefficient of electrons in the D ÷ state [1/s] emission coefficient of electrons in the D - state [I/s] Dit Si/SiO2interface trap density [1/eV em2] % permittivity of the Si3N4 [F/cm] Eo~ permittivity of the SiO2 [F/cm] ~ permittivity of the Si [F/cm] Eox electric field in the SiO2 [V/cm] E. electric field in the Si3N4 [V/era] EoN nitride band gap [eV] m*.e electron effective mass in the Si [kg] m*x.c electron effective mass in the SiO2 [kg] m*c electron effective mass in the Si3N4 [kg] m~.h hole effective mass in the Si [kg] mo*~h hole effective mass in the SiO2 [kg] m*h hole effective mass in the Si3N4 [kg] NT uniform trap density in the Si3N4 [l/cm 3] ~b~ barrier height between the Si and the SiO2 for electrons [eV] ~b~ barrier height between the SiO2 and the Si3N4 for electrons [eV] ~b~ barrier height between the Si and the Si3N 4 for holes [eV] ~b2 h barrier height between the SiO2 and the SiO 2 for holes [eV] ~bMS work function difference between the gate and the substrate [V] O, semiconductor surface potential IV] Q, charge in the Si [C/cm 2] Qit interface trap charge at the Si/SiO2 interface [C/cm2] Qr fixed charge in the tunneling oxide [C/cm 2] p,(x, t) charge trap density in the Si3N4 [C/cm 3] i'This project was partially supported by the Sherman Fairchild Foundation, the National Science Foundation and the Office of Naval Research.

Xot Xn ?fob x

tunneling oxide thickness [A] nitride thickness [A] blocking oxide thickness [A] distance from the tunneling oxide and nitride inter° face into the nitride [/~] l. INTRODUCTION

Electrically Erasable Programmable Read Only Memories (EEPROMs) are becoming a d o m i n a n t product for Nonvolatile Semiconductor Memory (NVSM). One of the potential applications of E E P R O M s is for the semiconductor disk which can replace the magnetic disk drive in portable computer systems. The major concern for this application is whether the programming voltage of the E E P R O M device can be scaled to match the scaled-down power supply of the sub-half-micron CMOS circuits. The programming voltage for the floating gate E E P R O M devices is maintained at >~15V because of the limitation in scaling the inter-poly dielectric thickness[l,2]. Meanwhile, the programming voltage for Polysilicon- Oxide -Nitride-Qxide -_Silicon (SONOS) devices has been scaled to 5-6 V since 198313-6], by scaling the nitride thickness of the device to ~ 50 ,~. In addition, a large n u m b e r ( > 1,000,000) of ERASE/ W R I T E cycles and long term ( > 1 0 years) data retention are required for the semiconductor disk application[7]. Therefore, the reliability of the scaled SONOS device is an important design criterion for EEPROMs. The scaled SONOS device can usually take a high n u m b e r of E R A S E / W R I T E cycles because of the low programming fields in the O N O dielectric layers[8]. Data retention for the scaled SONOS device is determined by the loss of charge stored in the nitride layer. Measurement results on a typical surface n-channel

1401

1402

YINHU and MARVINH. WHITE

0.2 0.18

.

. - .

.

.

.

.

buried-channel SONOS device has less hole injection during the retention mode. In the retention mode, the gate, substrate as well as source/drain junction of the device are generally grounded. Figure 3 shows the cross section and band diagram of a scaled SONOS device in the retention mode. The injected electrons stored in the nitride layer establish an electric field such that stored electrons can leave their traps by the following tunneling processes:

.

SCSONOS

~0.16 0.14 ~ 0.12 0.1

0.08

100

102 104 106 10 Number of E/W cycles Fig. 1. The threshold voltage decay rate in the retention mode after WRITE is plotted as a function of the number of ERASE/WRITE cycles. Data were obtained from measurements on a surface n-channel SONOS device with Xot = 20 A, X. = 68 • and Xob= 72 A. The measurement was made at 1-1000 s. The ERASE/WRITE cycling conditions are: +10V, 20ms; -10V, 101 ms.

(1) electron direct tunneling from traps into the silicon conduction band[12]; (2) electron tunneling from nitride traps into the Si/SiO2 interface traps[9,10]; (3) the Poole-Frenkel emission process[13]; (4) hole injection from Si valence band into the nitride traps under the internal electric field, and recombination with the electrons in nitride traps[12,14]; (5) alteration of the internal charge distribution and electric field due to the detrapping of electrons in the bulk nitride[12]; (6) stored electrons and holes tunneling through the blocking oxide to the gate electrode.

SONOS device show that the threshold voltage decay rate, t~Vth(t)/6~ log(t), in the retention mode, and the Si/SiO2 interface trap density, Dit increase with increasing number of ERASE/WRITE cycles, as shown in Figs 1 and 2. All these phenomena are the result of the change in the charge storage in the nitride after ERASE/WRITE cycling and have been observed by a number of research groups[9-1 l]. Recently, Hu and White[5] reported that the buried channel SONOS structure achieves better retention compared with the surface-channel SONOS structure because the

1012

..,

..,

All these six processes can cause a loss in memory for the SONOS device. Figure 3 shows the energy band diagram of these charge loss processes in the nitride. Processes (1) and (2) are usually referred to as the back tunneling processes and are similar to reported hysteresis effects in MOS transistors[15].

..,

..,

..,

..,

..,

single.wall oxidation o

Xot = 20 A Xn = 73 A Xob = 54 A

m

/

~

~

d

~

'

~

O

~

l

Xot = 20 ~.

1011 J

Xn = 68 Xob = 72 ,~ t r i p l e - w ~

.m

10 ~o 10 0

101

102

10 3

104

10 s

10 6

10 7

10 8

Erase/Write Cycles Fig. 2. The Si/SiO2 interface trap density Dit as function of the E/W cycles for SONOS devices with the tunneling oxide grown by single-walland triple-wall oxidations. For the SONOS devicewith the tunneling oxide grown by single-wall oxidation, Xot = 20 A, X, = 73 ~ and Xob= 54 A, The width to length ratio of the device is: W/L = 24 ~m/24 #m. The cycling conditions are: +9 V, 3 ms; - 9 V, 30 ms. For the SONOS device with the tunneling oxide grown by triple-wall oxidation, Xot = 20 A, Xn = 68 A and Xob= 72 A. The width to length ratio of the device is: W/L = 48/~m/12 #m. The cycling conditions are: + 10 V, 20 ms; - 10 V, 150 ms. The cycling measurement parameters are chosen to have the same electric fields in the ONO dielectrics of both devices.

Charge retention in memory devices

1403

(a)

~__ EFG _-=-

Dit - C - p ~ Si

O

0

N

Poly Si

J

Xot

XN

Xob

Fig. 3. (a) The cross section of the scaled SONOS device in the retention mode. (b) The energy band diagram of the tunneling processes responsible for the charge loss in the nitride in the retention after WRITE: (~) is the process of electrons tunneling from the nitride traps to the Si conduction band (e~); (~) is the process of electrons tunneling from the nitride traps to the Si/SiO2 interface traps (e°); (~) is the Poole-Frenkel emission process; 0) is the process of hole injection from the Si valence band to the nitride traps (c°); (~) is the process of the internal charge distribution; and (~) is the process of electron tunneling through the blocking oxide to the electrode. Process (4) is usually referred to as the soft ERASE or soft WRITE process and is important when a large amount of charge is stored in the nitride. Process (5) is strongly dependent on temperature and field[16] and normally less important in thin oxide devices (15-35 A) due to the low nitride field in the retention mode. Process (6) can be minimized with a thicker blocking oxide[17]. To achieve good retention characteristics in SONOS NVSM devices, it is important to understand the mechanism of the loss in the stored charge in the nitride layer during the retention mode. Previous authors have developed charge-loss process models which include: electrons back-tunneling from the nitride traps to the Si conduction band with an exponential trapped-charge distribution in the silicon nitride[12], electrons back-tunneling from the nitride

traps to Si/SiO2 interface traps with a single-level trap charge distribution in the nitride[9], and electrons back-tunneling from the nitride traps to the Si conduction band with an amphoteric trap charge distribution in the nitride[18]. In all these charge loss process models, the authors only dealt with one of the six charge loss processes listed above and neglected hole injection from the Si valence band to the nitride traps, which is a major contribution to the loss of the charge retention in the SONOS devices[18]. In this paper, we present a comprehensive model to investigate the influence of charge loss processes on the charge retention in the scaled nitride layers (50-70 A) of SONOS devices. The new model considers three charge-loss processes in the scaled SONOS devices and uses an amphoteric trap distribution in the nitride layer. The new model assumes

1404

YIN Hu and MARVINH. WHITE

that (1) electrons tunneling from the nitride traps to the Si conduction band dominates the short term charge retention (1 #s-10ms). The charge loss for long term retention ( > 1 0 m s ) is governed by (2) electrons tunneling from the stored nitride traps to the Si/SiO2 interface traps and (3) hole injection from the Si valence band to the nitride traps. We have compared experimental retention data obtained from surface- and buried-channel SONOS devices with results of analytical calculations and observed good agreement between the model prediction and experimental results.

Amphoteric Trap Model

d

e:..


2. I. Amphoteric trap model

Deep-trapping centers play a critical role in silicon nitride films used in nonvolatile memories[19-22]. Many studies have been performed to explore the origin and charge state of these traps. The idea that amphoteric traps in the silicon nitride may be responsible for the memory characteristics of SONOS transistor was proposed initially by Robertson and Powell[23] with theoretical calculations in 1981 and later verified by Fujita and Sasaki[22] with electron spin resonance and optical measurements in 1985, and Krick et al.[24] with electron spin resonance and electrical measurements in 1988. In 1985, White and Chao[25] solved the coupled-rate equations based on the amphoteric trap model and the one-dimensional continuity equation for the electron capture process. They applied the results to the ERASE/WRITE operation of the nonvolatile SONOS device structure. Recently, there have been additional results to support an amphoteric trap model in the silicon nitride[26,27]. We have employed the ampboteric trap model in this paper to analyze the charge loss processes in the silicon nitride. The amphoteric traps considered here are paramagnetic silicon-dangling-bond centers in the silicon nitride which have three charge states (D +, D °, D - ) and two transition energies (ETA, ErO)[22,24]. An

"

D.

:.f "~h+

EGN

2. THRESHOLD VOLTAGE DECAY MODEL FOR CHARGE RETENTION

In this section, we present a new threshold-voltage decay model which includes: (1) electron charge loss by trap-to-band tunneling to the Si, (2) electron charge loss by trap-to-Si/SiO 2 interface-trap tunneling, and (3) hole injection from the Si to the nitride by band-to-trap tunneling processes with an amphoteric trap charge distribution model in the nitride. In the second charge loss process, we assume that after the electron charges tunnel to the Si/SiO2 interface traps, they are emitted to the Si conduction band immediately. This model not only predicts the effects of the initial stored charge on the threshold voltage decay during short-term retention, but also predicts the effect of the Si/SiO2 interface trap density and hole injection on the threshold voltage decay during long-term retention.

,:,o %

( -10 )

ETA

( 0/+ )

ETD

E=0 Fig. 4. Charge states and transitional energiesETA and E.rD of an amphotcric trap for electron and hole processes.

amphoteric trap interacts with electrons and holes as shown in Fig. 4. Consider, initially, that there are two electrons in the D - state where the associated energy level is ErA. By emitting one electron, the second electron will be transferred to the D o state where the associated energy level is ErD. The transition for this second electron movement from the D - to the D o state is the result of electron and lattice relaxation and the transition time is on the order of 10-14-10-12 s. If the second electron emits again, then the trap assumes the D + ground state. There are four capture and emission processes involved in the three states of an amphoteric trap and these processes may be expressed with two coupled first-order rate equations for the occupation funct i o n s f + (D + state),f ° (D Ostate), and f - ( D - state): df + o o + = ¢ p f --ep f dt

--

drdt

= c°f ° -- e:f-

+

--

c~+f+ + e . f o o,

-- c;f-

f0 + f - + f + = 1.

+ e ° f °,

(1)

(2)

(3)

The emission and capture coefficients in the above rate equations are different from the thermal emission and capture coefficients in the SRH generation and recombination theory[28,29]. We neglect the thermal emission and capture processes to the silicon nitride bands in the above rate equations because the traps in this study are "deep" traps. Let us consider three tunneling processes for the electron discharge from the nitride layer as shown in Fig. 5. (The hole discharge process is assumed to be analogous.) First, electrons at the D - trap state back tunnel to the Si conduction band. This tunneling

Charge retention in memory devices

•

1405

,w EGN o

•

.......

en

Dit

Si

Si 3 N 4

SiO2

/

_1

41

Xo t

-[ 0

X

Fig. 5. Energy band diagram for the SONOS structure in the retention state after WRITE. The electron emission processes include tunneling from D - state to the Si conduction band ( e ; ) , emission from D state to D Ostate, and tunneling from D Ostate to the Si/SiO 2 interface states (e°). The hole injection from the Si valence band to silicon nitride traps and capture by traps in D Ostate (c °) is also shown in the figure.

x/2m*.~ [Ero - q ( ~ -- ~b~)]

process is characterized by a time constant ~ r - e (x) at a distance x from the SiO2/Si3N 4 interface[30,31]:

1

ZT- n (X) -- ---2_= ZT- a0 c h x ~ e ~ ,

~ =

h

,

x/2m*x.°(q~ + ETD)

(4)

17n =

(I0)

(II)

h

en

where TT- ~ is an intrinsic time constant on the order of 10-12-10 -i4 s[12], and:

Third, holes in the Si valence band tunnel to nitride traps in the D o state with a time constant

ZB-T(X)[33]: I T B - T ~ "["0 = '~B- TO ea°txX°t e ~ x ,

h

x

Cp

l

1 e.o~a;,

1

44~+ETA/q

24~+ErA/q]'

ot~ ~ 2

1

E.x

4 Ck~+ ETA/q "

here za_ To is assumed to be the same as ~T-~ and

] (5)

1

~--

~ = ~e

"~T - To e2s°~ Xote2,t. x,

_h ~ox

(7)

,

~

2 ~ ~ 1 h

h

~t_h= 2x/2qm*.~(EoN -- ETD) h

(6)

The second tunneling process describes the tunneling of electrons in the D O trap state to the Si/SiO2 interface traps. The time constant ~T-T(X) associated with this process is[32]: TT - T ( X )

df+(x, t) -- eO(x)fO(x, t) -~ C°p(X)f°(x, t), dt d f - ( x , t) = - e l ( x ) f - ( x , t). dt

(8)

2~ 2thi t~3Dit lit

•

no,,- x/2mo,,..(q~,, + erD)

h

'

(9)

(13) 04 )

With the electron emission and hole capture processes described above, the rate equations for the occupancy functions becomes:

- -

where:

~T - To ----"

(12)

(15)

(16)

Assume injected electrons are all trapped in the D state initially (t = 0), so:

f - ( x , O) ----1,

(17)

f ° ( x , 0) = 0,

(18)

f+ (x, 0) = 0.

(19)

1406

YIN H u a n d MARVIN H . WHITE

1 0.9

- ~ '

/',-

0.8

d

0.7

o •-

0.6

=

0.5

=

0.4

c ,*-'

0.3

=

0.2

o

0.1

==m

O

o

'

t

/

o

]-l

o

X=SA, Xot=20A

',,

\/

A--L0eV

i

il /

.... S ~ ,

' Dit = ' l ~ 0 [ e V cm'2

~\

/

/

.

~

I

i

,~

,

fO(DOstate)

\,~

lO • s 10"4 10"3 10 "2 10"l 10 0

,

,

,

10 1 10 2

,

10 3

10 4

I0 s

log (t) [sec] Fig. 6. The occupancy functions f - (D- state), f0 (D o state) as function of time, t, at distance x = 5 A from the SiO2/Si3N4 interface. Then, solving eqns (15) and (16), together with eqn (3), we obtain:

f-(x, t) = e -~" (x),,

(20)

f°(x, t) = m(x)[e-td(~)+~ C~)~'- e-~(~'], (21) with:

eO(x ) + cO(x ) . 1

Q,+Qi,+Qf V t h ( t ) = eMS "1- q~s

Co~ _qNT f x " ( X ' - x + X o b ~ Jo \

1

re(x) =

assuming a uniform trap density, Nx, in the nitride. Substituting eqns (21), (20) and (24) into cqn (23), we have:

(22)

e~ (x)

*.

Eo~/

x [1 - m(x)(e -"/'r T+,/~,-r~ _ e-,/w B) --2e -'/*v "] dx.

From eqns (20, 21), we can see that the occupancy functions of the D - and D Ostates depend upon the trap energy levels, ETA and ETD, the distance x, as well as the time t. Figure 6 shows the time dependence of the f-(x, t) and f°(x, t) at a fixed distance x = 5 ~ . F o r the traps located at 5 A away from the tunneling oxide and nitride interface, all the charges at D states tunnel to the Si conductance band within 10 ms, meanwhile, the D - states are totally converted to the D O states.

(25)

Differentiating both sides of the eqn (25) with respect to t and multiplying both sides by 2.3t, the threshold voltage decay rate becomes: 01ogt

J0 \

× [{2-m(x)} L

En

Cox/

t e-'/"-" "~T- B

+

')

2.2. Threshold voltage decay rate model From electrostatic considerations, the change of the threshold voltage Vth(t) after ERASE/WRITE cycling can be written for the SONOS transistor as [17]: ~ v~(t)

= 4~s + ¢,

Qs + Qit + Qf

_ I~ ° {x~-

x

+

xob\

.

)p.tx, t)dx, (23)

and the trapped charge in the nitride p,(x, t) is:

p. (x, t) = qNT[f +(x, t) -- f -(x, t)] = qNT[I --f°(x, t) -- 2f-(x, t)l,

(24)

x e - " m - v + 'J"-v)}] dx.

(26)

In the above threshold-voltage-decay rate equation, the time constants associated with the trap-to-band, trap-to-trap and band-to-trap tunneling processes arc related to the energy level ETA and ETD, the tunneling oxide thickness Xot, the barrier height for electrons and holes $] and $~ between the Si/SiO2 and $$ and qb~ between the SiO 2/Si3N4, and the distance from the SiO2/Si~N~ interface x. The first term in the bracket of eqn (26) is the threshold voltage decay rate contributed by electron tunneling from the nitride traps to the Si conduction band (trap-to-band tunneling), and the second term is the threshold voltage

Charge retention in memory devices decay rate contributed by both electron tunneling from the nitride traps to the Si/SiO2 interface traps (trap-to-trap tunneling) and hole injection from the Si valence band to the nitride traps (band-to-trap tunneling). The contribution from the trap-to-trap and band-to-trap tunneling processes are correlated in the threshold voltage decay rate equation. To emphasize the effect of each individual tunneling process on the threshold voltage decay rate, we will discuss one tunneling process at a time. Thus, the term:

1407

A. Trap-to-band and trap-to-trap tunneling processes: OVth(t) ., [ f X n - - x ; + Xob~(2--m,'~ 0 log------7- --2'3"q~vT[~ ' ~. Eo---~/\,'~. ]

X

~2"n,j(m"'](le-'/"r-'r)]

(30)

where: 1 T -'{-- t (.CT_

1- -'~e- t(l/¢T-'r ) + (1/~' - T), "~B-- T// Xi~-0~5

in the threshold voltage decay rate expression [eqn (25)] can be approximated by: t "~X- T

e-~YsY_~if we only consider the trap-to-trap tunneling process,

x;

= --

ln(-;--'3 ~TT_ B,/

,(,)

2q.

In

- -

Ti_ T

.

B. Trap-to-band and band-to-trap tunneling processes:

and: O log-------~~ -- 2.3. qNr

t t - - - e - , - f f ~ _ r if we only consider the "~-T band-to-trap tunneling process,

over the entire time and distance range. In addition, we notice that the ratio of zx- a to either TT- r or % _ x remains relatively constant throughout the entire nitride layer. Hence, we can replace re(x) in eqn (22) with m: 1

/f/ ~---mtt -~ _

1

_

e~

+ (X~--x;~.~ + Xob' 1 %~~(mbt' ] \ ~~](

where:

l(t 7

0[n

"~'- T

and: 1

for the band-to-trap m =mbt . ~ - 1 ~~B tunneling process, / TB-T

where: "~T- B = T T - B0 e'gxx°',

(27)

"f"T - T = '~T - To e2"°x Xo,,

(28)

~ - T = TB - To e'°b" Xo,.

(29)

In general, with ¢ ( x ) = z'e " : , as a function of the form: t

z(x) e-t/~x)' is sharply peaked around x = x'[32], where: x ' = 1 ln(t/¢'), so we can take the terra (X. - x)/~, + (Xob/Eo~) out of the integrand in eqn (26) and substitute x with x'. With the above approximations, we can obtain the following simplified expressions for the threshold voltage decay rate:

_ e_,nB_,)l,

(31)

x;=~ln

for the trap-to-trap ~ r - B tunneling process,

Eox]

•

~B-T]

The first term in eqns (30) and (31) represents the contribution of the electron back tunneling from the nitride traps to the Si conduction band (trap-to-band tunneling) and the second term denotes the contribution of electron back tunneling from the nitride traps to the Si/SiO2 interface traps (trap-to-trap tunneling) and hole injection from the Si valence band to the nitride traps (band-to-trap tunneling). Figures 7 and 8 show the threshold voltage decay rate as a function of time t with trap-to-band and trap-totrap tunneling processes and with trap-to-band and band-to-trap tunneling processes, respectively. The two figures are similar to each other, so we will confine our discussion to Fig. 7. From Fig. 7, we can clearly see that there are two decay stages: one results from the trap-to-band tunneling process, and the other results from the trap-totrap tunneling process. Each tunneling process is associated with a transient time constant *~'-B and • ~'-T, respectively (*~-T>Z~-B)- When t < * ~ - B , the threshold voltage decay rate is almost zero. When ~-B< t <~_T, the threshold voltage decay rate saturates to a value which is proportional to ( 2 - m . ) # t ~ , which is about the same as reported by Lundkvist et a!.[12], and Roy and White[18]. When t > "C-r_ T , the threshold voltage decay rate saturates to another value which is proportional to ( 2 - m t t ) / ~ + m . / 2 r h . Since both m. and ¢~'-r are

1408

YIN Hu and MpatvlN H. WHITE

~

.0.1 ~

e

~

ETA

.

] [-

.

.

.

.

.

EGN- ETA = 1.0 eV

"D -0.2 -0.3 ,.~

-0.4 -0.5 -0.6

.~

-0.7

.:1010 evcm

1

.o.s -0.9 -1

!

10 "610-5

10-410-3

10 -2 10 -110 0

!

101

102

103

R e a d D e l a y T i m e , log(t) [s] Fig. 7. The calculated threshold voltage decay rate, OVth(t)/alogt, as a function of time t. Only trap-to-band and trap-to-trap tunneling processes are included in the calculations. The threshold voltage decay rate reaches 0.05 V/dec after 10-4 s (due to the trap-to-band tunneling process) and decays again to 0.092 V/dec after 10-2s (due to both trap-to-band and trap-to-trap tunneling processes). The ONO dielectric thicknesses used in the calculation are: Xot = 20 ,~, X, = 68 A and Xob = 72 A. The trap density in the nitride layer is: NT= 2 × 10t9cm -3. related to the Si/SiO2 interface trap density, the Dit value can affect the threshold voltage decay rate in the long term retention.

3. SONOSDEVICEFABRICATION The surface-channel SONOS devices were fabricated with N M O S technology and LOCOS isolation on a p-type Si substrate. A 20 ~, thick tunnel oxide

EcN - ETA = 1.0 eV E r r - EVN = 1.0 eV

•~"~E~A l~r.

-0.1 ~,

is thermally grown in an ultra clean/dry triple wall oxidation system[5,34]. The purpose of using the triple wall oxidation system is to achieve a low latent Si/SiO2 interface state density so the SONOS device can sustain an extensive high electric field stress. A thin layer of LPCVD Si3N4 is then deposited, followed by a thin layer of LPCVD deposited blocking oxide. A 900°C, 30 min wet 02 is done at this stage to densify the LPCVD deposited blocking oxide.

-0.2 -0.3 .0.4

~x

"--" -0.5

~

-0.6

"~-

-0.7

~

-0.8 ~t

-0.9 -1

10

t

16 s

|

1'

10-4

I

10-3

|

16 2

161

i ,

10o

~

I

101

x

I

102

10 3

Read Delay Time, log(t) [s] Fig. 8. The calculated threshold voltage decay rate, 0l'/th(t)/O log t, as a function of time. Only trap-to-band and band-to-trap tunneling processes are included in the calculation. The threshold voltage decay rate with both trap-to-band and band-to-trap tunneling process reaches 0.05 V/dec after 10-4 s (due to the trap-to-band tunneling processes) and decays again to 0.09V/dec after 10-~s (due to both trap-to-band and band-to-trap tunneling processes). The ONO dielectric thicknesses used in the calculation are: Xot = 20A, Xn = 68A, and Xob = 72A. The trap density in the nitride layer is: N-r=2 x 1019cm-3.

Charge retention in memory devices After this wet 02 process, the nitridc layer will be reduced by about 5-10A and the thickness of the blocking oxide will increase by 5-10 A, due to the formation of a thin oxide layer between the nitride and blocking oxide. The final thicknesses of the composite ONO layers should be the effective thicknesses of the ONO layer after the wet 02 process. In addition, the temperature and time of this anneal process are critical for the trapping properties of the nitride layer[35,32]. The effective thickness of the ONO dielectric layers used in this paper are: Xo~=20A, X.=68A and Xob = 72A. A thick blocking-oxide layer is used in this work so that the electron or hole charge loss process by tunneling through the blocking oxide to the gate can be minimized. Immediately following the ONO gate dielectrics process, a 5kA thick polysilicon film is LPCVD deposited. After defining the gate area, the polysilicon in the gate regions (as well as the source/drain regions) is doped with a phosphorus diffusion using a POCL3 source. Thus the n + source/drain junctions and n + poly gate are formed. Figure 9 shows a photograph of the top view of a SONOS device. The buried-channel SONOS device used in this paper has the identical ONO dielectric thicknesses as the surface channel SONOS device. The buried channel is formed with an As implant: 40keV, 2.5 x 10~2cm-2, and activated at 900°C in a N~ ambient. The buried-channel implant condition is selected to form a normally off MOSFET in the

1409

BC SONOS Fig. 10. Buried channel SONOS device cross section written state. Figure 10 shows a cross section of the buried channel SONOS device. 4. SONOS DEVICE RETENTION CHARACTERIZATION

In this section, we present the experimental results on the charge retention of SONOS devices and compare the results to the analytical calculations. Based on the analytical modeling, we divide this section into two parts; one deals with the conventional surface n-channel SONOS devices which corresponds to the trap-to-band and trap-to-trap tunneling processes, and the other with the novel buried-channel SONOS devices which correspond to the trap-to-band and band-to-trap tunneling proceSSeS.

4,1. Retention characteristics of the conventional surface channel SONOS devices--trap-to.band and trap-to-trap tunneling Retention characteristics are measured when the gate, source/drain and bulk of the device are grounded after WRITE or ERASE. The threshold voltage of the device after WRITE or ERASE is measured after a read delay time. Figure I 1 shows the schematic diagram for the ERASE/WRITE and READ measurement setup and Fig. 12 shows the ERASE/WRITE and READ circuit diagram and its four corresponding measurement modes. An

[ITDT IZ IDS~ T46E~0IK GHP98'36OSC~'ISCOPE?~C IOMPUTER"[

ERASE/WRITE&READ ~ cmctJrr

Fig. 9. A photograph of the top view of a finished SONOS device. SSE ~ / I ~ D

I

[ '~[

PATrERN 1

"1O~.'U~R

Fig. I 1. The schematic diagram of the ERASE/WRITE measurement setup.

Yzt~ Hu and MARVZNH. Wxz~

1410

VDD

RD R I ~

,ol

~

...... I I~ ~I RI...~="

v.

Vow DUT sw2

CS.-'~"" IRE

RS

ol'iR]l[ 39K

K

. _ / 4 w3-1

IOD[

5V

39K

R1

SW3-2

VREF

__-!R1 ~R 1 Fig. 12. The circuit diagram of the ERASE/WRITE and READ circuit and its four measurement modes, Ref. [32].

HP-9836 computer is used to control the custom made pattern generator which provides the ERASE, WRITE, READ and IDLE pulses to the ERASE/ WRITE and READ circuit. The gate, source, drain and bulk of the device under test are connected to the ERASE/WRITE and READ circuit. To measure the retention after WRITE, the device is first erased with - 10 V applied on the gate for 10 s, and then written with + 10 V for a time to set the threshold voltage to the desired value. After a read delay time, the threshold voltage is measured by forcing a 10#A current into the source/drain junction and measuring the voltage of the source junction with Tektronix 7854 digitizing oscilloscope in the trigger mode. In order to minimize any "read disturb effect", we reset the initial state prior to each threshold voltage measurement. In a similar manner, the retention is measured after ERASE. The retention characteristics of the memory transistor represents how well a device can store the information after the device is erased or written. The retention data of the surface n-channel SONOS memory transistor are measured to compare with the analytical results. Figure 13 shows the threshold voltage decay rate as a function of time

calculated by the model and compared with the measured retention data from a surface n-channel SONOS memory transistor. Good agreements in both the short time period and long time period of the

1.3 1.2

#

1.1

E ~

' 0.9 0.8

0.7 0.6

0.$ I0 -8

calculated @

m~sur~

• ,

i

i

10-6

I0.4

I0 -2

I

i0 0

I

I0 2

I0 4

log (t) [s~) Fig. 13. The measured SONOS transistor retention data and calculated threshold voltage decay as a function of time. The SONOS transistor is a surface n-channel device with Xot = 20 A, X, = 68 A and Xob= 72 A. The device is programmed at 10 V initially and grounded during retention. The Si/SiO2 interface trap density of the measured device and for the calculated results is, Dit = 1 x 10meV-. cm-2.

Charge retention in memory devices 140

: 0

: calculated O measured

120

-0-6o 1010 1011 1012 Si/SiO2 interface trap Density, l~t [eV"1 cnf 2 ]

Fig. 14. The calculated and measured threshold voltage decay rate, DVth(t)/c3 log (t), as function of Si/SiO2 interface trap density, D~t,during retention. The Dit value is measured with a Charge-Pumping measurement after various number of ERASE/WRITE cycles. A surface n-channel SONOS device is used in the measurement, with Xot=20A, X, = 68 A and Xob= 72 A. retention are only possible by including the process of charge loss by electron back tunneling from the nitride traps to the Si/SiO2 interface traps. In the threshold voltage decay rate expression eqn (30), mtt is proportional to the Si/SiO2 interface trap density Dit. Therefore, when Dit increases, the threshold voltage decay rate also increases. We measured the retention data and the Si/SiO2 interface trap density data of a SONOS device after a number of ERASE/WRITE cycles and compared these results with the analytical calculations, as shown in Fig. 14. As the Si/SiO2 interface trap density increases from 101° to 1012eV -1 c m -2, the threshold voltage decay rate due to the trap-to-trap tunneling process (calculated by the analytical model) increases from 0.092 to 0.135 V/dec, although the calculated threshold voltage decays slower than the measured threshold voltage in the lower Dit range ( < 10j° eV -l cm-2). For the first time, the new model qualitatively predicts the relationship between the threshold voltage decay rate and the Si/SiO2 interface trap density.

4.2. Retention characteristics of the novel buried channel SONOS devices--trap-to-band and band-to-trap tunneling As mentioned in Section 1, the buried-channel SONOS structure reported has better data retention than the surface-channel SONOS structure. A comparison between the buried-channel and the surfacechannel device structures reveals that the potential profile and that the electric fields in the ONO dielectrics are very similar in these two different device structures. However, the potentials and electric fields in these two structures differ considerably in the vicinity of the semiconductor surface[5,17]. Figures 15 and 16 show the potential profile and electric fields of a buried channel and surface channel SONOS devices in the retention mode after WRITE and ERASE operations, simulated by a l D Poisson's solver. In the case of the buried channel structure in

1411

the retention mode after WRITE, the band bending near the surface forms a potential barrier because of the pn junction in the substrate. The height of this potential barrier increases as the buried-channel doping density increases. The presence of this potential barrier prevents holes from moving into the surface from the substrate so there are less holes available at the surface to be injected into the nitride. Therefore, we should expect better retention characteristics after WRITE for the buried channel structure. As shown in Fig. 8, the threshold voltage decay rate model B developed in Section 2 predicts the hole injection increases the threshold voltage decay rate in the long term retention. To verify that the buried channel SONOS devices have less hole injection from the Si valence band to the nitride traps in the retention after WRITE, we plot the measured threshold voltages as a function of the read delay time for both buried channel and surface channel experimental devices in Fig. 17. We notice that the threshold voltage decays at the same rate between the two devices up to 10 ms, which is the contribution from the electron back tunneling from the nitride traps to the Si conduction band (see Fig. 8). The two devices (surface and buried channel) have essentially the same Si/SiO 2 interface trap density since their tunneling oxides are grown with the same technology. Thus, the effect of electron tunneling from the nitride traps to the Si/SiO2 interface traps will be the same for the two devices and this tunneling process is ignored in the threshold voltage decay calculations for both devices. The thresholdvoltage decay rate after WRITE for the buriedchannel device is ~0.047V/dec after 10ms, while the threshold-voltage decay rate after WRITE for the surface channel device is ~0.087V/dec after 10 ms. The experimental data, therefore, agree with the prediction of the threshold-voltage decay rate model B developed in Section 2, namely, the buried channel SONOS device suffers less soft ERASE than its surface channel counterpart. 5. DISCUSSION As shown in the previous sections, the thresholdvoltage decay rate in the long term retention is affected by either the electron tunneling from the nitride traps to the Si/SiO2 interface traps, or the hole injection from the Si valence band to the nitride traps. Therefore, a reduction in the Si/SiOz interface trap density, Dit, and the amount of holes available at the Si surface for a given nitride trap distribution becomes the key approach to improve the retention characteristics of the SONOS memory transistors. Furthermore, a reduction in the Si/SiO2 interface trap density combined with a buried channel device structure will also improve the endurance of the SONOS devices. The endurance of a SONOS device is defined in terms of an unacceptable change in the device electrical properties (for example, program ability

1412

YIN Hu and MARVIN H. WHITE

1 WRITE

Xot=7.0~

0.8

x~--sM. Xob--4sA,

0.6 ~ . . _ . S C SONOS

0.4

%

(a)

0.2 N D=1x1017era'3

0

.. - ..............

',

SONOS

-0.2 ,i

-0.4

oo

"" - " ' " Si I SiO2

-0.6

~

N D =2xlOlTem____-3

I

I

lx10.5

I

I

2x10.5 3x10 5 4x10 .5 Bulk Distance, x [cm]

$x10.5

0,.4

ERASE

0.2

0

SC S O N O ~ f

-0.2

~.-"~*"~'~

Y'.~-;''-

N n •IxlOt?cm "3

(b)

-0.4 N D =2x1017cm'3 -0.6

-0.8

Xot=20~

-1

XNfS0~ Xobffi4S~

-1.2

Si / Si02

-1.4

I

I

.5

0

lxl0

I

.5

2x10

I

.$

3x10

.5

4x10

.5

5x10

Bulk Distance, x [cm] Fig. 15. The potential profile of the buried channel and surface channel SONOS device in the retention mode: (a) after WRITE, AQN = - l . 5 # C / c m 2 ; (b) after ERASE, A Q s = l.SpC/cm 2. Xot=20A, XN = 50 A and Xob = 45 A. The As implant conditions are: energy = 100 keV, dose = 1-2 x 10~2cm -2. The substrate doping density, N^ = 3 x 10~5cm -3. In the figure, the various As implant conditions have already been converted into different surface doping densities. Junction depths of buried channel layers are approximately 0.1 pro.

and retention) when the device is subjected to repetitive ERASE/WRITE pulses. The repetitive application of a high electric field in the tunneling oxide region can cause the formation of interface states near the Si/SiO2 interface[10,36] with sufficient density to accelerate the back tunneling of the charge stored in the nitride traps. Consequently, the decay rate of stored charge is increased and the memory retention is decreased. The formation of the interface states will also deteriorate the channel mobility of the device so the device may fail to deliver the required current during the read mode. This will affect both the ability to program the device as well as the retention of the device. Guided by the analytical prediction, two approaches are taken in this paper to improve the retention and endurance characteristics of SONOS

devices. First, we employ the triple-wall oxidation furnace system to grow the tunneling oxides. The triple-waU oxidation furnace eliminates the diffusion of heavy metal ions, mobile alkali ions and moisture from the quartz wall of the furnace during the oxidation. Thin gate oxides grown by the triple-wall oxidation process have low Si/SiO2 interface states and higher endurance to field stress[34]. Second, we employ a buried channel device structure to reduce the amount of holes available at the Si surface during the retention after WRITE. We have observed that the SONOS device with a tunneling oxide grown by the triple-wall oxidation system has a much lower initial trap density than the tunnefing oxide grown with a conventional singlewall oxidation system. Furthermore, as shown in Fig. 2, the Si/SiOe interface trap density of the

Charge retention in memory devices

1413

3.0

~

2.$

WRITE

BC SONOS

2.0

1.5 1.0 __~

0.S

................ NDdlXl017cm~. . . . . . . . . .

(a)

0

-0.S -1.0 -L$ -2.0 0

lxlO 4

2xlO 4

3xlO 4

4xlO 4

$xlO 4

6xlO4

Bulk Distance, x [cm] 2.5

2.0 I'1

IOl

N

"3

1.0

' ,

•

(b) -0.5

II o 0

I

xN=so,t

5 x 1 0 "7

lxl0 4

1 . $ x l 0 "6 2 x 1 0 "6 2 . 5 x 1 0 "6 3 x l O 6

Bulk Distance, x [cm] Fig. 16. The electric field of the buried channel and surface channel SONOS device in the retention mode: (a) after WRITE, AQ~ = - 1.5 ~C/cm2; (b) after ERASE, AQ~ = 1.5/~C/cm2. )tot = 20 A, XN= 50 A and Xob ~ 45 .~. The As implant conditions are: energy = 100 keV, dose = I-2 × 10.2cm -2. The substrate doping density, N^ = 3 × 10:5 cm =3. In the figure, the various As implant conditions have already been converted into different surface doping densities. Junction depths of buried channel layers are approximately 0.1 ~ m. triple-wall tunneling oxide SONOS device remains relatively unchanged in the early stage of the ERASE/WRITE cycling. This is in contrast with the rapid increase in the Si/SiO2 interface trap density of the single-wall tunneling oxide SONOS device. This comparison clearly demonstrates the excellent reliability of the tunneling oxide grown in the ultraclear/dry triple-wall oxidation system. We have also compared the charge retention characteristics of the two types of SONOS devices. Measurements have shown the charge retention changes from 0.080 V/dec to 0.086 V/dec for the triple-wall tunneling oxide SONOS device after l0 z ERASE/WRITE cycles, and from 0.087 V/dec to 0.103 V/dec for the singie-wall tunneling oxide SONOS device[37]. Figure 18 shows the charge retention characteristics of both SONOS devices with tunneling oxides grown by triple-wall

and single-wall oxidation systems after 106 ERASE/ WRITE cycles. For the buried channel SONOS devices, the improvement in the charge retention is already shown in Section 4. In addition, we have also observed good endurance characteristics from the buried channel SONOS device. The buried channel SONOS device structure circumvents the mobility degradation problem, arising from the extended number of ERASE/WRITE cycles, since the conducting channel is formed in the ion implanted region away from the surface. Therefore, scattering from Coulombic centers in the Si/SiO2 interface have less impact on the channel current of buried channel device. Figure 19 compares the transconductance of both surface channel and buried channel SONOS devices. The peak value of the transconductance of the buried channel

YIN HU and MARVIN H. WroTE

1414

~

1.5 1.0

S 10V 30ms 0.8 V

0.5 E

I

o -0.5 -1.0 10 years -1.5

I

I

I

I

I

I

I

10-4

162

100

102

104

106

l0 s

Read Delay Time [s] Fig. 17. The measured retention characteristics of buried channel and surface channel SONOS devices. The two devices have the same ONO dielectric thicknesses. )tot = 20 ,~, X, = 68 JL and Xob = 72 JL. The programming voltage for both devices is: + I0 V for the WRITE and - I0 V for the ERASE. The buried channel is formed by an As implant: 40 keV, 2.5 x I0 ~2cm -2. The threshold voltage of the buried channel SONOS device decays slower than the threshold voltage of the surface channel due to the reduction of hole injection from the Si valence band to the nitride traps.

S O N O S device is 42% higher than the peak value of the transconductance of the surface channel S O N O S device. Measurement results also indicate, after 106 E R A S E / W R I T E cycles, that the transconductance of the buried channel device remains relatively unchanged, while the transconductance of the surface channel device has degraded by 14%. Therefore, the buried channel S O N O S device has less mobility degradation than the surface channel S O N O S device

|

1.4 1.2 1

0.4

i

!

t

ol

i

Xot=20,A single-wall oxidation Xn=73Ao ---e

- - -t - - 1~. *

0.8 0.6

t

under extensive E R A S E / W R I T E cycling. Figure 20 shows the endurance characteristics of the buried channel device. In the same figure, we also plot the threshold voltage after W R I T E and E R A S E at various read delay times. This figure shows that the buried channel S O N O S device not only can sustain a larger number of E R A S E / W R I T E cycles but also maintain a good memory window at 100 s of read delay time.

I

/

~

I

Xob=~A ~ a - - . e O . 1 0 3 . . V/dec

/

"-a

Xot--2?

0.086 V/dec

Xob=72,l.

O.2 I

I

10"s 10 .4

I

I

I

I

10 .3 10 "2 10 "1 100

i

101

i

102

103

Read Delay Time [s] Fig. 18. The retention characteristics of both SONOS devices with tunneling oxides grown by triple-wall and single-wall oxidations. The measurements were made after 10~E/W cycles. The cycling and measurement conditions for the triple-wall tunneling oxides are: + 10 V, 20 ms; - 10 V, 150 ms. The cycling and measurement conditions for the single wall tunneling oxides are: +9 V, 3 ms; - 9 V, 30 ms. Both devices have the same width to length ratio; W/L = 150#m/10/~m.

Charge retention in memory devices i

1.4x10 "4

!

w

i

VDS=S0mV

1.2x10.4

1415

i

i

i

BC SONOS

,--. l ' O x l O ' 4

/

~

8.0xlO -s 6.0x10 "s

////

4.0xlO "s

~'~'''''"

/

2.0x10 "s /

-2

I

LJ

-1.5

-1

~

I

I

I

-0.5

0

0.5

I

I

1

1.5

2

V~s [V] Fig. 19. The transconductance of a buried channel and a surface channel SONOS device measured before any programming. The drain voltage, Vas, in the measurement is 50 inV. The peak value of the transconductance of the buried channel device is 42% higher than the surface channel device. Both devices have the same width to length ratio: W/L = 150/~m/10/~m.

valence band to the nitride traps. A comparison of our model prediction with the experimental retention data from both surface channel and buried channel SONOS devices shows good agreement for the threshold voltage decay rate in the retention mode. The model qualitatively predicts the threshold voltage decay rate increases with the increasing of the Si/SiO2 interface trap density. The model also predicts the threshold voltage decays less without hole injection from the Si valence band to the nitride traps. In summary, by adopting the buried-channel structure and a good preparation of the tunneling oxide, we can improve both retention and endurance

6. CONCLUSIONS In this paper, we have presented a new analytical model for the threshold voltage decay rate in the retention mode for SONOS NVSM devices, which includes three major charge loss processes in the SONOS memory devices. We have shown that the electron back tunneling from the nitride traps to the Si conduction band dominates the short term charge retention (1/~s-I ms) and the charge loss for the long term retention ( > 1 ms) is governed by either electron back tunneling from the nitride traps to the Si/SiO2 interface traps or hole injection from the Si

2 1.5

1

•

.

=

•

•

i

-

i

.

i

V w = I O V t w = 5 1 ms lOlp.s ~o is .~. 11s A---= lOl s =',,

I"1

+

+

t'l

?

O.5

0

,II

T

-0.5

~--

o

f/

-1

"-

o VE=-IOV

~,~

tE=51ms

-1.5 •

r

.

I

,

I

.

.

i

.

.

i

.

.

"2

101

10 2

10 3

10 4

10 5

10 6

10 7

N u m b e r o f E/W Cycles Fig. 20. The endurance measurement of a buffed channel SONOS device. The ONO dielectric thickness is:"got= 20 ,~,, X, = 68 ,~ and "gob= 72 .~. The width to length ratio of the device is: W/L = 48 #m/12/tm. The E/W cycling conditions are: + I0 V, 51 ms; - 1 0 V, 51 ms. The threshold voltage after WRITE and ERASE operations is measured at various read delay times.

1416

YIN Hu and MARVIN H. WHITE

characteristics for S O N O S memory transistors. In addition, the trap distribution in the nitride also has a great impact on the retention characteristics of S O N O S devices. The farther the traps are located from the interface of tunneling oxide and nitride, the longer the time is needed for stored charges tunneling to the Si surface and the better the retention will be for the device. Acknowledgements--The authors would like to express their appreciation to Amit Banerjee for help with the measurements and Bill Wagner for the development of the Poisson solver used in the simulations.

REFERENCES

1. H. E. Maes, G. Groeseneken, H. Lebon and J. Witters, Microelectron. J. 20, 9-58 (1989). 2. U. Sharma, R. Moazzami, P. Tobin, Y. Okada, S. Cheng and J. Yeargain, IEDM Technical Digest, p. 461. San Francisco, Calif. (1992). 3. E. Suzuki et al., IEEE Trans. Electron Devices ED-38, 122 (1983). 4. F. R. Libsch, A. Roy and M. H. White, IEEE Device Research Conf., Santa Barbara, Calif. (1987). 5. Y. Hu and M. H. White, in 50th IEEE Device Research Conf., Cambridge, Mass. (1992). 6. M. French, C. Y. Chen and M. H. White, in 12th IEEE Nonvolatile Semiconductor Memory Workshop, Monterey, Calif. (1992). 7. T. Nozaki, T. Tanaka, Y. Kijiya, E. Kinoshita and T. Tsuchiya, IEEE J. Solid-State Circuits 26, 497-501 (1991). 8. Y. Kamigaki et al., 1EEE J. Solid State Circuits 24, 1714 (1989). 9. M. H. White and J. R. Cricchi, 1EEE Trans. Electron Devices ED-19, 1280 (1972). 10. M. H. White, J. W. Dzimianski and M. C. Peckerar, IEEE Trans. Electron. Devices ED-24, 577 (1977). 11. S. Minami, Y. Kamigaki and K. Uchida, Jap. J. appl. Phys. 27, L2168 (1988). 12. L. Lundkvist, I. Lundstrom and C. Svensson, Solid-St. Electron. 16, 811 (1973).

13. K. Lehovec and A. Fedotowsky, Appl. Phys. Lett. 32, 335 (1978). 14. G. L. Heyns and H. E. Maes, in Proc. Fifth Int. Conf. on Insulating Films on Semiconductors, p. 154, Leuven, Belgium (1987). 15. K. I. Lundstrom, S. Christensson and C. M. Svensson, Physica status solidi (a) 1, 395 (1970). 16. D. Frohman-Bentchkowsky and M. Lenslinger, J. appl. Phys. 40, 3307 (1969), 17. Yin Hu, Ph.D. thesis, Lehigh University (1992). 18. A. Roy and M. White, Solid-St. Electron. 34, 1083 (1991). 19. C. Arnett and B. H. Yun, Appl. Phys. Lett. 26, 94 (1975). 20. K. Lehovec and D. W. Crain, J. appl. Phys. 47, 2763 (1976). 21. K. L. Ngai and Y. Hsia, Appl. Phys. Lett. 41, 159 (1982). 22. S. Fujita and A. Sasaki, J. electrochem. Soc. 132, 398-402 (1985). 23. J. Robertson and M. Powell, Phil. Mag. B 44, 2, 215 (1981). 24. D. T. Krick, P. M. Lenahan and J. Kanicki, Phys. Rev. B 38, 8226-8229 (1988). 25. M. H. White and C. C. Chao, J. appl. Phys. 57, 2318 (1985). 26. D. T. Krick, P. M. Lenahan and J. Kanicki, J. appl. Phys. 64, 3558 (1988). 27. P. M. Lenahan and S. E. Curry, Appl. Phys. Lett. 56, 157 (1990). 28. W. Shockley Jr and W. Read, Phys. Rev. 87, 835 (1952). 29. R. N. Hall, Phys. Rev. 87, 387 (1952). 30. C. Svensson and I. Lundstrom, Electron. Lett. 6, 645~47 (1970). 31. I. Lundstrom and C. Svensson, J. appl. Phys. 43, 5045 (1972). 32. A. Roy, Ph.D. thesis, Lehigh Univ. (1989). 33. C. Svensson and I. Lundstrom, J. appl. Phys. 44, 4657 (1973). 34. S. Yoon and M. White, J. Electron. Mater. 19, 487-493 (1990). 35. F. R. Libsch, Ph.D. thesis, Lehigh Univ. (1989). 36. E. Suzuki and Y. Hayashi, J. appl. Phys. 52, 6377-6385 (1981). 37. Y. Hu, A. Banerjee and M. H. White, in poster presentation at 23rd IEEE Semiconductor Interface Specialist Conf., San Diego, Calif. (1992).