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Charge trapping in MOS systems
Thin Solid Films-Elsevier Sequoia S.A., Lausanne-Printed in Switzerland
1
CHARGE TRAPPING IN MOS SYSTEMS*
D. J. BREED AND R. P. KRAMER Philips Research Laboratories, Eindhoven (The Netherlands) (Received May 17, 1972)
Measurements on MOS capacitors and MOS transistors at room temperature and 77 K lead to the conclusion that large slow-trapping effects can occur at the Si-SiO 2 interface at room temperature. These "slow state" effects differ substantially from the" slow state" effects usually observed in the Si-SiO 2 system.
When MOS (metal--oxide-silicon) capacitors are cooled from room temperature to 77 K, the C-Vcurve (differential capacitance as a function of d.c. voltage) shifts along the voltage axis, due to surface states 1. We have observed, however, that the voltage shift greatly depends on the bias applied to the sample at room temperature and during cooling. This is shown in Fig. 1 for a p-type sample. It is not possible to produce these shifts by applying a high negative voltage at 77 K. We have therefore concluded that these shifts are not connected with "fast interface states" and that the charging of the traps causing these shifts is a thermally activated process z. Since the shifts increase with increasing voltage across the oxide, it is most likely that the traps are located in the SiO2. The voltage shift increases with the length of time for which the sample is biased at room temperature and therefore we conclude that the charge trapping observed at 77 K occurs already at room temperature. The shifts observed in p-type samples are stable at 77 K. At this temperature thermal generation of charge carriers is negligible. However, if electrons are generated, for example by the incidence of visible light on the sample, the shifts disappear for the most part. This suggests that the traps interact with the conduction band of the silicon. It is found that p-type and n-type samples behave very differently after cooling to 77 K. This can be seen in Fig. 2, where the voltage shift of the C - V curve after cooling with bias is plotted as a function of that bias. The samples had been prepared in the same way as the sample of Fig. 1. The shifts depend strongly on the method of preparation of the oxide and are also observed in MOS structures obtained by standard processing. For example, from silicon oxidized in dry oxygen at 1150 °C only, MOS capacitors are obtained for which the shifts are similar to but about five times smaller than the shifts shown in Fig. 2. * Paper presented at the International Conference on Thin Films, "Application of Thin Films ", Venice, Italy, May 15-19, 1972; Paper 8.1.
Thin Solid Films, 13 (1972) 1-4
2
D.J.
36
,
,
BREED,
R.
P.
KRAMER
T
30 C(pF)
T 10
o
• o + A r e
-20V -30V -40V -50V -60V -70V -B0V -90V -lOOV
o60
20
-50
-
-3o
-io
-;o
o
V (Volt)
Fig. 1. C - V plots measured at 77K from accumulation ( - 3 0 V or more negative still) to deep depletion with a p-type sample (p--_3 x 1015 cm-3). The sample was biased, at room temperature for 30 s and during cooling, with the gate voltages indicated in the figure. For comparison the room temperature C - V plot is given.
J -5
• p-MOS (p:3.1Ol~'cm 3 } o n-MOSln=8*lOl~/cm 3) orientation :( III ) gate oxide: oxidized 80"at 1150"C*60'at 600"C in dry oxygen gate material : AI
-10
AV measured cat 77K
D, VglVolt) -15
-5;
'
'
'
'
0
'
'
50
Fig. 2. The shift AV of C V curves measured at 77 K with a p-type and an n-type sample ( p - 3 xl015 cm -3, n-~8 xl014 cm-3), plotted as a function of V~, the gate voltage applied to the sample at room temperature and during cooling. The oxide thickness is about 2000 A.
The difference between n-type and p-type samples can be explained by assuming that the traps are discharged as soon as free electrons are present at the surface. In p-type samples this will not occur, since the thermal generation of electrons is totally negligible at 77 K. It must be emphasized that the C - V curves are always measured from accumulation to deep depletion (no minority charge carriers). To check this explanation we measured the threshold voltage shift of a p-channel (n-substrate) MOS transistor as a function of the gate voltage applied at room temperature and during cooling. It is possible to observe the shift of the threshold voltage without first going to accumulation. At the same time one can Thin Solid Films, 13 (1972) 1-4
CHARGE TRAPPING IN M O S
SYSTEMS
3
measure whether the trapped charge disappears on the application of an accumulation voltage to the gate of the MOS transistor. In Fig. 3 the results are shown for such an MOS transistor, the MOS capacitor of which had been prepared in the same way as the other MOS capacitors quoted in this paper. It can be seen from the figure that the observed threshold voltage shifts agree reasonably well with the shifts observed in the p-type MOS capacitor (Fig. 2). The threshold voltages observed after short-circuiting the gate to the bulk for about 0.5 s and 30 s, respectively, are also plotted. Threshold voltages obtained after longer times or stronger accumulation voltages differ only slightly from the threshold voltages shown in the latter curve. From a comparison of Figs. 2 and 3 one may conclude that the difference between n-type and p-type samples shown in Fig. 2 is due largely to the method of measuring the trapped charge in this case. On the other hand, the residual shift shown in Fig. 3 is about four times larger than the shift observed in the n-type MOS capacitor. This is not yet understood. The difference may be due to differences of the two samples or to the fact that states are created at large negative voltages at room temperature, behaving at 77 K like "fast interface states". If these states do not disappear when electrons are present at the surface, they will influence the shift of the threshold voltage of the MOS transistor and the shift of the C-V curve of the MOS capacitor in different ways. In conclusion, in p-type and n-type samples large positive charge trapping effects can occur at room temperature. This charge trapping can easily be observed by cooling to 77 K. The charging of the traps 2 is reminiscent o f " slow states -3, 4 If electrons are present at the silicon surface, the discharging of the traps can be -16
p-channel MOST I n - 8x101~cma :
-20
orientotion : ( Ill ] gate oxide: oxidized 90"at 1150"C,60'at 600"C in dry oxygen gate material: AI
-25
Vr.( 77K 1: • measured after cooling ÷ . . . . Vg =0 during 0.5s o .. after Vg = 0 during 30s
-30
V¢ (Volt) -35
-S0
0
5O
Fig. 3. Threshold voltage VTn of an MOS transistor measured at 77 K as a function of the gate voltage applied to the sample at room temperature and during cooling. For VTn we have taken the gate voltage at which a channel current of 10 -5 A is measured with a drain voltage of 0.5 V. The channel is about 400 ~tm long and 2500 Ixm wide. The oxide thickness is about 2000 A. Thin Solid Films, 13 (1972) 1-4
4
D.J.
BREED, R. P. KRAMER
very fast in our case, and therefore we conclude that the observed charge trapping differs substantially from the "slow state" effects usually observed. REFERENCES 1 P.V. Gray and D. M. Brown, Appl. Phys. Letters, 8 (1966) 31. 2 D.J. Breed and R. P. Kramers, Appl. Phys. Letters, to be published. 3 A. Many, Y. Goldstein and N. B. Grover, Semiconductor Surfaces, North-Holland Publ. Co., Amsterdam, 1965. 4 S.R. Hofstein, Solid State Electron., 10 (1967) 657.
Thin Solid Films, 13 (1972) 1 4
1
CHARGE TRAPPING IN MOS SYSTEMS*
D. J. BREED AND R. P. KRAMER Philips Research Laboratories, Eindhoven (The Netherlands) (Received May 17, 1972)
Measurements on MOS capacitors and MOS transistors at room temperature and 77 K lead to the conclusion that large slow-trapping effects can occur at the Si-SiO 2 interface at room temperature. These "slow state" effects differ substantially from the" slow state" effects usually observed in the Si-SiO 2 system.
When MOS (metal--oxide-silicon) capacitors are cooled from room temperature to 77 K, the C-Vcurve (differential capacitance as a function of d.c. voltage) shifts along the voltage axis, due to surface states 1. We have observed, however, that the voltage shift greatly depends on the bias applied to the sample at room temperature and during cooling. This is shown in Fig. 1 for a p-type sample. It is not possible to produce these shifts by applying a high negative voltage at 77 K. We have therefore concluded that these shifts are not connected with "fast interface states" and that the charging of the traps causing these shifts is a thermally activated process z. Since the shifts increase with increasing voltage across the oxide, it is most likely that the traps are located in the SiO2. The voltage shift increases with the length of time for which the sample is biased at room temperature and therefore we conclude that the charge trapping observed at 77 K occurs already at room temperature. The shifts observed in p-type samples are stable at 77 K. At this temperature thermal generation of charge carriers is negligible. However, if electrons are generated, for example by the incidence of visible light on the sample, the shifts disappear for the most part. This suggests that the traps interact with the conduction band of the silicon. It is found that p-type and n-type samples behave very differently after cooling to 77 K. This can be seen in Fig. 2, where the voltage shift of the C - V curve after cooling with bias is plotted as a function of that bias. The samples had been prepared in the same way as the sample of Fig. 1. The shifts depend strongly on the method of preparation of the oxide and are also observed in MOS structures obtained by standard processing. For example, from silicon oxidized in dry oxygen at 1150 °C only, MOS capacitors are obtained for which the shifts are similar to but about five times smaller than the shifts shown in Fig. 2. * Paper presented at the International Conference on Thin Films, "Application of Thin Films ", Venice, Italy, May 15-19, 1972; Paper 8.1.
Thin Solid Films, 13 (1972) 1-4
2
D.J.
36
,
,
BREED,
R.
P.
KRAMER
T
30 C(pF)
T 10
o
• o + A r e
-20V -30V -40V -50V -60V -70V -B0V -90V -lOOV
o60
20
-50
-
-3o
-io
-;o
o
V (Volt)
Fig. 1. C - V plots measured at 77K from accumulation ( - 3 0 V or more negative still) to deep depletion with a p-type sample (p--_3 x 1015 cm-3). The sample was biased, at room temperature for 30 s and during cooling, with the gate voltages indicated in the figure. For comparison the room temperature C - V plot is given.
J -5
• p-MOS (p:3.1Ol~'cm 3 } o n-MOSln=8*lOl~/cm 3) orientation :( III ) gate oxide: oxidized 80"at 1150"C*60'at 600"C in dry oxygen gate material : AI
-10
AV measured cat 77K
D, VglVolt) -15
-5;
'
'
'
'
0
'
'
50
Fig. 2. The shift AV of C V curves measured at 77 K with a p-type and an n-type sample ( p - 3 xl015 cm -3, n-~8 xl014 cm-3), plotted as a function of V~, the gate voltage applied to the sample at room temperature and during cooling. The oxide thickness is about 2000 A.
The difference between n-type and p-type samples can be explained by assuming that the traps are discharged as soon as free electrons are present at the surface. In p-type samples this will not occur, since the thermal generation of electrons is totally negligible at 77 K. It must be emphasized that the C - V curves are always measured from accumulation to deep depletion (no minority charge carriers). To check this explanation we measured the threshold voltage shift of a p-channel (n-substrate) MOS transistor as a function of the gate voltage applied at room temperature and during cooling. It is possible to observe the shift of the threshold voltage without first going to accumulation. At the same time one can Thin Solid Films, 13 (1972) 1-4
CHARGE TRAPPING IN M O S
SYSTEMS
3
measure whether the trapped charge disappears on the application of an accumulation voltage to the gate of the MOS transistor. In Fig. 3 the results are shown for such an MOS transistor, the MOS capacitor of which had been prepared in the same way as the other MOS capacitors quoted in this paper. It can be seen from the figure that the observed threshold voltage shifts agree reasonably well with the shifts observed in the p-type MOS capacitor (Fig. 2). The threshold voltages observed after short-circuiting the gate to the bulk for about 0.5 s and 30 s, respectively, are also plotted. Threshold voltages obtained after longer times or stronger accumulation voltages differ only slightly from the threshold voltages shown in the latter curve. From a comparison of Figs. 2 and 3 one may conclude that the difference between n-type and p-type samples shown in Fig. 2 is due largely to the method of measuring the trapped charge in this case. On the other hand, the residual shift shown in Fig. 3 is about four times larger than the shift observed in the n-type MOS capacitor. This is not yet understood. The difference may be due to differences of the two samples or to the fact that states are created at large negative voltages at room temperature, behaving at 77 K like "fast interface states". If these states do not disappear when electrons are present at the surface, they will influence the shift of the threshold voltage of the MOS transistor and the shift of the C-V curve of the MOS capacitor in different ways. In conclusion, in p-type and n-type samples large positive charge trapping effects can occur at room temperature. This charge trapping can easily be observed by cooling to 77 K. The charging of the traps 2 is reminiscent o f " slow states -3, 4 If electrons are present at the silicon surface, the discharging of the traps can be -16
p-channel MOST I n - 8x101~cma :
-20
orientotion : ( Ill ] gate oxide: oxidized 90"at 1150"C,60'at 600"C in dry oxygen gate material: AI
-25
Vr.( 77K 1: • measured after cooling ÷ . . . . Vg =0 during 0.5s o .. after Vg = 0 during 30s
-30
V¢ (Volt) -35
-S0
0
5O
Fig. 3. Threshold voltage VTn of an MOS transistor measured at 77 K as a function of the gate voltage applied to the sample at room temperature and during cooling. For VTn we have taken the gate voltage at which a channel current of 10 -5 A is measured with a drain voltage of 0.5 V. The channel is about 400 ~tm long and 2500 Ixm wide. The oxide thickness is about 2000 A. Thin Solid Films, 13 (1972) 1-4
4
D.J.
BREED, R. P. KRAMER
very fast in our case, and therefore we conclude that the observed charge trapping differs substantially from the "slow state" effects usually observed. REFERENCES 1 P.V. Gray and D. M. Brown, Appl. Phys. Letters, 8 (1966) 31. 2 D.J. Breed and R. P. Kramers, Appl. Phys. Letters, to be published. 3 A. Many, Y. Goldstein and N. B. Grover, Semiconductor Surfaces, North-Holland Publ. Co., Amsterdam, 1965. 4 S.R. Hofstein, Solid State Electron., 10 (1967) 657.
Thin Solid Films, 13 (1972) 1 4