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Modulation of charge trapping and current-conduction mechanism of TiO2-doped HfO2 gate dielectrics based MOS capacitors by annealing temperature
Journal of Alloys and Compounds 647 (2015) 1054e1060
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Modulation of charge trapping and current-conduction mechanism of TiO2-doped HfO2 gate dielectrics based MOS capacitors by annealing temperature J.W. Zhang a, G. He a, *, H.S. Chen a, J. Gao a, X.F. Chen a, P. Jin a, D.Q. Xiao a, R. Ma b, M. Liu b, Z.Q. Sun a a
School of Physics and Materials Science, Radiation Detection Materials & Devices Lab, Anhui University, Hefei 230601, PR China Key Laboratory of Materials Physics, Anhui Key Laboratory of Nanomaterials and, Nanostructure, Institute of Solid State Physics, Chinese Academy of Sciences, Hefei, 230031, PR China
b
a r t i c l e i n f o
a b s t r a c t
Article history: Received 27 April 2015 Received in revised form 1 June 2015 Accepted 5 June 2015 Available online 17 June 2015
Current conduction mechanisms of Hf1xTixO2-gated metaleoxideesemiconductor (MOS) capacitors depending on various post-annealing temperature (PDA) have been investigated. The sample subjected to 400 C annealing exhibits superior performance with negligible hysteresis memory window shift (DVfb ¼ 0.005 V) and lowest gate leakage current density (5.4 105 A/cm2 at Vg ¼ 2 V). In addition, evolution of density of interface traps (Dit), border charger density (Not) and oxide charge density (Qox) as a function of annealing temperature were investigated in details. Detailed electrical measurements reveal that the dominant current conduction behaviors are PooleeFrankel (PeF) emission in the region of low electric fields and Schottky Emission (SE) in the region of high electric fields for gate injection. For substrate injection, however, is mainly via Ohm's conduction, Schottky emission (SE) conduction mechanism serves in low applied field in the samples, respectively. © 2015 Elsevier B.V. All rights reserved.
Keywords: High-k gate dielectrics TiO2-doped HfO2 Puttering Current-conduction mechanism
1. Introduction Metal gate/high-dielectric-constant (high-k) dielectric stacked films are a promising candidate of conventional silicon dioxide SiO2 layer to enhance the performances of metal oxide semiconductor (MOS) devices with the shrinking of the gate length and gate dielectric thickness [1e6]. Hf-based high-k gate dielectrics are very promising among some potential high-k candidates. However, one of the main concerns about pure HfO2 is the density of active traps at and near the high-k dielectric/Si interface which is higher than the density of traps at SiO2/Si interface, which can act as significant scattering centers for carriers and increase the interface-state density (Dit) [7]. In the past decades Hf-based gate dielectric materials, such as, HfTaO, HfTiO, HfZrLaO, HfLaO dielectrics, have been paid more attention due to their thermodynamic stability with silicon channels, preferable band offsets, and reasonably high dielectric constants [8e11]. Especially, the incorporation of titanium element into HfO2 has attracted considerable attention
* Corresponding author. E-mail address: [email protected] (G. He). http://dx.doi.org/10.1016/j.jallcom.2015.06.042 0925-8388/© 2015 Elsevier B.V. All rights reserved.
because TiO2 has a high dielectric constant (k ~ 80), and a high electron barrier to Si [12,13]. Ye et al. have shown that the introduction of TiO2 into HfO2 demonstrates the increased crystallization temperature (>700 C) and improved microstructure including interface, surface and amorphous properties [14]. The concept of doping can be understood that the dopants act as network modifiers, compensate the oxygen vacancies in metal oxides, and by this way reduce the leakage current and trap density. By far, although there exists significant material performance improvement by TiO2-incorporation into HfO2, annealing temperature dependent detailed charge trapping and current-conduction mechanism, such as trapped oxide charges, interface trap density (Dit), leakage current behavior of TiO2-doped HfO2 gate dielectrics based MOS capacitors, in particular, have not been systematically investigated. The variation of electrical characteristics of capacitors with temperature will, to a large extent, influence its capacitance and gate leakage current, hence the circuit performance. In this work, the effect of annealing temperature on the CeV characteristic and gate leakage current of MOS capacitors based on Hf1xTixO2 gate dielectric has been investigated. What's more, a special focus of current study is to reveal the mechanism of temperature dependence of tunneling in all field regions.
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2. Experimental details A commercially purchased n-doped Si wafer with a doping concentration of 1 1015 cm3, epitaxial thickness of 1 mm was chosen as the substrates. Prior to Hf1xTixO2 gate dielectric deposition, the wafers were ultrasonically cleaned with acetone and alcohol in sequence for 10 min to remove residues and contaminants, and than etched in a diluted hydrofluoric solution to remove native oxide on the surface, leaving an H-terminated surface. After cleaning, the composite targets (Hf1xTixO2, with 60 mm in diameter and 5 mm in thickness) sintered at high temperature with the mixing proportion of HfO2 (99.99% purity) and TiO2 (99.99% purity) was used as sputtering target to deposit film and the mass percent concentration of TiO2 in the targets is 3%. Hf1xTixO2 gate dielectrics with thickness of about 20 nm confirmed by spectroscopic ellipsometry (SC630, SANCO Co, Shanghai) were deposited by sputtering equipment (JGPDZS, Chinese Academy of Sciences, Shenyang Scientific Instrument Co., Ltd), in an Ar ambient with a RF power of 60 W. To obtain the thickness of the films accurately, the CauchyeUrbach dispersion model was used to fit the data with a threelayer-structured optical model structure (Hf1xTixO2/SiO2/Si) during fitting process. Subsequently, post-deposition annealing (PDA) using rapid thermal annealing (RTA) system was performed under a vacuum atmosphere for 60 s at 400, 600, and 800 C, respectively. In order to explore the electrical properties, Al/Hf1xTixO2/n-Si/Al MOS capacitors were fabricated by sputtering a Al top electrode through a shadow mask with an area of 7.065 104 cm2 and the back surfaces of all samples were deposited with a 200-nm-thick Al film by sputtering after the back surface oxide stripping to decrease contact resistance, as schematically shown in Fig. 1. A semiconductor device analyzer (Agilent B1500A) combined with Cascade Probe Station was used for CeV measurement at room temperature. Short circuit and open circuit calibration were performed before real measurements. Sinusoid signals with different frequency range from 600 kHz to 1 MHz were superimposed upon a direct current (DC) voltage which was applied between top and bottom electrodes. And the DC voltage was swept from negative to positive or back and forth to perform single and double sweeps. Additionally, the leakage current properties were measured by B1500A. All the electrical characterization was performed at room temperature in a shielded dark box.
Fig. 2. High frequency (1 MHz) capacitanceevoltage curves for as-deposited Hf1xTixO2 thin film and annealed ones at 400 C, 600 C and 800 C.
3. Results and discussion 3.1. Electrical analyses of the Al/Hf1xTixO2/n-Si MOS devices The dependence of high-frequency (1 MHz) CeV characteristics on the annealing temperatures, swept from 2 V to 1.5 V, is depicted in Fig. 2. The gate voltage was swept from inversion to accumulation region and vice versa to check the magnitude of hysteresis. Holes are tunneling from the substrate to the thin film when it is applied a negative voltage at the gate, and when applied a positive voltage at the gate, electrons from the substrate are tunneling to the thin film. The steeper CeV curves found in depletion layer indicate the lower interface state densities and the existed small hysteresis. It is well known that the semiconductor surface layer will deviate from the flat band condition because the internal electrical charges produce field in high dielectric material. The shielding distance or band bending region is known as extrinsic Debye length LD which is formulized by Refs. [15,16],
sffiffiffiffiffiffiffiffiffiffiffi KT3s LD ¼ q2 Na
where Na is the doping concentration in semiconductor, 3s is the semiconductor permittivity (11.9), k is Boltzmann constant. The flat band capacitance Cfb with the above extrinsic Debye length LD is given by Refs. [17],
Cfb ¼
1 Cox
1 þ C1s
Cs ¼ ðA3o KÞ=LD
Fig. 1. Schematic of the structure of Al/Hf1xTixO2/n-Si capacitors. Gate voltages are applied for substrate injection and gate injection.
(1)
(2)
(3)
here, Cox is oxide layer capacitance, Cs is semiconductor capacitance. The corresponding flat band voltage Vfb values to Cfb were extracted from the respective CeV curves. It is clearly visible that the accumulation capacitance (Cox) is reduced after PDA, which can be due to the reduction of the dielectric constant with increased annealing temperature. The effective dielectric constants of Hf1xTixO2 films at room temperature, 400, 600, and 800 Cannealed were 19.2, 18.2, 18.0 and 17.7, respectively. The evolution of the dielectric constant related with annealing temperature can be attributed to the microstructure change, such as crystalline, interfacical structure referring mainly to the notable increment of the SiO2 and Hf-silicate interfacial layer thickness due to the Hf diffusion into SiO2, accompanying Si up-diffusion into the high-k dielectric [13,18]. In general, a lower-k interface layer thickness increasing at higher PDA temperatures will lead to lowering Cox,
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which in turn results in an increase in equivalent oxide thickness (EOT), which is undesirable to the final electrical characteristics of MOS devices and scaling rules. Additionally, the CeV curve “stretches out” effect along the voltage axis for as deposited Hf1xTixO2 has been improved after PDA treatments. On the other hand, the positive shift for CeV curves indicates the existence of negative oxide-charge density in the Hf1xTixO2 film. The density of the oxide charge density (Qox) was extracted from the CeV curve based on the following equation:
. Aq Q ox ¼ Cox Vfb ∅ms
(4)
where Øms is the work-function difference between Al and Si substrate. Cox and A are accumulation oxide capacitance and electrode area. Border charge density trapped oxide charges with the expression:
. Aq Not ¼ Cox DVfb
(5)
here, DVfb is hysteresis voltage. The as-deposited condition shows a hysteresis voltage of 0.116 V after a double-sweeping capacitance measurement. When the annealing temperature reaches to 400 C, the hysteresis loop dramatically decreased to the minimum (0.005 V), showing improved interface as compared with the others, as shown in Fig. 3. Moreover, the interface trap charge density (Dit) during stressing has been calculated using the method proposed by Terman from the high-frequency CeV measurements at 1 MHz using the equation [19]:
Dit ¼
Cox dðDVgÞ Aq djs
(6)
where Dit is the interface trap charge density, DVg is the experimental voltage shift relative to the ideal high frequency characteristic curve. The idea gate voltage only consist of two parts: one part of it is given to the insulating layer and the other is forming the surface potential (js). The density of oxide charge, border charge and interface trap charges calculated from CeV measurements were found to be 1.03 1012cm2, 1.10 1012 and 2.12 1012 cm2, for 400 C annealed samples, respectively. However, a conspicuous change in charge trapping properties is observed for samples annealed at 600 and 800 C. In this case, the increasing of the kinds of these charges may be explained to be owing to the large number of trapping of electrons during PDA. The corresponding values estimated for others were displayed in Table 1. Fig. 4 shows measured capacitance vs. gate bias at different annealing temperature and various frequencies for the Al/
Hf1xTixO2/n-Si (MOS) structure, indicating that the measured capacitance is dependent on bias voltage and frequency. It is clear that the capacitance decreases with decreasing frequency in the range of high frequency. The frequency dispersion at accumulation region is not only due to the defects in high-k and interface, but also strongly depends on series resistance because of the increase in the interface layer thickness with thermal annealing [20]. It is also seen that with the decrease of the measurement frequency, there was little variation of the flat-band voltage Vfb implying trace amount of existence of a considerable amount of oxide charge. To clarify this point further, Fig. 5 shows the measured capacitance with frequency (Cef) of Al/Hf1xTixO2/n-Si structure. The measured capacitance almost remains constant up to a certain value of the frequency in the higher side of the frequency scale, and the capacitance reaches the minimum at about 4.3 105 Hz. By decreasing the frequency, C(f) shows a sharp rise again until it reaches the maximum values as a function of the frequency. This occurs based on one theory that at lower frequencies the interface states can follow the alternating current signal and yield an excess capacitance. However, in the high frequency limit (f > 500 kHz), the interface states cannot follow the applied signal, which will make the contribution of interface state capacitance to the total capacitance negligibly small.
3.2. Leakage current-conduction mechanism analysis In order to analyze the leakage current-conduction mechanism of the Hf1xTixO2 thin films, the temperature dependence of the gate leakage current has been investigated systematically. Asymmetric leakage current density via gate voltage (J-V) curves in accumulation and inversion biases can be clearly observed. From Fig. 6, it is clear that the leakage current density under gate injection is much larger than that under substrate injection at the same absolute voltage value, which is attributed to the different energy band under different injection modes [21]. In addition, the leakage current density reaching the minimum possibly originates from the reduction of traps and the suppression of interfacial parasitic oxide during 400 C-annealing. The increase of leakage current density depended on temperature in the negative region may be caused by electron tunneling form Al gate electrode to Si through defect and interface states [22]. It is well known that, in MOS structure, the current conduction mechanisms of hopping conduction mainly includes direct tunneling (DT), Fowler-Nordheim (FeN) tunneling, Schottky emission (SE), Poole-Frenkle (PeF) emission, and spacecharge-limited conductions (SCLCs). In current work, various types of charge conduction mechanisms through a gate oxide will be represented in relation to MOS application with a negatively biased metal gate (gate injection) and a positively biased metal gate (substrate injection) used in the description. Schottky emission is a field-assisted thermionic emission of an electron over a surface barrier. The leakage current density governed by Schottky emission is expressed as [23],
" pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi# qðøB qE=4p3i 3o J ¼ AT exp KT 2
Fig. 3. Dielectric constant (k) and hysteresis loop (DVfb) of the Hf1xTixO2 thin film as functions of annealing temperatures.
(7)
where A is effective Richardson constant and A ¼ 4pq(mox)k2/ h3 ¼ 120(mox/m0), T,øB, E, 3o, 3i, k, m0, mox and h are the absolute temperature, the Schottky barrier height, the electric field in oxide, the vacuum permittivity, the dynamic dielectric constant, the Boltzmann constant, the free electron mass, the electron effective mass and the Planck's constant respectively. The 3i is the square of the measured refractive index (3i ¼ n2) and E ¼ (Vg-Vfb)/tox (tox is the thickness of oxide) [24]. On both sides with logarithmic, ln(J/T2)
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Table 1 Parameters of the MOS capacitors extracted from HF CeV curves. Samples
Vfb (V)
DVfb(V)
Border charges density (Not)
ad 400 C 600 C 800 C
0.117 0.119 0.146 0.166
0.116 0.005 0.054 0.073
2.67 1.10 1.18 1.51
1011cm2 1010cm2 1011cm2 1011cm2
Fig. 4. Measured capacitance versus gate voltage for as deposited thin film and annealed ones at (a) room temperature, (b) 400 C, (c) 600 C, and (d) 800 C for the Al/Hf1xTixO2/n-Si (MOS) structure.
K
Dit (cm2ev1)
19.2 18.2 18.0 17.7
2.32 2.12 2.18 2.26
Oxide-charge density (Qox)
1012 1012 1012 1012
1.01 1.03 1.32 1.49
1012 1012 1012 1012
cm2 cm2 cm2 cm2
Fig. 7. Schottky emission (SE) plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for gate injection. The inset in (a) is the band diagram of MOS capacitors.
versus (E)1/2 properties of the capacitor with different annealed Hf1xTixO2 dielectric for gate injection was shown in Fig. 7. The slopes of the SE plots can be got from graphical representation expressed as,
slop ¼
Fig. 5. Variation of capacitance as a function of frequency of the as-deposited Al/ Hf1xTixO2/n-Si MOS capacitor.
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi q q=4p3i 3o 1 ¼ 1:31 105 pffiffiffiffiffiffiffiffi T 3i 3o KT
ðcm=VÞ1=2
(8)
here, 3i and n values at different temperatures were extracted from the slopes of the SE plots and these values were tabulated in Table 2. The fitted dynamic dielectric constant 3i values at all temperatures deviated from the theoretical value in the field (E1/ 2 < 800 (V/cm)1/2). The IeV curves were well fitted with SE conduction in the field (E1/2 > 800 (V/cm)1/2) with 3i values increasing within the ranges of 5.9 < 3i < 23.5 corresponding to n in the range of 2.4 < n < 4.8, as shown in the Table 2. It is also found that the conversion of current transport mechanism to Schottky emission occurs at the electric field of about 600 (V/cm)1/2 for the 400 Cannealed sample, smaller than that for the others, which can be
Table 2 n and ØB values extracted from the SeE and at various annealing temperatures for gate injection.
3i,
Fig. 6. Typical JeV characteristics of Si-based MOS capacitors as functions of annealing temperatures.
Sample
Schottky E1/2 < 800
E1/2 > 800
3i
n
ØB
3i
n
ØB
ad 400 C 600 C 800 C
0.6 0.5 0.6 2.1
0.8 0.7 0.8 1.5
e e e e
5.9 13.4 6.0 23.5
2.4 3.5 2.5 4.8
0.95 0.96 0.88 0.89
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ascribed to that there are only a very small amount of impurities and the highly homogenous quality of oxide for 400 C-annealed sample. Through using the Arrhenius plot the Schottky barrier height between Al and Hf1xTixO2 interface is analyzed to be about 0.96 eV for 400 C annealed sample. The leakage current in oxide associated with PeF emission can be shown by utilizing the following equation [25]:
" J Eexp
qðøt
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi# qE=p3i 3o KT
Table 3 n and Øt values extracted from the PeF and at various annealing temperatures for gate injection.
3i,
Sample
ad 400 C 600 C 800 C
Poole-Frankel E1/2 < 800
E1/2 > 800
3i
n
Øt
3i
n
Øt
8.5 8.6 13.4 23.2
2.9 2.9 3.5 4.8
1.32 1.34 1.23 1.20
95.3 89.1 52.3 24.8
9.7 9.0 7.2 4.9
e e e e
(9)
where øt is the trap energy barrier separating traps from conduction band. The plot of PeF coordinate of ln(J/E) versus E1/2 at different annealing temperatures is sketched in Fig. 8. The dielectric constant of thin film can be extracted from the slope of curve,
1 slop ¼ KT
sffiffiffiffiffiffiffiffiffiffiffi q3 1 ¼ 2:62 105 pffiffiffiffiffiffiffiffi T 3i 3o p3i 3o
ðcm=VÞ1=2
(10)
The value of the dynamic dielectric constant 3i and n extracted from the plot of PeF coordinate were tabulated in Table 3. It is found that PeF conduction was only prevailing at low field (E1/ 2 < 800 (V/cm)1/2) with n values falling within the ranges of 2.9 < n < 4.8. Moreover, the trap energy level (øt) in the Hf1xTixO2 thin film is analyzed to be about 1.20e1.32 eV. It should be noted that the barrier heights discussed in this work correspond to relevant references [26,27]. FeN conduction was called that even though electron have not enough energy to be used to tunnel through surface potential barrier, it can tunnel from the semiconductor conduction band into the oxide conduction band through a triangular barrier, governed by the well-known formula given by following [28]:
# " 1 2 q3 E2 mo 8pð2qm Þ2 ø3o J¼ exp 8ph∅o m 3hqE
(11)
Fig. 9. Fowler-Nordheim (FeN) emission plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for gate injection. The inset in (a) is the band diagram of the MOS capacitors.
here, m* is the tunneling electron effective mass in Hf1xTixO2 thin film, øo is the triangular barrier height and the other terms are as defined earlier. In this work, m* ¼ mox is assumed. In Hf-based films
m* ¼ 0.4m0 [29]. For a standard FeN tunneling, a plot of ln(J/E2) versus 1/E should be linear, as shown in Fig. 9. From Eq. (11), the slope of the curve is obviously proportional to øo 3/2 [30],
1 2 slop ¼ 7:134 1016 m ∅3o ðMV=cmÞ
Fig. 8. PeF emission plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for gate injection. The inset in (a) is the band diagram of the MOS capacitors.
(12)
Eq. (12), plotted in the region of high oxide fields, 1/ E ¼ 0.50e0.66 cm/MV, corresponding to Vg ¼ 2.27 ~ 3 V. The experimental øo values at all temperatures extracted from the slopes of the FeN plots were under 0.20 eV for gate injection. The calculated value of øo is far away from what we expected, implying that the Fowler-Nordheim tunneling was not a dominant current transport mechanism. The compact and superior oxide layer in the MOS capacitor could make the tunneling mechanisms such as Fowler-Nordheim tunneling under through the barrier height at Si/ Hf1xTixO2 interface being subordinate. As a positive gate voltage is applied on a gate electrode, electrons as the majority carriers in n-type Si are being accumulated. The current varies linearly with the oxide field (Ohmic type conduction), which can occur at an extremely low gate voltage. This type of low field current conduction may be due to a hopping mechanism where current is carried by thermally excited electrons moving between isolated discrete defect states [31]. According to the Lampert's theory of space charge limited mechanism, the Ohm's conduction dominates at low gate bias which can be mathematically described as follows [32]:
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Table 4 and n values extracted from the SeE plots at various annealing temperatures for substrate injection.
3i
Sample
ad 400 C 600 C 800 C
Fig. 10. A family of current density (J)eapplied voltage (Vg) plot of Hf1xTixO2 measured at different temperatures for gate injection. Filled line indicates the linear fitting of Ohm's law.
Johm ¼ qno m
Vg tox
(13)
where JOhm is the current density, q is electronic charge, no is concentration of free-charge carrier in thermal equilibrium, m is electronic mobility in the oxide and tox is physical thickness of the oxide. Fig. 10 presents an example of a typical logarithm J-V plot measured at different temperatures and fitted with Ohm's law (J ~ Vg) in a MOS capacitor. Various current conduction mechanisms can be occurred at various electrical fields. According to the formula of Ohm, SE, FP, and FN for substrate injection, respectively, all portions of JeV plots were also considered for substrate injection. The straight-line fitting in Figs. 10 and 11 indicates that the conduction mechanism at low electrical field in Hf1xTixO2 dielectric is dominated by Ohm and SE. The 3i and n values at different temperatures extracted from the SE slopes in the field (E1/2 < 800 (V/ cm)1/2) with 3i values increasing within the ranges of 3.3 < 3i < 4.3 corresponding to n in the range 1.5 < n < 2.1, and the Schottky barrier height between Si and Hf1xTixO2 interface is between 1.00
Fig. 11. Schottky emission (SE) plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for substrate injection.
Schottky E1/2 < 800
E1/2 > 800
3i
n
ØB
3i
n
ØB
4.3 4.5 2.1 3.3
2.1 2.1 1.5 1.8
1.08 1.12 1.09 1.00
e e e e
e e e e
e e e e
and 1.12 eV for prepared sample, as shown in Table 4. At a higher electrical fields in the Hf1xTixO2 layer, the fitting curve is a corresponding line that exhibits the existence of the FowlereNordheim (FeN) tunneling mechanism, as seen from the straight-line fit to ln(J/E2) vs. 1/E plot of the measurement results illustrated in Fig. 12, which corresponds to barrier heights of 0.20e0.30. The calculated value of øo is still far away from what it is expected, suggesting that is also not dominant in the sample. Based on the above, one can draw a conclusion that the good quality of thin film make the tunneling mechanisms such as FowlerNordheim tunneling to be secondary. From the curve fitting, it is also found that the 400 C annealed sample exhibits highest threshold voltage (Vth > 2.50) for the beginning of FeN mechanisms. Additionally, the inexistence of PeF conduction mechanism suggests good dielectric quality and improved leakage current from which a better dielectric integrity and reliability can be anticipated. 4. Conclusion In conclusion, the effect of the PDA on the dielectric and electrical properties of the as-deposited and annealed Hf1xTixO2 thin films have been investigated. Electrical measurements show that accumulation capacitance of Al/Hf1xTixO2/Si MOS capacitors reduces after PDA thereby decreasing the value of dielectric constant, which is related to the continuous increase in the physical thickness of a lower-k inter-layer. It is found at 400 C annealed condition, the film has the best electrical properties with the relatively large dielectric constant, lowest hysteresis loop, lowest border charge density and negligible oxide-charge density. It is also found that the
Fig. 12. Fowler-Nordheim (FeN) emission plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for substrate injection.
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variation in the scale of the leakage currents at low oxide field is dominated by PeF emission and schootky emission at high oxide field for gate injection. Ohm's conduction and Schottky emission (SE) were dominated in low applied field in the samples for substrate injection, respectively. In addition, the noticeable results show that Hf1xTixO2 films annealed at 400 C show greater insulation properties in terms of leakage current suppression with respect to larger higher threshold Voltage (Vth) which are about ±2.50 eV corresponding to FeN current conduction mechanism beginning for gate and substrate injection. On account of these results, it makes it clear that Hf1xTixO2 is a viable dielectric material to be considered for future MOS electronic devices. However, better improvement of the charge trapping mechanism and control of the interfacial layer to enhance dielectric constant are needed in order to integrate these materials into semiconductor processing. Acknowledgments The authors acknowledge the support from National Key Project of Fundamental Research (2013CB632705), National Natural Science Foundation of China (11104269), Technology Foundation for Selected Overseas Chinese Scholar, Ministry of Personnel of China (J05015131), Outstanding Young Scientific Foundation of Anhui University (KJJQ1103), and “211 project” of Anhui University. References [1] Y.C. Byun, S.H. Choi, Y.S. An, P.C. McIntyre, H.S. Kim, ACS Appl. Mater. Interfaces 6 (2014) 10482e10488. [2] L.P. Feng, N. Li, H. Tian, Z.T. Liu, J. Mater. Sci. 49 (2014) 1875e1881. [3] J.S. Lee, W.H. Kim, I.K. Oh, M.K. Kim, G. Lee, C.W. Lee, J. Park, C. LansalotMatras, W. Noh, H. Kim, Appl. Surf. Sci. 297 (2014) 16e21. [4] C. Choi, R. Choi, Thin Solid Films 521 (2012) 42e44. [5] C.K. Lee, J.Y. Kim, S.N. Hong, H.C. Zhong, B. Chen, V. Misra, J. Mater. Sci. 40 (2005) 2693e2695. [6] X.L. Zhang, S.Y. Ma, F.M. Li, F.C. Yang, J. Liu, Q. Zhao, J. Alloys Comp. 574 (2013) 149e154.
[7] M. Chandra Sekhar, P. Kondaiah, G. Mohan Rao, S.V. Jagadeesh Chandra, S. Uthanna, Superlattice. Microst 62 (2013) 68e80. [8] K.C. Lin, J.Y. Chen, H.W. Hsu, H.W. Chen, C.H. Liu, Solid. State. Electron 77 (2012) 7e11. [9] G. He, J. Gao, H.S. Chen, J.B. Cui, X.S. Chen, Z.Q. Sun, ACS Appl. Mater. Interfaces 6 (2014) 22013e22025. [10] A. Ogawa, K. Iwamoto, H. Ota, Y. Morita, M. Ikeda, T. Nabatame, A. Toriumi, Microelectron. Eng. 84 (2007) 1861e1864. [11] Y. Yang, C.G. Jin, Z.F. Wu, X.M. Wu, L.J. Zhuge, T. Yu, Mater. Chem. Phys. 142 (2013) 479e482. [12] G. He, J.W. Liu, H.S. Chen, Y.M. Liu, Z.Q. Sun, X.S. Chen, M. Liu, L.D. Zhang, J. Mater. Chem. C 2 (2014) 5299e5308. [13] J.W. Zhang, G. He, L. Zhou, H.S. Chen, X.S. Chen, X.F. Chen, B. Deng, J.G. Lv, Z.Q. Sun, J. Alloys Comp. 611 (2014) 253e259. [14] C. Ye, C. Zhan, J.Q. Zhang, H. Wang, T.F. Deng, S.R. Tang, Microelectron Reliab. 54 (2014) 388e392. [15] L.S. Yeoh, M.J. Abdullah, Z. Hassan, Curr. Appl. Phys. 14 (2014) 23e29. [16] J.W. Liu, A. Kobayashi, J. Ohta, H. Fujioka, M. Oshima, Appl. Phys. Lett. 103 (2013) 172101-1e172101-4. [17] S. Kaya, R. Lok, A. Aktag, J. Seidel, E. Yilmaz, J. Alloys Comp. 583 (2014) 476e480. [18] T. Yu, C.G. Jin, X.M. Yang, Y.J. Dong, H.Y. Zhang, L.J. Zhuge, X.M. Wu, Z.F. Wu, Appl. Surf. Sci. 258 (2012) 2953e2958. [19] P.S. Das, A. Biswas, Microelectron Reliab. 52 (2012) 112e117. [20] A. Tataroglu, S¸. Altındal, M.M. Bülbül, Microelectron Eng. 81 (2005) 140e149. [21] Z. Xu, M. Houssa, S.D. Gendt, M. Heyn, Appl. Phys. Lett. 80 (2002) 1975e1977. [22] T. Yu, C.G. Jin, Y.J. Dong, D. Cao, L.J. Zhuge, X.M. Wu, Mat. Sci. Semicon. Proc. 16 (2013) 1321e1327. [23] S.J. Ding, D.W. Zhang, L.K. Wang, J. Phys. D. Appl. Phys. 40 (2007) 1072e1076. [24] C.L. Cheng, J.H. Horng, K.S. Chang-Liao, J.T. Jeng, H.Y. Tsai, Solid State Electron. 54 (2010) 1197e1203. [25] T. Hori, Gate Dielectrics and MOS ULSIs, SpringereVerlag, New York, 1997, pp. 45e88. [26] H.W. Chen, S.Y. Chen, K.C. Chen, H.S. Huang, C.H. Liu, F.C. Chiu, Appl. Surf. Sci. 254 (2008) 6127e6130. [27] C.H. Liu, H.W. Chen, S.Y. Chen, H.S. Huang, L.W. Cheng, Appl. Phys. Lett. 95 (2009) 012103-1e012103-3. [28] K.Y. Cheong, J.H. Moon, H.J. Kim, W. Bahng, N.K. Kim, J. Appl. Phys. 103 (2008) 084113-1e084113-8. [29] F.C. Chiu, J. Appl. Phys. 100 (2006) 114102-1e114102-5. [30] J. Kim, S.A. Krishnan, S. Narayanan, M.P. Chudzik, M.V. Fischetti, Microelectron Reliab. 52 (2012) 2907e2913. [31] Z. Ouennoughia, C. Strenger, F. Bourouba, V. Haeublein, H. Ryssel, L. Frey, Microelectron Reliab. 53 (2013) 1841e1847. [32] F.C. Chiu, H.W. Chou, J.Y. Lee, J. Appl. Phys. 97 (2005) 103503-1e103503-5.
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Journal of Alloys and Compounds journal homepage: http://www.elsevier.com/locate/jalcom
Modulation of charge trapping and current-conduction mechanism of TiO2-doped HfO2 gate dielectrics based MOS capacitors by annealing temperature J.W. Zhang a, G. He a, *, H.S. Chen a, J. Gao a, X.F. Chen a, P. Jin a, D.Q. Xiao a, R. Ma b, M. Liu b, Z.Q. Sun a a
School of Physics and Materials Science, Radiation Detection Materials & Devices Lab, Anhui University, Hefei 230601, PR China Key Laboratory of Materials Physics, Anhui Key Laboratory of Nanomaterials and, Nanostructure, Institute of Solid State Physics, Chinese Academy of Sciences, Hefei, 230031, PR China
b
a r t i c l e i n f o
a b s t r a c t
Article history: Received 27 April 2015 Received in revised form 1 June 2015 Accepted 5 June 2015 Available online 17 June 2015
Current conduction mechanisms of Hf1xTixO2-gated metaleoxideesemiconductor (MOS) capacitors depending on various post-annealing temperature (PDA) have been investigated. The sample subjected to 400 C annealing exhibits superior performance with negligible hysteresis memory window shift (DVfb ¼ 0.005 V) and lowest gate leakage current density (5.4 105 A/cm2 at Vg ¼ 2 V). In addition, evolution of density of interface traps (Dit), border charger density (Not) and oxide charge density (Qox) as a function of annealing temperature were investigated in details. Detailed electrical measurements reveal that the dominant current conduction behaviors are PooleeFrankel (PeF) emission in the region of low electric fields and Schottky Emission (SE) in the region of high electric fields for gate injection. For substrate injection, however, is mainly via Ohm's conduction, Schottky emission (SE) conduction mechanism serves in low applied field in the samples, respectively. © 2015 Elsevier B.V. All rights reserved.
Keywords: High-k gate dielectrics TiO2-doped HfO2 Puttering Current-conduction mechanism
1. Introduction Metal gate/high-dielectric-constant (high-k) dielectric stacked films are a promising candidate of conventional silicon dioxide SiO2 layer to enhance the performances of metal oxide semiconductor (MOS) devices with the shrinking of the gate length and gate dielectric thickness [1e6]. Hf-based high-k gate dielectrics are very promising among some potential high-k candidates. However, one of the main concerns about pure HfO2 is the density of active traps at and near the high-k dielectric/Si interface which is higher than the density of traps at SiO2/Si interface, which can act as significant scattering centers for carriers and increase the interface-state density (Dit) [7]. In the past decades Hf-based gate dielectric materials, such as, HfTaO, HfTiO, HfZrLaO, HfLaO dielectrics, have been paid more attention due to their thermodynamic stability with silicon channels, preferable band offsets, and reasonably high dielectric constants [8e11]. Especially, the incorporation of titanium element into HfO2 has attracted considerable attention
* Corresponding author. E-mail address: [email protected] (G. He). http://dx.doi.org/10.1016/j.jallcom.2015.06.042 0925-8388/© 2015 Elsevier B.V. All rights reserved.
because TiO2 has a high dielectric constant (k ~ 80), and a high electron barrier to Si [12,13]. Ye et al. have shown that the introduction of TiO2 into HfO2 demonstrates the increased crystallization temperature (>700 C) and improved microstructure including interface, surface and amorphous properties [14]. The concept of doping can be understood that the dopants act as network modifiers, compensate the oxygen vacancies in metal oxides, and by this way reduce the leakage current and trap density. By far, although there exists significant material performance improvement by TiO2-incorporation into HfO2, annealing temperature dependent detailed charge trapping and current-conduction mechanism, such as trapped oxide charges, interface trap density (Dit), leakage current behavior of TiO2-doped HfO2 gate dielectrics based MOS capacitors, in particular, have not been systematically investigated. The variation of electrical characteristics of capacitors with temperature will, to a large extent, influence its capacitance and gate leakage current, hence the circuit performance. In this work, the effect of annealing temperature on the CeV characteristic and gate leakage current of MOS capacitors based on Hf1xTixO2 gate dielectric has been investigated. What's more, a special focus of current study is to reveal the mechanism of temperature dependence of tunneling in all field regions.
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2. Experimental details A commercially purchased n-doped Si wafer with a doping concentration of 1 1015 cm3, epitaxial thickness of 1 mm was chosen as the substrates. Prior to Hf1xTixO2 gate dielectric deposition, the wafers were ultrasonically cleaned with acetone and alcohol in sequence for 10 min to remove residues and contaminants, and than etched in a diluted hydrofluoric solution to remove native oxide on the surface, leaving an H-terminated surface. After cleaning, the composite targets (Hf1xTixO2, with 60 mm in diameter and 5 mm in thickness) sintered at high temperature with the mixing proportion of HfO2 (99.99% purity) and TiO2 (99.99% purity) was used as sputtering target to deposit film and the mass percent concentration of TiO2 in the targets is 3%. Hf1xTixO2 gate dielectrics with thickness of about 20 nm confirmed by spectroscopic ellipsometry (SC630, SANCO Co, Shanghai) were deposited by sputtering equipment (JGPDZS, Chinese Academy of Sciences, Shenyang Scientific Instrument Co., Ltd), in an Ar ambient with a RF power of 60 W. To obtain the thickness of the films accurately, the CauchyeUrbach dispersion model was used to fit the data with a threelayer-structured optical model structure (Hf1xTixO2/SiO2/Si) during fitting process. Subsequently, post-deposition annealing (PDA) using rapid thermal annealing (RTA) system was performed under a vacuum atmosphere for 60 s at 400, 600, and 800 C, respectively. In order to explore the electrical properties, Al/Hf1xTixO2/n-Si/Al MOS capacitors were fabricated by sputtering a Al top electrode through a shadow mask with an area of 7.065 104 cm2 and the back surfaces of all samples were deposited with a 200-nm-thick Al film by sputtering after the back surface oxide stripping to decrease contact resistance, as schematically shown in Fig. 1. A semiconductor device analyzer (Agilent B1500A) combined with Cascade Probe Station was used for CeV measurement at room temperature. Short circuit and open circuit calibration were performed before real measurements. Sinusoid signals with different frequency range from 600 kHz to 1 MHz were superimposed upon a direct current (DC) voltage which was applied between top and bottom electrodes. And the DC voltage was swept from negative to positive or back and forth to perform single and double sweeps. Additionally, the leakage current properties were measured by B1500A. All the electrical characterization was performed at room temperature in a shielded dark box.
Fig. 2. High frequency (1 MHz) capacitanceevoltage curves for as-deposited Hf1xTixO2 thin film and annealed ones at 400 C, 600 C and 800 C.
3. Results and discussion 3.1. Electrical analyses of the Al/Hf1xTixO2/n-Si MOS devices The dependence of high-frequency (1 MHz) CeV characteristics on the annealing temperatures, swept from 2 V to 1.5 V, is depicted in Fig. 2. The gate voltage was swept from inversion to accumulation region and vice versa to check the magnitude of hysteresis. Holes are tunneling from the substrate to the thin film when it is applied a negative voltage at the gate, and when applied a positive voltage at the gate, electrons from the substrate are tunneling to the thin film. The steeper CeV curves found in depletion layer indicate the lower interface state densities and the existed small hysteresis. It is well known that the semiconductor surface layer will deviate from the flat band condition because the internal electrical charges produce field in high dielectric material. The shielding distance or band bending region is known as extrinsic Debye length LD which is formulized by Refs. [15,16],
sffiffiffiffiffiffiffiffiffiffiffi KT3s LD ¼ q2 Na
where Na is the doping concentration in semiconductor, 3s is the semiconductor permittivity (11.9), k is Boltzmann constant. The flat band capacitance Cfb with the above extrinsic Debye length LD is given by Refs. [17],
Cfb ¼
1 Cox
1 þ C1s
Cs ¼ ðA3o KÞ=LD
Fig. 1. Schematic of the structure of Al/Hf1xTixO2/n-Si capacitors. Gate voltages are applied for substrate injection and gate injection.
(1)
(2)
(3)
here, Cox is oxide layer capacitance, Cs is semiconductor capacitance. The corresponding flat band voltage Vfb values to Cfb were extracted from the respective CeV curves. It is clearly visible that the accumulation capacitance (Cox) is reduced after PDA, which can be due to the reduction of the dielectric constant with increased annealing temperature. The effective dielectric constants of Hf1xTixO2 films at room temperature, 400, 600, and 800 Cannealed were 19.2, 18.2, 18.0 and 17.7, respectively. The evolution of the dielectric constant related with annealing temperature can be attributed to the microstructure change, such as crystalline, interfacical structure referring mainly to the notable increment of the SiO2 and Hf-silicate interfacial layer thickness due to the Hf diffusion into SiO2, accompanying Si up-diffusion into the high-k dielectric [13,18]. In general, a lower-k interface layer thickness increasing at higher PDA temperatures will lead to lowering Cox,
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which in turn results in an increase in equivalent oxide thickness (EOT), which is undesirable to the final electrical characteristics of MOS devices and scaling rules. Additionally, the CeV curve “stretches out” effect along the voltage axis for as deposited Hf1xTixO2 has been improved after PDA treatments. On the other hand, the positive shift for CeV curves indicates the existence of negative oxide-charge density in the Hf1xTixO2 film. The density of the oxide charge density (Qox) was extracted from the CeV curve based on the following equation:
. Aq Q ox ¼ Cox Vfb ∅ms
(4)
where Øms is the work-function difference between Al and Si substrate. Cox and A are accumulation oxide capacitance and electrode area. Border charge density trapped oxide charges with the expression:
. Aq Not ¼ Cox DVfb
(5)
here, DVfb is hysteresis voltage. The as-deposited condition shows a hysteresis voltage of 0.116 V after a double-sweeping capacitance measurement. When the annealing temperature reaches to 400 C, the hysteresis loop dramatically decreased to the minimum (0.005 V), showing improved interface as compared with the others, as shown in Fig. 3. Moreover, the interface trap charge density (Dit) during stressing has been calculated using the method proposed by Terman from the high-frequency CeV measurements at 1 MHz using the equation [19]:
Dit ¼
Cox dðDVgÞ Aq djs
(6)
where Dit is the interface trap charge density, DVg is the experimental voltage shift relative to the ideal high frequency characteristic curve. The idea gate voltage only consist of two parts: one part of it is given to the insulating layer and the other is forming the surface potential (js). The density of oxide charge, border charge and interface trap charges calculated from CeV measurements were found to be 1.03 1012cm2, 1.10 1012 and 2.12 1012 cm2, for 400 C annealed samples, respectively. However, a conspicuous change in charge trapping properties is observed for samples annealed at 600 and 800 C. In this case, the increasing of the kinds of these charges may be explained to be owing to the large number of trapping of electrons during PDA. The corresponding values estimated for others were displayed in Table 1. Fig. 4 shows measured capacitance vs. gate bias at different annealing temperature and various frequencies for the Al/
Hf1xTixO2/n-Si (MOS) structure, indicating that the measured capacitance is dependent on bias voltage and frequency. It is clear that the capacitance decreases with decreasing frequency in the range of high frequency. The frequency dispersion at accumulation region is not only due to the defects in high-k and interface, but also strongly depends on series resistance because of the increase in the interface layer thickness with thermal annealing [20]. It is also seen that with the decrease of the measurement frequency, there was little variation of the flat-band voltage Vfb implying trace amount of existence of a considerable amount of oxide charge. To clarify this point further, Fig. 5 shows the measured capacitance with frequency (Cef) of Al/Hf1xTixO2/n-Si structure. The measured capacitance almost remains constant up to a certain value of the frequency in the higher side of the frequency scale, and the capacitance reaches the minimum at about 4.3 105 Hz. By decreasing the frequency, C(f) shows a sharp rise again until it reaches the maximum values as a function of the frequency. This occurs based on one theory that at lower frequencies the interface states can follow the alternating current signal and yield an excess capacitance. However, in the high frequency limit (f > 500 kHz), the interface states cannot follow the applied signal, which will make the contribution of interface state capacitance to the total capacitance negligibly small.
3.2. Leakage current-conduction mechanism analysis In order to analyze the leakage current-conduction mechanism of the Hf1xTixO2 thin films, the temperature dependence of the gate leakage current has been investigated systematically. Asymmetric leakage current density via gate voltage (J-V) curves in accumulation and inversion biases can be clearly observed. From Fig. 6, it is clear that the leakage current density under gate injection is much larger than that under substrate injection at the same absolute voltage value, which is attributed to the different energy band under different injection modes [21]. In addition, the leakage current density reaching the minimum possibly originates from the reduction of traps and the suppression of interfacial parasitic oxide during 400 C-annealing. The increase of leakage current density depended on temperature in the negative region may be caused by electron tunneling form Al gate electrode to Si through defect and interface states [22]. It is well known that, in MOS structure, the current conduction mechanisms of hopping conduction mainly includes direct tunneling (DT), Fowler-Nordheim (FeN) tunneling, Schottky emission (SE), Poole-Frenkle (PeF) emission, and spacecharge-limited conductions (SCLCs). In current work, various types of charge conduction mechanisms through a gate oxide will be represented in relation to MOS application with a negatively biased metal gate (gate injection) and a positively biased metal gate (substrate injection) used in the description. Schottky emission is a field-assisted thermionic emission of an electron over a surface barrier. The leakage current density governed by Schottky emission is expressed as [23],
" pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi# qðøB qE=4p3i 3o J ¼ AT exp KT 2
Fig. 3. Dielectric constant (k) and hysteresis loop (DVfb) of the Hf1xTixO2 thin film as functions of annealing temperatures.
(7)
where A is effective Richardson constant and A ¼ 4pq(mox)k2/ h3 ¼ 120(mox/m0), T,øB, E, 3o, 3i, k, m0, mox and h are the absolute temperature, the Schottky barrier height, the electric field in oxide, the vacuum permittivity, the dynamic dielectric constant, the Boltzmann constant, the free electron mass, the electron effective mass and the Planck's constant respectively. The 3i is the square of the measured refractive index (3i ¼ n2) and E ¼ (Vg-Vfb)/tox (tox is the thickness of oxide) [24]. On both sides with logarithmic, ln(J/T2)
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Table 1 Parameters of the MOS capacitors extracted from HF CeV curves. Samples
Vfb (V)
DVfb(V)
Border charges density (Not)
ad 400 C 600 C 800 C
0.117 0.119 0.146 0.166
0.116 0.005 0.054 0.073
2.67 1.10 1.18 1.51
1011cm2 1010cm2 1011cm2 1011cm2
Fig. 4. Measured capacitance versus gate voltage for as deposited thin film and annealed ones at (a) room temperature, (b) 400 C, (c) 600 C, and (d) 800 C for the Al/Hf1xTixO2/n-Si (MOS) structure.
K
Dit (cm2ev1)
19.2 18.2 18.0 17.7
2.32 2.12 2.18 2.26
Oxide-charge density (Qox)
1012 1012 1012 1012
1.01 1.03 1.32 1.49
1012 1012 1012 1012
cm2 cm2 cm2 cm2
Fig. 7. Schottky emission (SE) plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for gate injection. The inset in (a) is the band diagram of MOS capacitors.
versus (E)1/2 properties of the capacitor with different annealed Hf1xTixO2 dielectric for gate injection was shown in Fig. 7. The slopes of the SE plots can be got from graphical representation expressed as,
slop ¼
Fig. 5. Variation of capacitance as a function of frequency of the as-deposited Al/ Hf1xTixO2/n-Si MOS capacitor.
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi q q=4p3i 3o 1 ¼ 1:31 105 pffiffiffiffiffiffiffiffi T 3i 3o KT
ðcm=VÞ1=2
(8)
here, 3i and n values at different temperatures were extracted from the slopes of the SE plots and these values were tabulated in Table 2. The fitted dynamic dielectric constant 3i values at all temperatures deviated from the theoretical value in the field (E1/ 2 < 800 (V/cm)1/2). The IeV curves were well fitted with SE conduction in the field (E1/2 > 800 (V/cm)1/2) with 3i values increasing within the ranges of 5.9 < 3i < 23.5 corresponding to n in the range of 2.4 < n < 4.8, as shown in the Table 2. It is also found that the conversion of current transport mechanism to Schottky emission occurs at the electric field of about 600 (V/cm)1/2 for the 400 Cannealed sample, smaller than that for the others, which can be
Table 2 n and ØB values extracted from the SeE and at various annealing temperatures for gate injection.
3i,
Fig. 6. Typical JeV characteristics of Si-based MOS capacitors as functions of annealing temperatures.
Sample
Schottky E1/2 < 800
E1/2 > 800
3i
n
ØB
3i
n
ØB
ad 400 C 600 C 800 C
0.6 0.5 0.6 2.1
0.8 0.7 0.8 1.5
e e e e
5.9 13.4 6.0 23.5
2.4 3.5 2.5 4.8
0.95 0.96 0.88 0.89
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ascribed to that there are only a very small amount of impurities and the highly homogenous quality of oxide for 400 C-annealed sample. Through using the Arrhenius plot the Schottky barrier height between Al and Hf1xTixO2 interface is analyzed to be about 0.96 eV for 400 C annealed sample. The leakage current in oxide associated with PeF emission can be shown by utilizing the following equation [25]:
" J Eexp
qðøt
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi# qE=p3i 3o KT
Table 3 n and Øt values extracted from the PeF and at various annealing temperatures for gate injection.
3i,
Sample
ad 400 C 600 C 800 C
Poole-Frankel E1/2 < 800
E1/2 > 800
3i
n
Øt
3i
n
Øt
8.5 8.6 13.4 23.2
2.9 2.9 3.5 4.8
1.32 1.34 1.23 1.20
95.3 89.1 52.3 24.8
9.7 9.0 7.2 4.9
e e e e
(9)
where øt is the trap energy barrier separating traps from conduction band. The plot of PeF coordinate of ln(J/E) versus E1/2 at different annealing temperatures is sketched in Fig. 8. The dielectric constant of thin film can be extracted from the slope of curve,
1 slop ¼ KT
sffiffiffiffiffiffiffiffiffiffiffi q3 1 ¼ 2:62 105 pffiffiffiffiffiffiffiffi T 3i 3o p3i 3o
ðcm=VÞ1=2
(10)
The value of the dynamic dielectric constant 3i and n extracted from the plot of PeF coordinate were tabulated in Table 3. It is found that PeF conduction was only prevailing at low field (E1/ 2 < 800 (V/cm)1/2) with n values falling within the ranges of 2.9 < n < 4.8. Moreover, the trap energy level (øt) in the Hf1xTixO2 thin film is analyzed to be about 1.20e1.32 eV. It should be noted that the barrier heights discussed in this work correspond to relevant references [26,27]. FeN conduction was called that even though electron have not enough energy to be used to tunnel through surface potential barrier, it can tunnel from the semiconductor conduction band into the oxide conduction band through a triangular barrier, governed by the well-known formula given by following [28]:
# " 1 2 q3 E2 mo 8pð2qm Þ2 ø3o J¼ exp 8ph∅o m 3hqE
(11)
Fig. 9. Fowler-Nordheim (FeN) emission plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for gate injection. The inset in (a) is the band diagram of the MOS capacitors.
here, m* is the tunneling electron effective mass in Hf1xTixO2 thin film, øo is the triangular barrier height and the other terms are as defined earlier. In this work, m* ¼ mox is assumed. In Hf-based films
m* ¼ 0.4m0 [29]. For a standard FeN tunneling, a plot of ln(J/E2) versus 1/E should be linear, as shown in Fig. 9. From Eq. (11), the slope of the curve is obviously proportional to øo 3/2 [30],
1 2 slop ¼ 7:134 1016 m ∅3o ðMV=cmÞ
Fig. 8. PeF emission plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for gate injection. The inset in (a) is the band diagram of the MOS capacitors.
(12)
Eq. (12), plotted in the region of high oxide fields, 1/ E ¼ 0.50e0.66 cm/MV, corresponding to Vg ¼ 2.27 ~ 3 V. The experimental øo values at all temperatures extracted from the slopes of the FeN plots were under 0.20 eV for gate injection. The calculated value of øo is far away from what we expected, implying that the Fowler-Nordheim tunneling was not a dominant current transport mechanism. The compact and superior oxide layer in the MOS capacitor could make the tunneling mechanisms such as Fowler-Nordheim tunneling under through the barrier height at Si/ Hf1xTixO2 interface being subordinate. As a positive gate voltage is applied on a gate electrode, electrons as the majority carriers in n-type Si are being accumulated. The current varies linearly with the oxide field (Ohmic type conduction), which can occur at an extremely low gate voltage. This type of low field current conduction may be due to a hopping mechanism where current is carried by thermally excited electrons moving between isolated discrete defect states [31]. According to the Lampert's theory of space charge limited mechanism, the Ohm's conduction dominates at low gate bias which can be mathematically described as follows [32]:
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Table 4 and n values extracted from the SeE plots at various annealing temperatures for substrate injection.
3i
Sample
ad 400 C 600 C 800 C
Fig. 10. A family of current density (J)eapplied voltage (Vg) plot of Hf1xTixO2 measured at different temperatures for gate injection. Filled line indicates the linear fitting of Ohm's law.
Johm ¼ qno m
Vg tox
(13)
where JOhm is the current density, q is electronic charge, no is concentration of free-charge carrier in thermal equilibrium, m is electronic mobility in the oxide and tox is physical thickness of the oxide. Fig. 10 presents an example of a typical logarithm J-V plot measured at different temperatures and fitted with Ohm's law (J ~ Vg) in a MOS capacitor. Various current conduction mechanisms can be occurred at various electrical fields. According to the formula of Ohm, SE, FP, and FN for substrate injection, respectively, all portions of JeV plots were also considered for substrate injection. The straight-line fitting in Figs. 10 and 11 indicates that the conduction mechanism at low electrical field in Hf1xTixO2 dielectric is dominated by Ohm and SE. The 3i and n values at different temperatures extracted from the SE slopes in the field (E1/2 < 800 (V/ cm)1/2) with 3i values increasing within the ranges of 3.3 < 3i < 4.3 corresponding to n in the range 1.5 < n < 2.1, and the Schottky barrier height between Si and Hf1xTixO2 interface is between 1.00
Fig. 11. Schottky emission (SE) plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for substrate injection.
Schottky E1/2 < 800
E1/2 > 800
3i
n
ØB
3i
n
ØB
4.3 4.5 2.1 3.3
2.1 2.1 1.5 1.8
1.08 1.12 1.09 1.00
e e e e
e e e e
e e e e
and 1.12 eV for prepared sample, as shown in Table 4. At a higher electrical fields in the Hf1xTixO2 layer, the fitting curve is a corresponding line that exhibits the existence of the FowlereNordheim (FeN) tunneling mechanism, as seen from the straight-line fit to ln(J/E2) vs. 1/E plot of the measurement results illustrated in Fig. 12, which corresponds to barrier heights of 0.20e0.30. The calculated value of øo is still far away from what it is expected, suggesting that is also not dominant in the sample. Based on the above, one can draw a conclusion that the good quality of thin film make the tunneling mechanisms such as FowlerNordheim tunneling to be secondary. From the curve fitting, it is also found that the 400 C annealed sample exhibits highest threshold voltage (Vth > 2.50) for the beginning of FeN mechanisms. Additionally, the inexistence of PeF conduction mechanism suggests good dielectric quality and improved leakage current from which a better dielectric integrity and reliability can be anticipated. 4. Conclusion In conclusion, the effect of the PDA on the dielectric and electrical properties of the as-deposited and annealed Hf1xTixO2 thin films have been investigated. Electrical measurements show that accumulation capacitance of Al/Hf1xTixO2/Si MOS capacitors reduces after PDA thereby decreasing the value of dielectric constant, which is related to the continuous increase in the physical thickness of a lower-k inter-layer. It is found at 400 C annealed condition, the film has the best electrical properties with the relatively large dielectric constant, lowest hysteresis loop, lowest border charge density and negligible oxide-charge density. It is also found that the
Fig. 12. Fowler-Nordheim (FeN) emission plots for the Al/Hf1xTixO2/n-Si MOS capacitor at different annealing temperatures for substrate injection.
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variation in the scale of the leakage currents at low oxide field is dominated by PeF emission and schootky emission at high oxide field for gate injection. Ohm's conduction and Schottky emission (SE) were dominated in low applied field in the samples for substrate injection, respectively. In addition, the noticeable results show that Hf1xTixO2 films annealed at 400 C show greater insulation properties in terms of leakage current suppression with respect to larger higher threshold Voltage (Vth) which are about ±2.50 eV corresponding to FeN current conduction mechanism beginning for gate and substrate injection. On account of these results, it makes it clear that Hf1xTixO2 is a viable dielectric material to be considered for future MOS electronic devices. However, better improvement of the charge trapping mechanism and control of the interfacial layer to enhance dielectric constant are needed in order to integrate these materials into semiconductor processing. Acknowledgments The authors acknowledge the support from National Key Project of Fundamental Research (2013CB632705), National Natural Science Foundation of China (11104269), Technology Foundation for Selected Overseas Chinese Scholar, Ministry of Personnel of China (J05015131), Outstanding Young Scientific Foundation of Anhui University (KJJQ1103), and “211 project” of Anhui University. References [1] Y.C. Byun, S.H. Choi, Y.S. An, P.C. McIntyre, H.S. Kim, ACS Appl. Mater. Interfaces 6 (2014) 10482e10488. [2] L.P. Feng, N. Li, H. Tian, Z.T. Liu, J. Mater. Sci. 49 (2014) 1875e1881. [3] J.S. Lee, W.H. Kim, I.K. Oh, M.K. Kim, G. Lee, C.W. Lee, J. Park, C. LansalotMatras, W. Noh, H. Kim, Appl. Surf. Sci. 297 (2014) 16e21. [4] C. Choi, R. Choi, Thin Solid Films 521 (2012) 42e44. [5] C.K. Lee, J.Y. Kim, S.N. Hong, H.C. Zhong, B. Chen, V. Misra, J. Mater. Sci. 40 (2005) 2693e2695. [6] X.L. Zhang, S.Y. Ma, F.M. Li, F.C. Yang, J. Liu, Q. Zhao, J. Alloys Comp. 574 (2013) 149e154.
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