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Clock-less 8-bit SAR-ADC with delay-line based digital control circuit
Microelectronics Journal 94 (2019) 104641
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Clock-less 8-bit SAR-ADC with delay-line based digital control circuit M. Borgarino a, *, L. Giacomini a, G. Luppi a, F. Digiaro b, J.B. Begueret c, N. Verrascina c a
Engineering Department Enzo Ferrari, University of Modena and Reggio Emilia, Via Vivarelli, 10, int. 1, 41125, Modena, Italy Infineon Technologies, Pavia, Formerly with University of Modena and Reggio Emilia, Italy c IMS Laboratory, University of Bordeaux, France b
A R T I C L E I N F O
A B S T R A C T
Keywords: SAR-ADC CMOS Clock-free
Aim of the present paper is to propose an 8 bit SAR-ADC architecture where no external clock signals or on-chip clock generation circuits are used. The digital control circuitry is designed around a delay line constituted by a cascade of monostables. The circuit was implemented in a bulk 350 nm CMOS technology. The core of the integrated circuit is about 1500 μm 1500 μm. Post layout simulations for both static (DNL, INL) and dynamic (ENOB, SINAD, THD) Figure-of-Merits are reported. The obtained performance are well aligned with others claimed in the literature for clocked SAR-ADC architectures.
1. Introduction Integrated Circuits (ICs) interfacing human body and/or environment with digital systems are even more pervasive in the today digital society. The Analog-to-Digital Converter (ADC) is a key building block in these ICs. It is in charge of translating the incoming analog signal into a stream of bits. If, on one hand, the digital acquisition of bio-metric and environmental data does not need high speed conversion rate, because of the low frequency of the involved signals, on the other hand, the specific characteristics of the final application enforces low dissipated power, because of the power source exiguity and/or the impossibility of a frequent battery replacement. In medicine, the human-body/electronics interface should be implantable, as in the case of pace-makers, heart defibrillators or epileptic seizure detectors. In smart agriculture, the sensor in the nodes of a spatially distributed sensors network, as in the case of a vineyard, or the sensor embedded in a cow collar, as in the case of the livestock monitoring, should harvest energy from the surrounding environment. Several ADC architectures are available to the designer: flash, pipeline, Successive Approximation Register (SAR), sigma-delta. For the abovementioned applications the SAR-ADC architecture is preferable thanks to its low power consumption, medium-to-high resolution, and small form factor. The SAR-ADC exploits a binary research algorithm to find the output digital word best approximating the sampled analog input signal. This algorithm is implemented in a logic control circuit whose operation is usually controlled by a clock. The use of a clock is so widely employed [1–8], that only few papers detail as this clock is obtained [9–15]. In Ref. [10] and in Ref. [13] the clock was externally
generated. The clock was on-chip produced by a relaxation oscillator in Refs. [9,11,12], by a ring oscillator in Ref. [14], and by an asynchronous digital logic temporizer designed around a delayed feedback loop in Ref. [15]. The present work reports on the design in a 350 nm bulk CMOS technology of a SAR-ADC where the logic control circuit operates without clock. The logic is based on the use of a chain of monostables. To the best knowledge of the authors, this paper is the first report on the use of the monostable to control the digitization process in a SAR-ADC. The paper is organized as follows. Section 2 addresses the general SAR-ADC architecture, Sections 3 focuses on the schematics with main attention on the logic control circuitry, Section 4 describes the prototype layout and reports on the simulation results, discussed later in the following Section 5 together with a comparison with the literature. Section 6 ends the paper by drawing some conclusions. 2. SAR-ADC architecture Fig. 1 shows the general architecture of the designed SAR-ADC. This architecture was chosen, because it allows for a switching strategy minimizing the dynamic dissipation in the multi switched-capacitor Digital to Analog Converters (DACs) [10]. These DACs generate the Y and Z voltages on the basis of the control signals sent by the Digital Control Unit (DCU). The comparison of these voltages is used by the DCU to generate the future control signals for the DACs. Note that both DACs receive the reference voltage VREF but only DAC2 receives the analog input signal VIN to be digitized. Comparison by comparison the DCU makes sure that the SAR-ADC explores the binary tree of the conversion
* Corresponding author. E-mail address: [email protected] (M. Borgarino). https://doi.org/10.1016/j.mejo.2019.104641 Received 26 February 2019; Received in revised form 2 September 2019; Accepted 13 October 2019 Available online 21 October 2019 0026-2692/© 2019 Elsevier Ltd. All rights reserved.
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capacitors in the DAC1 are discharged while all the capacitors in the DAC2 are pre-charged to VREF/2-VIN. During this phase all Gndi and Refi (i ¼ 0 … 7) signals are forced to zero. The following replica are used by the logic unit for the successive settings of the switches. With the replica φ0 the logic unit initializes the DAC by forcing the control signals Refi (i ¼ 0 … 7) to high voltage and Gndi (i ¼ 0 … 7) to low voltage. As these signals drive the gate of the switching transistors in the DAC (see previous Fig. 2), all the transistors controlled by the Refi (Gndi) signals are set on (off). The replica φ1 is used by the logic unit to force Ref7 (Gnd7) to low (high) voltage, generating in this way the Most Significant Bit (MSB). All the others control signals are kept to their previously initialized values. With the following replicas φi, (i ¼ 2 … 8) the logic unit forces the control signals Ref9-i to the comparator output voltage (e.g. high voltage) and Gnd9-i to the negated comparator output voltage (e.g. low voltage). In addition, the logic unit forces the control signal Ref8-i (Gnd8-i) to low (high) voltage; all the remaining control signals are kept to their previous initialization value. In this way the output bits, following the MSB, coincide with the Refi (i ¼ 1 … 7) signals. The replica EoC, following the replica φ8, guarantees that the output register bank makes available the output stable bits. Note that the input signals to the output register bank are the MSB and control signals Refi (i ¼ 1 … 7), in agreement with the previous description. The last replica Reset states the end of the digitization process and it forces all the control signals Refi and Gndi (i ¼ 0 … 7) to low voltage. The following Fig. 4 summarizes the behaviour of the DCU through the sequence diagram it generates. For sake of saving space, all the replica have been plotted in a single time diagram. In fact, these replica are high one at a time. The Gndi (i ¼ 0 … 7) signals have been omitted, because they are complementary to the Refi (i ¼ 0 … 7) signals during all the digitization process with exception of the Reset time slot during which all Gndi and Refi (i ¼ 0 … 7) signals are forced to zero, as they were in the Start time slot. The gray areas indicate that the value of the signal may be high or low depending on the output generated by the comparator. After the Reset signal, the SAR-ADC is ready for receiving another Sample pulse, triggering a new digitization process. In short, Fig. 4 shows that the core of the digitization process is the sequence occurring between φ0 and φ8. The Start time-slot is aimed to the pre-charge of the capacitors in the DACs. It is during this phase that the SAR-ADC acquires the analog voltage VIN to be digitized. The EoC time-slot is devoted to the generation of the output bits and the Reset time-slot points to the reset of the Refi and Gndi (i ¼ 0 … 7) signals. The delay chain was designed by cascading twelve delay unit cells as that shown in Fig. 5. Core of this cell is a monostable, triggered on the rising edge of a short positive pulse applied at the input; if the input signal is a long pulse or even worse a step, the monostable does not more correctly work. In correspondence of the rising edge of the input signal, the monostable generates an output pulse whose width T depends on the constant time set by the capacitor C and the channel resistance of the pull-up Pchannel MOS transistor. T can be therefore tuned through the voltage VCTRL. The following delay unit cell should be triggered by a pulse generated in correspondence of the falling edge of the width pulse generated by the monostable. To this aim, an inverter is placed at the output of the monostable, so that the falling edge of the monostable output pulse is transformed into a rising edge. Since, as previously highlighted, the signal triggering the monostable should be a short pulse, a high-pass RC filter is placed at the output of the inverter. This filter acts as a derivator generating thus both negative and positive spikes. Only the positive spike is sensed by the monostable in the following delay unit cell, which is therefore triggered after a time interval T is elapsed from the triggering of the previous delay unit cell. Even if the delay line operation guarantees the correct succession of the pulses, since each pulse is generated by the falling edge of the previous one, Process Voltage Temperature (PVT) variations can induce variations in the width of the pulse. In the present paper, the pulse width was kept equal to 10μsec. The whole digitization process requires the
Fig. 1. General architecture of the designed SAR-ADC.
algorithm until the Last Significant Bit (LSB) is generated. Fig. 1 shows that the SAR-ADC is constituted by three main blocks: the DCU, the DAC and the comparator. Next section address the schematics of these blocks. 3. Schematics 3.1. DACs Fig. 2 shows that each DAC is as a network of binary weighted switched-capacitors where N-channel MOS transistors act as switches. Note that the switches are organized in triplets, each controlled by three signals Start, Gndi, and Refi, with i ¼ 0 … 7. As it visible in Fig. 1, these signals are sent to the DACs by the DCU. The switches controlled by the Start signal receive VIN in the DAC2 and VREF/2 in the DAC1, in agreement with the general architecture. 3.2. Digital Control Unit Fig. 3 shows the building block diagram of the DCU proposed in the present work. It is constituted by a delay chain, a logic unit, and an output register bank. The delay chain is the core of the DCU. The sampling signal Sample at the input of the delay chain triggers the digitization process. The DCU generates twelve delayed replicas of the signal Sample. In the time order, they are Start, φi (i ¼ 0 … 8), End of Conversion (EoC), and Reset. With the exception of Start, the logic unit receives these replicas and translates them into the control signals (Refi, and Gndi with i ¼ 0 … 7) for the switches in the DACs. The first generated replica, labelled “Start” in Fig. 3, is directly sent to the DAC to set the switches so that all the
Fig. 2. Switched-capacitor network of each DAC. 2
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Microelectronics Journal 94 (2019) 104641
Fig. 3. Building block diagram of the DCU.
Fig. 4. Sequence diagram generated by the DCU.
Moreover, even if not implemented in the present work, the capacitor in the monostable may be replaced by a bank of capacitors, similar to those used in the VCO’s, to enlarge further the time margin. Of course, the capabilities of appeasing reduce with increasing the sampling rate. The logic unit is organized on three layers and designed in static CMOS logic. The first layer is an array of eight 2-input AND gates. The second layer is an array of twenty-three 2-input OR gates. These two layers implement the previously hinted algorithm generating the control signals for the DACs. The third layer is an array of seventeen set-reset flipflops designed by cross-coupling two NOR gates. This layer stores an output bit each time it is generated during the digitization process. The bias was set to 1 V, in order to reduce the power dissipation. Since the nominal bias voltage of the employed technology is 3.3 V, the high logic level generated by the DCU is not high enough to correctly control the transistor gates in the DACs. The DCU outputs and the DACs inputs were therefore interfaced with arrays of two cascaded CMOS inverters biased at increasing supply voltage. They rise up the high logic voltage level from 1 V to 1.5 V and from 1.5 V to 2 V, a large enough value for a correct
Fig. 5. Delay unit cell in the delay chain.
generation of twelve replica. So, each digitization takes 120μsec. The used sampling frequency is 5 kHz, leaving a margin of 80μsec available to appease a possible longer width due to PVT variations. It would be needful to increase this time margin, the voltage VCTRL (see Fig. 4), controlling the constant time of the monostable, can come into help. 3
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way, the circuit merges the pulses generated by the delay chain. Fig. 7 shows also that the signal Enable is applied not only to the dynamic comparator but also to a synchronization register placed between the comparator and the logic unit. Note that the signal Enable is applied to the synch register with delay, in order to guarantee that the register samples only when the comparator output is stable. The schematic of the used delay cell is sketched in Fig. 8. Its core is a starved current inverter loaded with a 650 fF capacitor. The signal Vdelay allows for tuning the propagation time. An output Schmitt trigger makes sharper the output pulse, whose falling edge may result too smooth, because of the slow discharge induced by the starved current. Eventually, in Fig. 7 note also a dummy register at the comparator output not connected to the synchronization register. This dummy register helps in reducing as much as possible the unbalance in the output parasitic capacitances, to which the dynamic comparator is highly sensible.
Fig. 6. Schematic of the dynamic comparator.
4. Results
control of the transistors in the DACs. Note that the use of two inverters saves the logic phase of the control signals. Finally, the output register bank was simply designed as an array of eight master-slave, transmission gate-based, D-type registers clocked by the EoC signal. In correspondence of the rising edge of the EoC signal, these registers sample the Refi (i ¼ 0 … 7) and the MSB signals to generate the output bits MSB, MSB-1, MSB-2, MSB-3, MSB-4, MSB-5, MSB-6, LSB.
A prototype of the previously described SAR-ADC was designed and laid out in the 350 nm CMOS technology from Austria Micro-Systems. Fig. 9 shows the obtained layout. It is core-limited with a core size of about 1500 μm 1500 μm. The eight output bits (MSB, MSB-1, MSB-2, MSB-3, MSB-4, MSB-5, MSB-6, MSB-7) are available on the pads distributed around the lower right corner of the padring. The signal starting the analog-to-digital conversion is applied on the pad Sample on the top. The reference voltage used for the conversion is applied on the pad VRef (on the bottom). Around the padring are visible the pads for the ground (on the top) and for the four different used biases 1 V (on the top), 1.5 V (on the right), 2 V and 3.3 V (on the bottom). The DC voltage biasing the gate of the pull-up PMOS transistor in the pulse merger (see Fig. 7) is applied on the pad VP (on the top). The DC voltage (VCTRL) biasing the gate of the PMOS transistor in the monostable (see Fig. 5) is applied on the pad VPulse (on the top). Eventually, the DC voltage controlling the starved current in the delay cell (see Fig. 8) is applied on the pad VDelay (on the right). The twelve delay unit cells constituting the delay chain are visible in the upper right corner of the layout. The two DACs are located on the left side of the layout while the remaining blocks as the logic unit and dynamic comparator are in the lower right corner area. The layout of the DAC was designed using a common centroid approach. All the binary weighted capacitors of the DAC were split into several 75 fF capacitors and arranged as described in Fig. 10. The four “0” stand for the four 75 fF capacitors for the C capacitor in Fig. 2; similarly, the four “1” stand for the other C capacitor in Fig. 2. The capacitance C is therefore of 300 fF.
3.3. Comparator The comparator is as a dynamic latch, whose schematic is depicted in Fig. 6. As in Ref. [16], it is a flipped version of the strong-ARM latch described in Ref. [17]. In a dynamic comparator a high sensitivity, due to the intrinsic positive feedback of a cross-coupled pair of CMOS inverters (transistors M4, M5, M7, and M8 in Fig. 6), comes together with a low dissipated power, because the circuit is gated by an enabling signal. The circuit dissipates only when enabled; it is in a sleeping state during the rest of the time. In the present work, the enabling signal Enable is generated by the pulse merger circuit depicted at the bottom of Fig. 7. Each gate of the N-channel transistors in the pull-down network is controlled by a different couple of spikes generated by the delay unit cell, generally indicated as “pulse x” in Fig. 5 with x ¼ 0 … 7. Because of the operation mode of the delay chain, only one transistor at a time is on, in correspondence of the received positive spike. The size of the P-channel transistor in the pull-up network and the static voltage applied to its gate are designed in order to achieve a large swing in the Enable signal. In this
Fig. 7. Pulse merger and dynamic comparator/logic unit interface. 4
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Microelectronics Journal 94 (2019) 104641
The eight “2” stand for the eight 75 fF capacitors for the 2C capacitor in Fig. 2; identically for the other cases. All the binary weighted capacitors of the DAC share therefore the same common centroid, located in the center of the scheme. Fig. 11 shows the resulting layout of the DAC. The switching NMOS transistors in Fig. 2 are located at the bottom of the layout where the controlling signals are highlighted in red. The metal lines connecting the switched capacitor introduce parasitic capacitances that were extracted and compensated with properly sized capacitors highlighted in white in Fig. 11. Table 1 compares the nominal values of the capacitors with the extracted ones. The table reports also the introduced compensating capacitances. It shows that the compensation capacitors make the weight factors of the DAC capacitors closer to the desired ideal binary values. The performances of the designed SAR-ADC were investigated both in terms of static Figure-of-Merits (FoMs) as the Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) and of dynamic FoMs as the Equivalent Number of Bit (ENOB) and Total Harmonic Distortion (THD). As depicted in Fig. 12, the static (dynamic) FoMs were obtained by applying at the input of the SAR-ADC a slow linear ramp (a 200 Hz sinusoidal tone) and analyzing in the time (frequency) domain the signal generated by an ideal DAC connected at the output of the SAR-ADC under test. The sampling frequency (fs) was set equal to 5 kHz in both the cases. Fig. 13 shows the static FoMs simulated without parasitics extraction and therefore without parasitics compensation. Figs. 14 and 15 show the simulations carried out by accounting for the parasitic extraction without or with the capacitive compensation, respectively. Fig. 16 shows the typical signal at the output of the ideal DAC together with its spectrum in the case of a dynamic FoM simulation carried out for an extracted SARADC with uncompensated DACs. The frequency analysis extracts the ENOB, SINAD, SFDR, and THD dynamic FoMs. The following Table 2 reports the obtained static and dynamic FOMs for the three different investigated cases.
Fig. 8. Schematic of the delay cell used in the dynamic comparator/logic unit interface.
5. Discussion Fig. 13 shows that before parasitic extraction both the DNL and the INL are lower than 0.1LSB. Table 2 shows that, under the same
Fig. 9. Layout of the designed SAR-ADC prototype.
Fig. 10. Common centroid scheme adopted for the DAC. Fig. 11. Layout of the DAC with the compensating capacitors highlighted. 5
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Table 1 DAC capacitors before and after extraction, with and without compensation. Capacitor
C0 C1 C2 C3 C4 C5 C6 C7
Ideal Weight Factor
Nominal capacitance [fF]
1 1 2 4 8 16 32 64
300 300 600 1200 2400 4800 9600 19200
Without compensation Parasitic capacitance [fF]
Total Capacitance [fF]
Real Weight Factor
30 34,8 41,82 56,66 77,67 134,4 252,4 524,3
330 334,8 641,82 1256,66 2477,67 4934,4 9852,4 19724,3
1 1,01 1,94 3,81 7,51 14,95 29,86 59,77
Compensating Capacitance [fF]
0 0 27,84 82,54 200,73 422,4 861,2 1722,4
With compensation Parasitic capacitance [fF]
Total Capacitance [fF]
Real Weight Factor
30 34,84 43,47 60,03 80,22 138,5 257,8 536,3
330 334,84 671,31 1342,57 2680,95 5360,9 10719 21458,7
1 1,01 2,03 4,07 8.12 16,25 32,48 65,03
Fig. 12. Simulation set-up for static and dynamic FoMs.
Fig. 14. DNL and INL simulated with parasitic extraction and uncompensated DAC.
Fig. 13. DNL and INL simulated without parasitic extraction and without compensation.
conditions, the ENOB is 8-bit and the THD is better than 60dB. After parasitic extraction (see Fig. 14) the DNL exhibits higher values and the INL get worse not only in the values but also in the general behaviour. The introduction of the compensating capacitors leads to static FoMs, whose values and behaviour are very close to the case before extraction; Figs. 13 and 15 appear indeed very similar. This indicates that the worsening shown in Fig. 14 is largely due to the incorrect ratios in the weight factors induced by the capacitive parasitics of the metal lines connecting the DAC to the switching capacitors (see Fig. 11) [18,19]. Table 1 shows indeed that the use of the compensating capacitors allows to reproduce weight factors very close to the pre-extraction values even if, of course, the absolute capacitance of each single capacitor is different. For the SAR-ADC linearity it is not important the absolute value of each capacitor but rather that the capacitances are in a binary ratio as much as possible. Table 2 gives evidence that the main impact of the parasitics is on the linearity, in agreement with [15,20]. THD gets worse more than
Fig. 15. DNL and INL simulated with parasitic extraction and compensated DAC.
SFDR and SINAD when the parasitics are introduced without compensating them. On the other hand, when the binary weights are restored through compensation, the THD recovers the pre-extraction value. The following Table 3, Figs. 17 and 18 compare the performance of the proposed SAR ADC with those claimed in the literature. Table 3 compares the simulated FoMs reported in Table 2 with the experimental ones claimed in the literature for other 350 nm CMOS SAR-ADCs working at comparable sampling frequency. The SAR-ADC designed in the present work well compares with the literature. Fig. 17 shows the breakdown of the dissipated power. The delay chain (Fig. 5) is the most power hungry
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Fig. 16. Ideal DAC output signal (on the left) and its spectrum (on the right) in the case of extracted parasitic and uncompensated DAC1 and DAC2. Table 2 Comparison of the static and dynamic FoMs for the three investigated cases. Extraction Compensation DNL [LSB] INL [LSB] ENOB [bit] SINAD [dB] SFDR [dB] THD [dB]
No No 0.103/þ0.096 0.093/þ0.081 8.02 50.02 53.92 64.32
Yes No 0.203/þ0.195 0.278/þ0.145 7.87 49.16 53.98 57.54
Yes Yes 0.103/þ0.096 0.109/þ0.074 8.02 50.02 53.97 64.32
Table 3 FoM comparison with other 350 nm CMOS SAR-ADC.
DNL [LSB] INL [LSB] ENOB [bits] SINAD [dB] SFDR [dB] THD [dB] fs [kHz]
[10]
[11]
[47]
[14]
This work
0.18/ þ0.34 0.20/þ0.27
0.65/ þ0.52 0.84/ þ0.65 n.a.
1.5/ þ1.5 2.0/ þ2.0 n.a.
0.1/ þ0.1 0.1/ þ0.1 8.0 on 8
48.2
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n.a.
n.a.
50
67.8 n.a. 2
n.a. 44.4 n.a.
n.a. n.a. 1000
n.a. n.a. 1
53.9 64.3 5
7.8 on 8
Fig. 18. Dissipated power versus sampling frequency. References for 350nm: [9], [10], [15], [21]. References for 180nm: [5–8], [10], [13], [22–31], [44], [40], [39], [38]. References for 130nm: [1], [2], [32–37]. References for 65nm: [3].
The proposed DCU works without the need of a clock. Its activity starts after the Sample pulse is received (see Fig. 3) and it stops at the end of the digitization process. Following [41] the SAR-ADC proposed in the present work can be classified as on demand. It does not exhibit switching activity in the waiting for the sampling event, putting to zero the standby dissipated power. On the other hand, a switching activity consumes current all the time in clocked or self-clocked solutions [1–15]. The control of the digitization process in the proposed DCU is based on a delay-line obtained by cascading several delay cell unit, whose core is a monostable (see Fig. 5). To the best knowledge of the authors, this is the first time that a monostable is applied to control the digitization process in a SAR ADC. In asynchronous solutions [42–44] the digital circuitry controlling the digitization process is based on a cascade of Bit Slice Unit (BSU). These digital circuits are designed by using dynamic logic, in order to reduce the number of transistors. The dynamic logic circuitry in a typical BSU counts thirteen transistors plus four inverters. The delay unit cell (see Fig. 4) proposed in the present work counts one transistor, one 2-input NOR gate and two inverters together with two capacitors and one resistor. In Ref. [45] the proposed solution is asynchronous with a digital loop in charge of generating on demand the self-clock to activate the dynamic comparator. It counts five 2-input gates, three inverters and a digital delay element. In the proposed DCU the self-synchronisation is guaranteed by the pulse merger (see Fig. 7), which is a very simple circuit common to the whole delay chain. With respect to the previously cited solutions, the proposed DCU offers therefore a reduced complexity of the digital logic even using a standard static CMOS style design. This reduced complexity is paid with an increase in the silicon area due to the use of
Fig. 17. Dissipated power breakdown.
block, responsible for about 40% of the dissipated power, followed by the voltage buffers (30%). The output register bank sinks only 3% of the total dissipated power. The remaining dissipated power is equally distributed between the delay cells and the logic unit. Moreover, Fig. 18 compares the designed SAR-ADC with the literature in terms of dissipated power and sampling rate. With the exception of four outstanding works [31,38, 39,44] and one inferior case [36], the symbols distribution in the figure describe a band defined by two lines with a slope of about 1 dec/dec. The SAR-ADC proposed in the present work stays on this band demonstrating therefore that it well compares with the state-of-art. 7
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capacitors in the monostable, as it appears in the layout (see Fig. 9). As explained in the sub-section 3.2, the mono-stable based delay unit cell offers capabilities of appeasing PVT variations. The counter- or BSU-based solutions do not offer these appeasing capabilities. This advantage is kept in the case the proposed SAR-ADC would be arranged to work in a self-clocked mode. The signal Reset generated by the delay chain could indeed be used similarly as in Ref. [41] to make self-clocked the proposed SAR-ADC even if at the cost of increasing the stand-by dissipated power. Eventually, it is worth noticing that the monostable demonstrated to be a promising alternative to the digital delay generator for low jitter delay higher than 100ns [46]. As the monostable is at the core of the delay line proposed in the present work, this seems promising in terms of intrinsic robustness against jitter.
[7]
[8]
[9]
[10]
[11]
6. Conclusions
[12]
This paper presents an 8-bit SAR-ADC designed in a low cost bulk 350 nm CMOS technology. The core of the layout consumes a silicon area of about 1500 μm 1500 μm. In particular, the layout of the DAC was designed common centroid and compensated for the parasitic capacitances introduced by the metal lines connecting the capacitor with the switches. The novelty of the proposed clock-less SAR-ADC is in the design of the control logic, which is based on the use of a delay-line, whose core is a monostable. The concept of delay for the design of the digital control circuitry was exploited also in Ref. [15] but in a different way. In addition to the use of a delay line, to the best knowledge of the authors, this paper is the first report on the use of monostables to control the digitization process of a SAR-ADC. It is worth noticing that the monostable seems to be promising for the generation of low jitter delay higher than 100ns. The proposed DCU offers the advantage of a reduced circuitry complexity with respect to the previously reported solutions where a cascade of dynamic logic BSU’s and/or more complex synchronization digital circuits are used. Moreover, the proposed DCU offers also the advantage of some capabilities of appeasing PVT induced variations. These advantages are paid with an increase of the silicon area, because of the use of capacitors in the monostable. Simulations demonstrated static and dynamic figure-of-merits well comparable with the literature. The SAR-ADC proposed in the present work well compare with the literature also in terms of dissipated power and sampling rate. The present work proves therefore that the monostable based delayline approach can be successfully applied to control the digitization process of a SAR-ADC.
[13] [14] [15]
[16]
[17] [18]
[19]
[20]
[21] [22]
[23]
[24]
[25]
Acknowledgment [26]
Austria Micro Systems is warmly acknowledged for having provided the design kit.
[27]
References [28]
[1] S. Al-Ahdab, R. Lofti, W. Serdijn, A 1-V 225-nW 1KS/s current successive approximation ADC for pacemakers, in: IEEE 6th Conference on PhD Research in Microelectronics and Electronics, July 2010, pp. 1–4. Berlin (Germany). [2] D. Zhang, A. Bhide, A. Alvandpour, A 53nW 9.12 ENOB 1kS/s SAR ADC in 0.13um CMOS for Medical Implant Devices, in: IEEE European Solid-State Circuits Conference, September 2011, pp. 467–470. Helsinki ( Finland). [3] M. Yip, A.P. Chandrakasan, A resolution-configurable 5-to-10b 0.4-to-1V power scalable SAR ADC, in: IEEE International Solid-State Circuits Conference, April 2011, pp. 190–191. San Francisco (CA). [4] N. Verma, A.,P. Chandrakasan, An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensors nodes, IEEE J. Solid State Circuits 42 (June 2007) 1196–1205. [5] A.T. Do, C.K. Lam, Y.S. Tan, K.S. Yeo, J.H. Cheong, L. Tao, M.T. Tan, M. Je, A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems, in: IEEE Asia and Pacific Conference on Circuits and Systems, December 2012, pp. 1–4. Kaohsiung (Taiwan). [6] A.T. Do, C.K. Lam, Y.S. Tan, K.S. Yeo, J.H. Cheong, X. Zou, L. Yao, K.W. Cheng, M. Je, A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications, in:
[29]
[30]
[31]
[32]
[33]
8
IEEE Int. New Circuits and Systems Conference, June 2012, pp. 525–528. Montreal (Canada),. Y. Susanti, P.K. Chan, V.K.S. Ong, An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator, in: IEEE Asia Pacific Conf. On Circuits and Systems, November-December 2008, pp. 284–287. Macao (China). Y.K. Yang, X. Liu, J. Zhou, J.H. Cheong, M. Je, W.L. Goh, A 0.5V 16nW 8.08-ENOB SAR ADC for ultra-low power sensor applications, in: IEEE Int. Microwave Workshop Series RF and Wireless Technologies for Biomedical and Healthcare Applications, December 2013, pp. 1–4. Singapore ( Singapore). X. Xu, X. Zou, L. Yao, Y. Lian, A 1-V 450-nW fully integrated biomedical sensors interface systems, in: IEEE Digest of Technical Paper Symposium on VLSI Circuits, June 2008, pp. 78–79. Honolulu (USA). W. Hu, Y.-T. Liu, T. Nguyen, D.Y.C. Lie, B.P. Ginsburg, An 8-bit single-ended ultralow-power SAR ADC with a novel DAC switching method and a counter-based digital control circuit, IEEE Trans. on Circuits and Systems – I, Regular Papers 60 (July 2013) 1726–1739. X. Zou, X. Xu, L. Yao, Y. Lian, A 1-V 450-nW fully integrated programmable biomedical sensor interface chip, IEEE J. Solid State Circuits 44 (April 2009) 1067–1077. H. Zhang, Y. Qin, S. Yang, Z. Hong, Design on an ultra-low power SAR ADC for biomedical applications, in: IEEE International Conference on Solid-State and Integrated Circuits Technology, November 2010, pp. 460–462. Shangai (China). J. Sauerbrey, D. Schmitt-Landsiedel, R. Thewes, A 0.5-V 1-uW successive approximation ADC, IEEE J. Solid State Circuits 38 (July 2003) 1261–1265. H. Wu, Y. P.Xu, A 1V 2.3 uW biomedical signal acquisition IC, in: IEEE International Conference on Solid-State Circuits, February 2006, pp. 1–4. San Francisco (CA). S. Brenna, A. Bonfanti, A.L. Lacaita, A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with Attenuation Capacitance Calibration in 0.35-um CMOS, vol. 89, November 2016, pp. 357–371. L. Zheng, L.B. Leene, Y. Liu, T.G. Costandinou, An adaptive 16/64kHz, 9-bit SAR ADC with peak-aligned sampling for neural soike recording, in: “IEEE International Symposium on Circuits and Sistems, 2014, pp. 2385–2388. Melbourne (Australia. B. Razavi, The StrongARM latch, in: IEEE Solid-State Circuits Magazine, 2015, pp. 12–17. Spring. M.P.-H. Lin, Y.-T. He, V.W.- H- Hsiao, R.-G. Chang, S.-Y. Lee, Common-centroid capacitor layout generation considering device matching and parasitic minimization, IEEE on Computer-Aided Design of Integrated Circuits and Systems 32 (July 2013) 991–1002. Y. Li, Z. Zhang, D. Chua, Y. Lian, Placement for binary-weighted capacitve array in SAR ADC using multiple weighting methods”, IEEE Trans. On Computer-Aided esign of Integrated Circuits and Systems 33 (September 2014) 1277–1287. M. Saberi, R. Lofti, K. Mafinezhad, W.A. Serdjin, Analysis of power consumption and linearity in capacitive digital-to-analog Converters used in successive approximation ADCs, IEEE Trans. On Circuits and Systems – I, Regular Papers 58 (August 2011) 1736–1748. X. Zou, X. Xu, L. Yao, Y. Lian, A 1-V 450-nW fully integrated biomedical sensor interface chip, IEEE J. Solid State Circuits 44 (Issue 4) (2009) 1067–1077. H. Zhang, Y. Qin, S. Yang, Z. Hong, Design on an ultra-low power SAR ADC for biomedical applications, in: IEEE International Conference on Solid-State and Integrated Circuits Technology, Shangai, China, 1-4 November 2010, pp. 460–462. I. Kianpour, Z. Zou, M.B. Nejad, L.R. Zheng, An 8-bit 166nW 11.25 kS/s 0.18um two-Step-SAR ADC for RFID applications Using Novel DAC Architecture, in: IEEE NORCHIP Conference, vols. 15–16, Tampere, Finland, November, 2010, pp. 1–4. R. Sekimoto, A. Shikata, H. Ishikuro, A Power Scalable SAR-ADC in 0.18um-CMOS with 0.5V Nano-Watt Operation, in: IEEE International Symposium on Access Spaces (ISAS), Yokohama, Japan, 17-19 June 2011, pp. 89–94. H. Zhang, Y. Qin, Z. Hong, A 1.8-V 770-nW biopotential acquisition system for portable Applications, in: IEEE Biomedical Circuits and Systems Conference, Beijing , China, 26-28 November 2009, pp. 93–96. S.K. Lee, S.J. Park, Y. Suh, H.J. Park, J.Y. Sim, A 1.3uW 0.6V 8.7-ENOB Successive Approximation DAC in a 0.18um CMOS, in: IEEE Digest Technical Papers Symposium on VLSI Circuits, Kyoto, Japan, 15-18 June 2009, pp. 242–243. H. Franca, M. Ataei, A. Boegli, P.-A. Farine, A 100nW 10-bit 400S/s SAR ADC for ultra low-power bio-sensing applications, IEEE International Symposium in Computational Medic and Health Technology, Himeji, Japan (1-3 September 2017) 1–4. M. Sadollahi, G. Temes, An 11-bit 250-nW 10KS/s SAR ADC with Doubled Input Range for Biomedical Applications, IEEE International Midwest Symposium on Circuits and Systems, Boston (MA), USA, 6-9 August 2017, pp. 385–388. M.-J. Seo, D.-H. Jin, Y.-D. Kim, S.-I. Hwang, J.-P. Kim, S.-T. Ryu, A 18.5nW 12-bit 1kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18um CMOS, IEEE Trans. on Circuits and Systems-I: Regular papers 65 (Issue 11) (2018) 3617–3627. S. Yim, Y. Park, S. Kim, Power efficient SAR ADC adaptive to input activity for ECG monitoring applications, in: IEEE International Symposium on Circuits and Systems, 2018, pp. 1–4. Baltimore (MA), USA. C.-E. Hsieh, S.-I. Liu, A 0.3V 10 bit 7.3fJ/conversion-step SAR ADC in 0.18um CMOS, in: IEEE Asian Solid-State Circuits Conference, 10-12 November 2014, pp. 325–328. Kaohsiung, Taiwan. P. Kamalinejad, S. Mirabbasi, V.C.M. Leung, An ultra-low-power SAR ADC with an area-efficient DAC architecture, in: IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, 15-18 May 2011, pp. 13–16. K. Abdelhalim, L. MacEachern, S. Mahmoud, A nanowatt ADC for ultra low power applications, in: IEEE International Symposium on Circuits and Systems, Kos, Greece, 21-24 May 2006, pp. 1507–1510.
M. Borgarino et al.
Microelectronics Journal 94 (2019) 104641 [41] Y. Zhang, E. Bonizzoni, F. Maloberti, A 10-b 200-kS/s 250-nA self-clocked coarsefine SAR ADC, IEEE Trans. on Circuits and Systems-II: Express Briefs 63 (Issue 10) (2016) 924–928. [42] S. Liu, Y. Shen, J. Wang, Z. Shu, A 10-bit self-clocked SAR ADC with enhanced energy efficiency for multi-sensor applications, IEEE Sens. J. 18 (Issue 10) (2018) 4223–4233. [43] P.J.A. Harpe, C. Zhou, Y. Bi, N.P. van der Meijs, X. Wang, K. Philips, G. Dolmans, H. de Groot, A 26 uW 8 bit 10MS/s asynchronous SAR ADC for low energy radios, IEEE J. Solid State Circuits 46 (Issue 7) (2011) 1585–1595. [44] Z. Zhu, Y. Liang, A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-um CMOS for Medical Implant Devices, IEEE Trans. on Circuits and Systems I, Regular Papers 62 (Issue 9) (2015) 2167–2176. [45] S. Liu, Y. Shen, Z. Zhu, A 12-bit 10 MS/s SAR ADC with high linearity and energyefficient switching, IEEE Trans. on Circuits and Systems – I: Regular papers 63 (Issue 10) (2016) 1616–1627. [46] M.S. Ansari, B. Singh, C.P. Navahe, A low jitter variable delay generator for regenerative amplifier in a table top terawatt femto second laser system, Indian J. Eng. Mater. Sci. 13 (2006) 269–274. [47] W. Liu, T. Wei, P. Guo, Y. Hu, Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors, in: IEEE International Conference on Industrial Electronics and Applications, 9-11 June 2014, pp. 867–871. Hangzhou, China.
[34] K. Abdelhalim, L. MacEachern, S. Mahmoud, A nanowatt successive approximation ADC with offset correction for implantable sensor applications, in: IEEE International Symposium on Circuits and Systems, New Orleans, USA, 27-30 May 2007, pp. 2351–2354. [35] A. Rodriguez-Perez, M. Delgado-Restituto, J. Ruiz-Amaya, F. Medeiro, An ultra-low power consumption 1-V, 10-bit successive approximation ADC, in: IEEE International Conference on Electronics, Circuits and Systems, 31 August-03 September 2008, pp. 634–637. St. Julien’s, Malta. [36] X. Yang, M. Zhao, X. Wu, Capacitor mismatch calibration method for SAR ADC with minimum area and power penalty, Electron. Lett. 54 (Issue 21) (2018) 1208–1210. [37] X. Yan, L. Fu, J. Wang, An 8-bit 100kS/s low power successive approximation register ADC for biomedical applications, in: International Conference on ASIC, vols. 28–31, October 2013, pp. 1–4. Shenzhen, China. [38] Y. Liang, Z. Zhu, A 10 bit 20 kS/s 17,7 nW 9.1 ENOB reference-insensitive SAR ADC in 0.18μm CMOS, Microelectron. J. 73 (2018) 24–29. [39] W. Guo, Z. Zhu, A 0.3V 8-bit 8.9 fJ/con.-step SAR ADC with sub-DAC merged switched for bio-sensors, Microelectron. J. 68 (2017) 44–54. [40] W. Bai, Z. Zhu, A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18μm CMOS for biomedical applications, Microelectron. J. 59 (2017) 40–46.
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Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Clock-less 8-bit SAR-ADC with delay-line based digital control circuit M. Borgarino a, *, L. Giacomini a, G. Luppi a, F. Digiaro b, J.B. Begueret c, N. Verrascina c a
Engineering Department Enzo Ferrari, University of Modena and Reggio Emilia, Via Vivarelli, 10, int. 1, 41125, Modena, Italy Infineon Technologies, Pavia, Formerly with University of Modena and Reggio Emilia, Italy c IMS Laboratory, University of Bordeaux, France b
A R T I C L E I N F O
A B S T R A C T
Keywords: SAR-ADC CMOS Clock-free
Aim of the present paper is to propose an 8 bit SAR-ADC architecture where no external clock signals or on-chip clock generation circuits are used. The digital control circuitry is designed around a delay line constituted by a cascade of monostables. The circuit was implemented in a bulk 350 nm CMOS technology. The core of the integrated circuit is about 1500 μm 1500 μm. Post layout simulations for both static (DNL, INL) and dynamic (ENOB, SINAD, THD) Figure-of-Merits are reported. The obtained performance are well aligned with others claimed in the literature for clocked SAR-ADC architectures.
1. Introduction Integrated Circuits (ICs) interfacing human body and/or environment with digital systems are even more pervasive in the today digital society. The Analog-to-Digital Converter (ADC) is a key building block in these ICs. It is in charge of translating the incoming analog signal into a stream of bits. If, on one hand, the digital acquisition of bio-metric and environmental data does not need high speed conversion rate, because of the low frequency of the involved signals, on the other hand, the specific characteristics of the final application enforces low dissipated power, because of the power source exiguity and/or the impossibility of a frequent battery replacement. In medicine, the human-body/electronics interface should be implantable, as in the case of pace-makers, heart defibrillators or epileptic seizure detectors. In smart agriculture, the sensor in the nodes of a spatially distributed sensors network, as in the case of a vineyard, or the sensor embedded in a cow collar, as in the case of the livestock monitoring, should harvest energy from the surrounding environment. Several ADC architectures are available to the designer: flash, pipeline, Successive Approximation Register (SAR), sigma-delta. For the abovementioned applications the SAR-ADC architecture is preferable thanks to its low power consumption, medium-to-high resolution, and small form factor. The SAR-ADC exploits a binary research algorithm to find the output digital word best approximating the sampled analog input signal. This algorithm is implemented in a logic control circuit whose operation is usually controlled by a clock. The use of a clock is so widely employed [1–8], that only few papers detail as this clock is obtained [9–15]. In Ref. [10] and in Ref. [13] the clock was externally
generated. The clock was on-chip produced by a relaxation oscillator in Refs. [9,11,12], by a ring oscillator in Ref. [14], and by an asynchronous digital logic temporizer designed around a delayed feedback loop in Ref. [15]. The present work reports on the design in a 350 nm bulk CMOS technology of a SAR-ADC where the logic control circuit operates without clock. The logic is based on the use of a chain of monostables. To the best knowledge of the authors, this paper is the first report on the use of the monostable to control the digitization process in a SAR-ADC. The paper is organized as follows. Section 2 addresses the general SAR-ADC architecture, Sections 3 focuses on the schematics with main attention on the logic control circuitry, Section 4 describes the prototype layout and reports on the simulation results, discussed later in the following Section 5 together with a comparison with the literature. Section 6 ends the paper by drawing some conclusions. 2. SAR-ADC architecture Fig. 1 shows the general architecture of the designed SAR-ADC. This architecture was chosen, because it allows for a switching strategy minimizing the dynamic dissipation in the multi switched-capacitor Digital to Analog Converters (DACs) [10]. These DACs generate the Y and Z voltages on the basis of the control signals sent by the Digital Control Unit (DCU). The comparison of these voltages is used by the DCU to generate the future control signals for the DACs. Note that both DACs receive the reference voltage VREF but only DAC2 receives the analog input signal VIN to be digitized. Comparison by comparison the DCU makes sure that the SAR-ADC explores the binary tree of the conversion
* Corresponding author. E-mail address: [email protected] (M. Borgarino). https://doi.org/10.1016/j.mejo.2019.104641 Received 26 February 2019; Received in revised form 2 September 2019; Accepted 13 October 2019 Available online 21 October 2019 0026-2692/© 2019 Elsevier Ltd. All rights reserved.
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capacitors in the DAC1 are discharged while all the capacitors in the DAC2 are pre-charged to VREF/2-VIN. During this phase all Gndi and Refi (i ¼ 0 … 7) signals are forced to zero. The following replica are used by the logic unit for the successive settings of the switches. With the replica φ0 the logic unit initializes the DAC by forcing the control signals Refi (i ¼ 0 … 7) to high voltage and Gndi (i ¼ 0 … 7) to low voltage. As these signals drive the gate of the switching transistors in the DAC (see previous Fig. 2), all the transistors controlled by the Refi (Gndi) signals are set on (off). The replica φ1 is used by the logic unit to force Ref7 (Gnd7) to low (high) voltage, generating in this way the Most Significant Bit (MSB). All the others control signals are kept to their previously initialized values. With the following replicas φi, (i ¼ 2 … 8) the logic unit forces the control signals Ref9-i to the comparator output voltage (e.g. high voltage) and Gnd9-i to the negated comparator output voltage (e.g. low voltage). In addition, the logic unit forces the control signal Ref8-i (Gnd8-i) to low (high) voltage; all the remaining control signals are kept to their previous initialization value. In this way the output bits, following the MSB, coincide with the Refi (i ¼ 1 … 7) signals. The replica EoC, following the replica φ8, guarantees that the output register bank makes available the output stable bits. Note that the input signals to the output register bank are the MSB and control signals Refi (i ¼ 1 … 7), in agreement with the previous description. The last replica Reset states the end of the digitization process and it forces all the control signals Refi and Gndi (i ¼ 0 … 7) to low voltage. The following Fig. 4 summarizes the behaviour of the DCU through the sequence diagram it generates. For sake of saving space, all the replica have been plotted in a single time diagram. In fact, these replica are high one at a time. The Gndi (i ¼ 0 … 7) signals have been omitted, because they are complementary to the Refi (i ¼ 0 … 7) signals during all the digitization process with exception of the Reset time slot during which all Gndi and Refi (i ¼ 0 … 7) signals are forced to zero, as they were in the Start time slot. The gray areas indicate that the value of the signal may be high or low depending on the output generated by the comparator. After the Reset signal, the SAR-ADC is ready for receiving another Sample pulse, triggering a new digitization process. In short, Fig. 4 shows that the core of the digitization process is the sequence occurring between φ0 and φ8. The Start time-slot is aimed to the pre-charge of the capacitors in the DACs. It is during this phase that the SAR-ADC acquires the analog voltage VIN to be digitized. The EoC time-slot is devoted to the generation of the output bits and the Reset time-slot points to the reset of the Refi and Gndi (i ¼ 0 … 7) signals. The delay chain was designed by cascading twelve delay unit cells as that shown in Fig. 5. Core of this cell is a monostable, triggered on the rising edge of a short positive pulse applied at the input; if the input signal is a long pulse or even worse a step, the monostable does not more correctly work. In correspondence of the rising edge of the input signal, the monostable generates an output pulse whose width T depends on the constant time set by the capacitor C and the channel resistance of the pull-up Pchannel MOS transistor. T can be therefore tuned through the voltage VCTRL. The following delay unit cell should be triggered by a pulse generated in correspondence of the falling edge of the width pulse generated by the monostable. To this aim, an inverter is placed at the output of the monostable, so that the falling edge of the monostable output pulse is transformed into a rising edge. Since, as previously highlighted, the signal triggering the monostable should be a short pulse, a high-pass RC filter is placed at the output of the inverter. This filter acts as a derivator generating thus both negative and positive spikes. Only the positive spike is sensed by the monostable in the following delay unit cell, which is therefore triggered after a time interval T is elapsed from the triggering of the previous delay unit cell. Even if the delay line operation guarantees the correct succession of the pulses, since each pulse is generated by the falling edge of the previous one, Process Voltage Temperature (PVT) variations can induce variations in the width of the pulse. In the present paper, the pulse width was kept equal to 10μsec. The whole digitization process requires the
Fig. 1. General architecture of the designed SAR-ADC.
algorithm until the Last Significant Bit (LSB) is generated. Fig. 1 shows that the SAR-ADC is constituted by three main blocks: the DCU, the DAC and the comparator. Next section address the schematics of these blocks. 3. Schematics 3.1. DACs Fig. 2 shows that each DAC is as a network of binary weighted switched-capacitors where N-channel MOS transistors act as switches. Note that the switches are organized in triplets, each controlled by three signals Start, Gndi, and Refi, with i ¼ 0 … 7. As it visible in Fig. 1, these signals are sent to the DACs by the DCU. The switches controlled by the Start signal receive VIN in the DAC2 and VREF/2 in the DAC1, in agreement with the general architecture. 3.2. Digital Control Unit Fig. 3 shows the building block diagram of the DCU proposed in the present work. It is constituted by a delay chain, a logic unit, and an output register bank. The delay chain is the core of the DCU. The sampling signal Sample at the input of the delay chain triggers the digitization process. The DCU generates twelve delayed replicas of the signal Sample. In the time order, they are Start, φi (i ¼ 0 … 8), End of Conversion (EoC), and Reset. With the exception of Start, the logic unit receives these replicas and translates them into the control signals (Refi, and Gndi with i ¼ 0 … 7) for the switches in the DACs. The first generated replica, labelled “Start” in Fig. 3, is directly sent to the DAC to set the switches so that all the
Fig. 2. Switched-capacitor network of each DAC. 2
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Fig. 3. Building block diagram of the DCU.
Fig. 4. Sequence diagram generated by the DCU.
Moreover, even if not implemented in the present work, the capacitor in the monostable may be replaced by a bank of capacitors, similar to those used in the VCO’s, to enlarge further the time margin. Of course, the capabilities of appeasing reduce with increasing the sampling rate. The logic unit is organized on three layers and designed in static CMOS logic. The first layer is an array of eight 2-input AND gates. The second layer is an array of twenty-three 2-input OR gates. These two layers implement the previously hinted algorithm generating the control signals for the DACs. The third layer is an array of seventeen set-reset flipflops designed by cross-coupling two NOR gates. This layer stores an output bit each time it is generated during the digitization process. The bias was set to 1 V, in order to reduce the power dissipation. Since the nominal bias voltage of the employed technology is 3.3 V, the high logic level generated by the DCU is not high enough to correctly control the transistor gates in the DACs. The DCU outputs and the DACs inputs were therefore interfaced with arrays of two cascaded CMOS inverters biased at increasing supply voltage. They rise up the high logic voltage level from 1 V to 1.5 V and from 1.5 V to 2 V, a large enough value for a correct
Fig. 5. Delay unit cell in the delay chain.
generation of twelve replica. So, each digitization takes 120μsec. The used sampling frequency is 5 kHz, leaving a margin of 80μsec available to appease a possible longer width due to PVT variations. It would be needful to increase this time margin, the voltage VCTRL (see Fig. 4), controlling the constant time of the monostable, can come into help. 3
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way, the circuit merges the pulses generated by the delay chain. Fig. 7 shows also that the signal Enable is applied not only to the dynamic comparator but also to a synchronization register placed between the comparator and the logic unit. Note that the signal Enable is applied to the synch register with delay, in order to guarantee that the register samples only when the comparator output is stable. The schematic of the used delay cell is sketched in Fig. 8. Its core is a starved current inverter loaded with a 650 fF capacitor. The signal Vdelay allows for tuning the propagation time. An output Schmitt trigger makes sharper the output pulse, whose falling edge may result too smooth, because of the slow discharge induced by the starved current. Eventually, in Fig. 7 note also a dummy register at the comparator output not connected to the synchronization register. This dummy register helps in reducing as much as possible the unbalance in the output parasitic capacitances, to which the dynamic comparator is highly sensible.
Fig. 6. Schematic of the dynamic comparator.
4. Results
control of the transistors in the DACs. Note that the use of two inverters saves the logic phase of the control signals. Finally, the output register bank was simply designed as an array of eight master-slave, transmission gate-based, D-type registers clocked by the EoC signal. In correspondence of the rising edge of the EoC signal, these registers sample the Refi (i ¼ 0 … 7) and the MSB signals to generate the output bits MSB, MSB-1, MSB-2, MSB-3, MSB-4, MSB-5, MSB-6, LSB.
A prototype of the previously described SAR-ADC was designed and laid out in the 350 nm CMOS technology from Austria Micro-Systems. Fig. 9 shows the obtained layout. It is core-limited with a core size of about 1500 μm 1500 μm. The eight output bits (MSB, MSB-1, MSB-2, MSB-3, MSB-4, MSB-5, MSB-6, MSB-7) are available on the pads distributed around the lower right corner of the padring. The signal starting the analog-to-digital conversion is applied on the pad Sample on the top. The reference voltage used for the conversion is applied on the pad VRef (on the bottom). Around the padring are visible the pads for the ground (on the top) and for the four different used biases 1 V (on the top), 1.5 V (on the right), 2 V and 3.3 V (on the bottom). The DC voltage biasing the gate of the pull-up PMOS transistor in the pulse merger (see Fig. 7) is applied on the pad VP (on the top). The DC voltage (VCTRL) biasing the gate of the PMOS transistor in the monostable (see Fig. 5) is applied on the pad VPulse (on the top). Eventually, the DC voltage controlling the starved current in the delay cell (see Fig. 8) is applied on the pad VDelay (on the right). The twelve delay unit cells constituting the delay chain are visible in the upper right corner of the layout. The two DACs are located on the left side of the layout while the remaining blocks as the logic unit and dynamic comparator are in the lower right corner area. The layout of the DAC was designed using a common centroid approach. All the binary weighted capacitors of the DAC were split into several 75 fF capacitors and arranged as described in Fig. 10. The four “0” stand for the four 75 fF capacitors for the C capacitor in Fig. 2; similarly, the four “1” stand for the other C capacitor in Fig. 2. The capacitance C is therefore of 300 fF.
3.3. Comparator The comparator is as a dynamic latch, whose schematic is depicted in Fig. 6. As in Ref. [16], it is a flipped version of the strong-ARM latch described in Ref. [17]. In a dynamic comparator a high sensitivity, due to the intrinsic positive feedback of a cross-coupled pair of CMOS inverters (transistors M4, M5, M7, and M8 in Fig. 6), comes together with a low dissipated power, because the circuit is gated by an enabling signal. The circuit dissipates only when enabled; it is in a sleeping state during the rest of the time. In the present work, the enabling signal Enable is generated by the pulse merger circuit depicted at the bottom of Fig. 7. Each gate of the N-channel transistors in the pull-down network is controlled by a different couple of spikes generated by the delay unit cell, generally indicated as “pulse x” in Fig. 5 with x ¼ 0 … 7. Because of the operation mode of the delay chain, only one transistor at a time is on, in correspondence of the received positive spike. The size of the P-channel transistor in the pull-up network and the static voltage applied to its gate are designed in order to achieve a large swing in the Enable signal. In this
Fig. 7. Pulse merger and dynamic comparator/logic unit interface. 4
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The eight “2” stand for the eight 75 fF capacitors for the 2C capacitor in Fig. 2; identically for the other cases. All the binary weighted capacitors of the DAC share therefore the same common centroid, located in the center of the scheme. Fig. 11 shows the resulting layout of the DAC. The switching NMOS transistors in Fig. 2 are located at the bottom of the layout where the controlling signals are highlighted in red. The metal lines connecting the switched capacitor introduce parasitic capacitances that were extracted and compensated with properly sized capacitors highlighted in white in Fig. 11. Table 1 compares the nominal values of the capacitors with the extracted ones. The table reports also the introduced compensating capacitances. It shows that the compensation capacitors make the weight factors of the DAC capacitors closer to the desired ideal binary values. The performances of the designed SAR-ADC were investigated both in terms of static Figure-of-Merits (FoMs) as the Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) and of dynamic FoMs as the Equivalent Number of Bit (ENOB) and Total Harmonic Distortion (THD). As depicted in Fig. 12, the static (dynamic) FoMs were obtained by applying at the input of the SAR-ADC a slow linear ramp (a 200 Hz sinusoidal tone) and analyzing in the time (frequency) domain the signal generated by an ideal DAC connected at the output of the SAR-ADC under test. The sampling frequency (fs) was set equal to 5 kHz in both the cases. Fig. 13 shows the static FoMs simulated without parasitics extraction and therefore without parasitics compensation. Figs. 14 and 15 show the simulations carried out by accounting for the parasitic extraction without or with the capacitive compensation, respectively. Fig. 16 shows the typical signal at the output of the ideal DAC together with its spectrum in the case of a dynamic FoM simulation carried out for an extracted SARADC with uncompensated DACs. The frequency analysis extracts the ENOB, SINAD, SFDR, and THD dynamic FoMs. The following Table 2 reports the obtained static and dynamic FOMs for the three different investigated cases.
Fig. 8. Schematic of the delay cell used in the dynamic comparator/logic unit interface.
5. Discussion Fig. 13 shows that before parasitic extraction both the DNL and the INL are lower than 0.1LSB. Table 2 shows that, under the same
Fig. 9. Layout of the designed SAR-ADC prototype.
Fig. 10. Common centroid scheme adopted for the DAC. Fig. 11. Layout of the DAC with the compensating capacitors highlighted. 5
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Table 1 DAC capacitors before and after extraction, with and without compensation. Capacitor
C0 C1 C2 C3 C4 C5 C6 C7
Ideal Weight Factor
Nominal capacitance [fF]
1 1 2 4 8 16 32 64
300 300 600 1200 2400 4800 9600 19200
Without compensation Parasitic capacitance [fF]
Total Capacitance [fF]
Real Weight Factor
30 34,8 41,82 56,66 77,67 134,4 252,4 524,3
330 334,8 641,82 1256,66 2477,67 4934,4 9852,4 19724,3
1 1,01 1,94 3,81 7,51 14,95 29,86 59,77
Compensating Capacitance [fF]
0 0 27,84 82,54 200,73 422,4 861,2 1722,4
With compensation Parasitic capacitance [fF]
Total Capacitance [fF]
Real Weight Factor
30 34,84 43,47 60,03 80,22 138,5 257,8 536,3
330 334,84 671,31 1342,57 2680,95 5360,9 10719 21458,7
1 1,01 2,03 4,07 8.12 16,25 32,48 65,03
Fig. 12. Simulation set-up for static and dynamic FoMs.
Fig. 14. DNL and INL simulated with parasitic extraction and uncompensated DAC.
Fig. 13. DNL and INL simulated without parasitic extraction and without compensation.
conditions, the ENOB is 8-bit and the THD is better than 60dB. After parasitic extraction (see Fig. 14) the DNL exhibits higher values and the INL get worse not only in the values but also in the general behaviour. The introduction of the compensating capacitors leads to static FoMs, whose values and behaviour are very close to the case before extraction; Figs. 13 and 15 appear indeed very similar. This indicates that the worsening shown in Fig. 14 is largely due to the incorrect ratios in the weight factors induced by the capacitive parasitics of the metal lines connecting the DAC to the switching capacitors (see Fig. 11) [18,19]. Table 1 shows indeed that the use of the compensating capacitors allows to reproduce weight factors very close to the pre-extraction values even if, of course, the absolute capacitance of each single capacitor is different. For the SAR-ADC linearity it is not important the absolute value of each capacitor but rather that the capacitances are in a binary ratio as much as possible. Table 2 gives evidence that the main impact of the parasitics is on the linearity, in agreement with [15,20]. THD gets worse more than
Fig. 15. DNL and INL simulated with parasitic extraction and compensated DAC.
SFDR and SINAD when the parasitics are introduced without compensating them. On the other hand, when the binary weights are restored through compensation, the THD recovers the pre-extraction value. The following Table 3, Figs. 17 and 18 compare the performance of the proposed SAR ADC with those claimed in the literature. Table 3 compares the simulated FoMs reported in Table 2 with the experimental ones claimed in the literature for other 350 nm CMOS SAR-ADCs working at comparable sampling frequency. The SAR-ADC designed in the present work well compares with the literature. Fig. 17 shows the breakdown of the dissipated power. The delay chain (Fig. 5) is the most power hungry
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Fig. 16. Ideal DAC output signal (on the left) and its spectrum (on the right) in the case of extracted parasitic and uncompensated DAC1 and DAC2. Table 2 Comparison of the static and dynamic FoMs for the three investigated cases. Extraction Compensation DNL [LSB] INL [LSB] ENOB [bit] SINAD [dB] SFDR [dB] THD [dB]
No No 0.103/þ0.096 0.093/þ0.081 8.02 50.02 53.92 64.32
Yes No 0.203/þ0.195 0.278/þ0.145 7.87 49.16 53.98 57.54
Yes Yes 0.103/þ0.096 0.109/þ0.074 8.02 50.02 53.97 64.32
Table 3 FoM comparison with other 350 nm CMOS SAR-ADC.
DNL [LSB] INL [LSB] ENOB [bits] SINAD [dB] SFDR [dB] THD [dB] fs [kHz]
[10]
[11]
[47]
[14]
This work
0.18/ þ0.34 0.20/þ0.27
0.65/ þ0.52 0.84/ þ0.65 n.a.
1.5/ þ1.5 2.0/ þ2.0 n.a.
0.1/ þ0.1 0.1/ þ0.1 8.0 on 8
48.2
0.8/ þ0.8 1.4/ þ1.4 10.2 on 12 63
n.a.
n.a.
50
67.8 n.a. 2
n.a. 44.4 n.a.
n.a. n.a. 1000
n.a. n.a. 1
53.9 64.3 5
7.8 on 8
Fig. 18. Dissipated power versus sampling frequency. References for 350nm: [9], [10], [15], [21]. References for 180nm: [5–8], [10], [13], [22–31], [44], [40], [39], [38]. References for 130nm: [1], [2], [32–37]. References for 65nm: [3].
The proposed DCU works without the need of a clock. Its activity starts after the Sample pulse is received (see Fig. 3) and it stops at the end of the digitization process. Following [41] the SAR-ADC proposed in the present work can be classified as on demand. It does not exhibit switching activity in the waiting for the sampling event, putting to zero the standby dissipated power. On the other hand, a switching activity consumes current all the time in clocked or self-clocked solutions [1–15]. The control of the digitization process in the proposed DCU is based on a delay-line obtained by cascading several delay cell unit, whose core is a monostable (see Fig. 5). To the best knowledge of the authors, this is the first time that a monostable is applied to control the digitization process in a SAR ADC. In asynchronous solutions [42–44] the digital circuitry controlling the digitization process is based on a cascade of Bit Slice Unit (BSU). These digital circuits are designed by using dynamic logic, in order to reduce the number of transistors. The dynamic logic circuitry in a typical BSU counts thirteen transistors plus four inverters. The delay unit cell (see Fig. 4) proposed in the present work counts one transistor, one 2-input NOR gate and two inverters together with two capacitors and one resistor. In Ref. [45] the proposed solution is asynchronous with a digital loop in charge of generating on demand the self-clock to activate the dynamic comparator. It counts five 2-input gates, three inverters and a digital delay element. In the proposed DCU the self-synchronisation is guaranteed by the pulse merger (see Fig. 7), which is a very simple circuit common to the whole delay chain. With respect to the previously cited solutions, the proposed DCU offers therefore a reduced complexity of the digital logic even using a standard static CMOS style design. This reduced complexity is paid with an increase in the silicon area due to the use of
Fig. 17. Dissipated power breakdown.
block, responsible for about 40% of the dissipated power, followed by the voltage buffers (30%). The output register bank sinks only 3% of the total dissipated power. The remaining dissipated power is equally distributed between the delay cells and the logic unit. Moreover, Fig. 18 compares the designed SAR-ADC with the literature in terms of dissipated power and sampling rate. With the exception of four outstanding works [31,38, 39,44] and one inferior case [36], the symbols distribution in the figure describe a band defined by two lines with a slope of about 1 dec/dec. The SAR-ADC proposed in the present work stays on this band demonstrating therefore that it well compares with the state-of-art. 7
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capacitors in the monostable, as it appears in the layout (see Fig. 9). As explained in the sub-section 3.2, the mono-stable based delay unit cell offers capabilities of appeasing PVT variations. The counter- or BSU-based solutions do not offer these appeasing capabilities. This advantage is kept in the case the proposed SAR-ADC would be arranged to work in a self-clocked mode. The signal Reset generated by the delay chain could indeed be used similarly as in Ref. [41] to make self-clocked the proposed SAR-ADC even if at the cost of increasing the stand-by dissipated power. Eventually, it is worth noticing that the monostable demonstrated to be a promising alternative to the digital delay generator for low jitter delay higher than 100ns [46]. As the monostable is at the core of the delay line proposed in the present work, this seems promising in terms of intrinsic robustness against jitter.
[7]
[8]
[9]
[10]
[11]
6. Conclusions
[12]
This paper presents an 8-bit SAR-ADC designed in a low cost bulk 350 nm CMOS technology. The core of the layout consumes a silicon area of about 1500 μm 1500 μm. In particular, the layout of the DAC was designed common centroid and compensated for the parasitic capacitances introduced by the metal lines connecting the capacitor with the switches. The novelty of the proposed clock-less SAR-ADC is in the design of the control logic, which is based on the use of a delay-line, whose core is a monostable. The concept of delay for the design of the digital control circuitry was exploited also in Ref. [15] but in a different way. In addition to the use of a delay line, to the best knowledge of the authors, this paper is the first report on the use of monostables to control the digitization process of a SAR-ADC. It is worth noticing that the monostable seems to be promising for the generation of low jitter delay higher than 100ns. The proposed DCU offers the advantage of a reduced circuitry complexity with respect to the previously reported solutions where a cascade of dynamic logic BSU’s and/or more complex synchronization digital circuits are used. Moreover, the proposed DCU offers also the advantage of some capabilities of appeasing PVT induced variations. These advantages are paid with an increase of the silicon area, because of the use of capacitors in the monostable. Simulations demonstrated static and dynamic figure-of-merits well comparable with the literature. The SAR-ADC proposed in the present work well compare with the literature also in terms of dissipated power and sampling rate. The present work proves therefore that the monostable based delayline approach can be successfully applied to control the digitization process of a SAR-ADC.
[13] [14] [15]
[16]
[17] [18]
[19]
[20]
[21] [22]
[23]
[24]
[25]
Acknowledgment [26]
Austria Micro Systems is warmly acknowledged for having provided the design kit.
[27]
References [28]
[1] S. Al-Ahdab, R. Lofti, W. Serdijn, A 1-V 225-nW 1KS/s current successive approximation ADC for pacemakers, in: IEEE 6th Conference on PhD Research in Microelectronics and Electronics, July 2010, pp. 1–4. Berlin (Germany). [2] D. Zhang, A. Bhide, A. Alvandpour, A 53nW 9.12 ENOB 1kS/s SAR ADC in 0.13um CMOS for Medical Implant Devices, in: IEEE European Solid-State Circuits Conference, September 2011, pp. 467–470. Helsinki ( Finland). [3] M. Yip, A.P. Chandrakasan, A resolution-configurable 5-to-10b 0.4-to-1V power scalable SAR ADC, in: IEEE International Solid-State Circuits Conference, April 2011, pp. 190–191. San Francisco (CA). [4] N. Verma, A.,P. Chandrakasan, An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensors nodes, IEEE J. Solid State Circuits 42 (June 2007) 1196–1205. [5] A.T. Do, C.K. Lam, Y.S. Tan, K.S. Yeo, J.H. Cheong, L. Tao, M.T. Tan, M. Je, A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems, in: IEEE Asia and Pacific Conference on Circuits and Systems, December 2012, pp. 1–4. Kaohsiung (Taiwan). [6] A.T. Do, C.K. Lam, Y.S. Tan, K.S. Yeo, J.H. Cheong, X. Zou, L. Yao, K.W. Cheng, M. Je, A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications, in:
[29]
[30]
[31]
[32]
[33]
8
IEEE Int. New Circuits and Systems Conference, June 2012, pp. 525–528. Montreal (Canada),. Y. Susanti, P.K. Chan, V.K.S. Ong, An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator, in: IEEE Asia Pacific Conf. On Circuits and Systems, November-December 2008, pp. 284–287. Macao (China). Y.K. Yang, X. Liu, J. Zhou, J.H. Cheong, M. Je, W.L. Goh, A 0.5V 16nW 8.08-ENOB SAR ADC for ultra-low power sensor applications, in: IEEE Int. Microwave Workshop Series RF and Wireless Technologies for Biomedical and Healthcare Applications, December 2013, pp. 1–4. Singapore ( Singapore). X. Xu, X. Zou, L. Yao, Y. Lian, A 1-V 450-nW fully integrated biomedical sensors interface systems, in: IEEE Digest of Technical Paper Symposium on VLSI Circuits, June 2008, pp. 78–79. Honolulu (USA). W. Hu, Y.-T. Liu, T. Nguyen, D.Y.C. Lie, B.P. Ginsburg, An 8-bit single-ended ultralow-power SAR ADC with a novel DAC switching method and a counter-based digital control circuit, IEEE Trans. on Circuits and Systems – I, Regular Papers 60 (July 2013) 1726–1739. X. Zou, X. Xu, L. Yao, Y. Lian, A 1-V 450-nW fully integrated programmable biomedical sensor interface chip, IEEE J. Solid State Circuits 44 (April 2009) 1067–1077. H. Zhang, Y. Qin, S. Yang, Z. Hong, Design on an ultra-low power SAR ADC for biomedical applications, in: IEEE International Conference on Solid-State and Integrated Circuits Technology, November 2010, pp. 460–462. Shangai (China). J. Sauerbrey, D. Schmitt-Landsiedel, R. Thewes, A 0.5-V 1-uW successive approximation ADC, IEEE J. Solid State Circuits 38 (July 2003) 1261–1265. H. Wu, Y. P.Xu, A 1V 2.3 uW biomedical signal acquisition IC, in: IEEE International Conference on Solid-State Circuits, February 2006, pp. 1–4. San Francisco (CA). S. Brenna, A. Bonfanti, A.L. Lacaita, A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with Attenuation Capacitance Calibration in 0.35-um CMOS, vol. 89, November 2016, pp. 357–371. L. Zheng, L.B. Leene, Y. Liu, T.G. Costandinou, An adaptive 16/64kHz, 9-bit SAR ADC with peak-aligned sampling for neural soike recording, in: “IEEE International Symposium on Circuits and Sistems, 2014, pp. 2385–2388. Melbourne (Australia. B. Razavi, The StrongARM latch, in: IEEE Solid-State Circuits Magazine, 2015, pp. 12–17. Spring. M.P.-H. Lin, Y.-T. He, V.W.- H- Hsiao, R.-G. Chang, S.-Y. Lee, Common-centroid capacitor layout generation considering device matching and parasitic minimization, IEEE on Computer-Aided Design of Integrated Circuits and Systems 32 (July 2013) 991–1002. Y. Li, Z. Zhang, D. Chua, Y. Lian, Placement for binary-weighted capacitve array in SAR ADC using multiple weighting methods”, IEEE Trans. On Computer-Aided esign of Integrated Circuits and Systems 33 (September 2014) 1277–1287. M. Saberi, R. Lofti, K. Mafinezhad, W.A. Serdjin, Analysis of power consumption and linearity in capacitive digital-to-analog Converters used in successive approximation ADCs, IEEE Trans. On Circuits and Systems – I, Regular Papers 58 (August 2011) 1736–1748. X. Zou, X. Xu, L. Yao, Y. Lian, A 1-V 450-nW fully integrated biomedical sensor interface chip, IEEE J. Solid State Circuits 44 (Issue 4) (2009) 1067–1077. H. Zhang, Y. Qin, S. Yang, Z. Hong, Design on an ultra-low power SAR ADC for biomedical applications, in: IEEE International Conference on Solid-State and Integrated Circuits Technology, Shangai, China, 1-4 November 2010, pp. 460–462. I. Kianpour, Z. Zou, M.B. Nejad, L.R. Zheng, An 8-bit 166nW 11.25 kS/s 0.18um two-Step-SAR ADC for RFID applications Using Novel DAC Architecture, in: IEEE NORCHIP Conference, vols. 15–16, Tampere, Finland, November, 2010, pp. 1–4. R. Sekimoto, A. Shikata, H. Ishikuro, A Power Scalable SAR-ADC in 0.18um-CMOS with 0.5V Nano-Watt Operation, in: IEEE International Symposium on Access Spaces (ISAS), Yokohama, Japan, 17-19 June 2011, pp. 89–94. H. Zhang, Y. Qin, Z. Hong, A 1.8-V 770-nW biopotential acquisition system for portable Applications, in: IEEE Biomedical Circuits and Systems Conference, Beijing , China, 26-28 November 2009, pp. 93–96. S.K. Lee, S.J. Park, Y. Suh, H.J. Park, J.Y. Sim, A 1.3uW 0.6V 8.7-ENOB Successive Approximation DAC in a 0.18um CMOS, in: IEEE Digest Technical Papers Symposium on VLSI Circuits, Kyoto, Japan, 15-18 June 2009, pp. 242–243. H. Franca, M. Ataei, A. Boegli, P.-A. Farine, A 100nW 10-bit 400S/s SAR ADC for ultra low-power bio-sensing applications, IEEE International Symposium in Computational Medic and Health Technology, Himeji, Japan (1-3 September 2017) 1–4. M. Sadollahi, G. Temes, An 11-bit 250-nW 10KS/s SAR ADC with Doubled Input Range for Biomedical Applications, IEEE International Midwest Symposium on Circuits and Systems, Boston (MA), USA, 6-9 August 2017, pp. 385–388. M.-J. Seo, D.-H. Jin, Y.-D. Kim, S.-I. Hwang, J.-P. Kim, S.-T. Ryu, A 18.5nW 12-bit 1kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18um CMOS, IEEE Trans. on Circuits and Systems-I: Regular papers 65 (Issue 11) (2018) 3617–3627. S. Yim, Y. Park, S. Kim, Power efficient SAR ADC adaptive to input activity for ECG monitoring applications, in: IEEE International Symposium on Circuits and Systems, 2018, pp. 1–4. Baltimore (MA), USA. C.-E. Hsieh, S.-I. Liu, A 0.3V 10 bit 7.3fJ/conversion-step SAR ADC in 0.18um CMOS, in: IEEE Asian Solid-State Circuits Conference, 10-12 November 2014, pp. 325–328. Kaohsiung, Taiwan. P. Kamalinejad, S. Mirabbasi, V.C.M. Leung, An ultra-low-power SAR ADC with an area-efficient DAC architecture, in: IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, 15-18 May 2011, pp. 13–16. K. Abdelhalim, L. MacEachern, S. Mahmoud, A nanowatt ADC for ultra low power applications, in: IEEE International Symposium on Circuits and Systems, Kos, Greece, 21-24 May 2006, pp. 1507–1510.
M. Borgarino et al.
Microelectronics Journal 94 (2019) 104641 [41] Y. Zhang, E. Bonizzoni, F. Maloberti, A 10-b 200-kS/s 250-nA self-clocked coarsefine SAR ADC, IEEE Trans. on Circuits and Systems-II: Express Briefs 63 (Issue 10) (2016) 924–928. [42] S. Liu, Y. Shen, J. Wang, Z. Shu, A 10-bit self-clocked SAR ADC with enhanced energy efficiency for multi-sensor applications, IEEE Sens. J. 18 (Issue 10) (2018) 4223–4233. [43] P.J.A. Harpe, C. Zhou, Y. Bi, N.P. van der Meijs, X. Wang, K. Philips, G. Dolmans, H. de Groot, A 26 uW 8 bit 10MS/s asynchronous SAR ADC for low energy radios, IEEE J. Solid State Circuits 46 (Issue 7) (2011) 1585–1595. [44] Z. Zhu, Y. Liang, A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-um CMOS for Medical Implant Devices, IEEE Trans. on Circuits and Systems I, Regular Papers 62 (Issue 9) (2015) 2167–2176. [45] S. Liu, Y. Shen, Z. Zhu, A 12-bit 10 MS/s SAR ADC with high linearity and energyefficient switching, IEEE Trans. on Circuits and Systems – I: Regular papers 63 (Issue 10) (2016) 1616–1627. [46] M.S. Ansari, B. Singh, C.P. Navahe, A low jitter variable delay generator for regenerative amplifier in a table top terawatt femto second laser system, Indian J. Eng. Mater. Sci. 13 (2006) 269–274. [47] W. Liu, T. Wei, P. Guo, Y. Hu, Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors, in: IEEE International Conference on Industrial Electronics and Applications, 9-11 June 2014, pp. 867–871. Hangzhou, China.
[34] K. Abdelhalim, L. MacEachern, S. Mahmoud, A nanowatt successive approximation ADC with offset correction for implantable sensor applications, in: IEEE International Symposium on Circuits and Systems, New Orleans, USA, 27-30 May 2007, pp. 2351–2354. [35] A. Rodriguez-Perez, M. Delgado-Restituto, J. Ruiz-Amaya, F. Medeiro, An ultra-low power consumption 1-V, 10-bit successive approximation ADC, in: IEEE International Conference on Electronics, Circuits and Systems, 31 August-03 September 2008, pp. 634–637. St. Julien’s, Malta. [36] X. Yang, M. Zhao, X. Wu, Capacitor mismatch calibration method for SAR ADC with minimum area and power penalty, Electron. Lett. 54 (Issue 21) (2018) 1208–1210. [37] X. Yan, L. Fu, J. Wang, An 8-bit 100kS/s low power successive approximation register ADC for biomedical applications, in: International Conference on ASIC, vols. 28–31, October 2013, pp. 1–4. Shenzhen, China. [38] Y. Liang, Z. Zhu, A 10 bit 20 kS/s 17,7 nW 9.1 ENOB reference-insensitive SAR ADC in 0.18μm CMOS, Microelectron. J. 73 (2018) 24–29. [39] W. Guo, Z. Zhu, A 0.3V 8-bit 8.9 fJ/con.-step SAR ADC with sub-DAC merged switched for bio-sensors, Microelectron. J. 68 (2017) 44–54. [40] W. Bai, Z. Zhu, A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18μm CMOS for biomedical applications, Microelectron. J. 59 (2017) 40–46.
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