CMOS four terminal floating nullor design using a simple approach

Microelectronics Journal Microelectronics Journal 30 (1999) 1187–1194 www.elsevier.com/locate/mejo

CMOS four terminal floating nullor design using a simple approach U. C ¸ am a,*, H. Kuntman b a

b

Sakarya University, Department of Electrical and Electronics Engineering, Engineering Faculty, 54040 Esentepe, Adapazarı, Turkey Istanbul Technical University, Department of Electronics and Communication Engineering, Faculty of Electrical and Electronic Engineering, 80626 Maslak, Istanbul, Turkey

Abstract In this study a simple approach for design of four terminal floating nullor (FTFN) is introduced and two new CMOS FTFN topologies are proposed using the approach from suitable CMOS negative current conveyor (CCII2) structures. The performance of the proposed circuits was tested by Pspice computer simulation program. The feasibility of the proposed circuits was shown on a current-mode band-pass filter example constructed using one of the proposed CMOS FTFN circuits. The simulation results are given to confirm the predicted theory. q 1999 Elsevier Science Ltd. All rights reserved. Keywords: CMOS FTFN; OFA; Current-mode circuits

1. Introduction At present there is a growing interest in the design of current mode circuits owing to their potential advantages such as inherently wide bandwidth, higher slew-rate, greater linearity, wider dynamic range, simple circuitry and low power consumption [1,2]. The analogue designers mostly use second generation current conveyors (CCIIs) instead of operational amplifier (OPAMP) as an active element in analogue IC design as a result of providing advantages of voltage copying and current copying properties simultaneously [1–4]. This leads to a growing interest in the design of CCIIs using CMOS, BICMOS and bipolar technologies. Therefore several high performance current conveyor circuits both negative and positive type are available in the literature [1–6]. Recently, attention has been concentrated on the use of four terminal floating nullor (FTFN) as current-mode active element as it has been shown that the FTFN is a more flexible, versatile and stable active element than an OPAMP and a CCII [7–16]. In general the FTFN (or called OFA by Huijsing) has been implemented either as a supply current sensing method (SCSM) using an OPAMP and current mirrors, or cascode connection of the two current conveyors [9,11,16,17].

However, in modern mixed analogue/digital IC design the preferred technology is CMOS owing to the low power consumption and high integration density consideration. Hence there is a special interest for CMOS implementation of the FTFN [15]. Apart from direct design of the FTFN, it is an appropriate task that yields CMOS FTFN structures from well-established high performance CMOS CCIIs in the literature. In this study a simple approach for design of

* Corresponding author. Tel.: 190-264-343-1602; fax: 190-264-3431450. E-mail addresses: [email protected] (U. C¸am), kuntman@ ehb.itu. edu.tr (H. Kuntman) 0026-2692/99/$ - see front matter q 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00021-X

Fig. 1. Nullor.

Fig. 2. Nullor models of CCII and FTFN.

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Fig. 3. Circuit schematic of the proposed circuits.

U. C ¸ am, H. Kuntman / Microelectronics Journal 30 (1999) 1187–1194 Table 1 Dimensions of MOS devices for proposed circuits Circuit 1

W (mm)

L (mm)

Circuit 2

W (mm)

L (mm)

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21

440 440 440 260 260 100 100 100 140 140 140 400 560 560 560 140 140 140 480 140 140

10 10 10 5 5 10 10 10 20 20 20 5 20 20 20 10 10 10 10 10 10

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12

200 200 200 200 200 200 200 200 200 20 20 20

5 5 5 5 5 5 5 5 5 5 5 5

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synthesis and network analysis [17,18]. A nullor consisting of a nullator and a norator are shown in Fig. 1. Both the branch voltage and the branch current of a nullator is identically zero. The branch voltage and the current of a norator are both arbitrary [17,18]. Ideal CCII shown in Fig. 2(a) is defined by the following matrix equation: 2 3 2 32 3 iy 0 0 0 vy 6 7 6 76 7 6 vx 7 ˆ 6 1 0 0 76 ix 7; …1† 4 5 4 54 5 ix

0

b 0

vx

where the circuit is a positive current conveyor for b positive unity, when b becomes negative unity the circuit is called a negative current conveyor. The FTFN shown in Fig. 2(b) is characterised by the following port relations: vx ˆ vy ; ix ˆ iy ˆ 0;

…2†

iz ˆ iw :

FTFN is introduced and two new CMOS FTFN topologies are proposed using the approach from suitable CMOS CCII2 structures. 2. Design methodology Since its introduction in 1964 by Carlin, the nullor concept has gained widespread acceptance both in network Table 2 Device model parameter used for SPICE simulation which are taken from ¨ BI˙TAK YI˙TAL 3m CMOS process TU No

Parameter

PMOS

NMOS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Level VTO KP GAMMA PHI LAMBDA TOX LD WD JS JSW XJ NFS ECRIT UCRIT UEXP CJ CJSW MJ MJSW RSH DELTA

2 21.0 1.5 × 10 25 0.7 0.7 0.035 4.5 × 10 8 1 × 10 27 4 × 10 27 1.6 × 10 26 2.2 × 10 29 3.5 × 27 1 × 10 11 28 000 40 000 0.17 1.9 × 10 24 6.3 × 10 210 0.3 0.35 100 1

2 0.9 4.4 × 10 25 0.22 0.58 0.035 4.5 × 10 28 1-10 27 3 × 10 27 25 × 10 26 4 × 10 29 2.5 × 27 1 × 10 11 15 000 60 000 0.15 1.1 × 10 24 3 × 10 210 0.5 0.4 35 1

The nullor representation of a CCII2 and a FTFN are given in Fig. 2. If we compare these models, we observe that a CCII2 model requires both nullator and norator having a common node, in contrast the FTFN model nullator and the norator are isolated from each other. A FTFN may be easily converted to a CCII2 by connecting one of the outputs to an input of opposite polarity. Similarly a CCII2 may also be converted to an FTFN by separating the input and the output ports. Using these fact we obtain two CMOS realisations of the FTFN as shown in Fig. 3. In order to describe the operation of FTFN in Fig. 3(a) three different parts of this circuit can be distinguished. First, there is a differential input pair followed by a gain stage formed by transistors M1, M2, M3, M4 and M7. Secondly, there is a transconductance stage consisting of M8 and M9 coupled to the differential input pair in a common connection to achieve voltage-to-current conversion. The last stage consists of current mirrors M10–M21 to provide current output capability. The operation of the FTFN circuit in Fig. 3(b) can be explained as follows. The current mirror formed by M3 and M4 forces equal currents in the transistors M1 and M2 which function as a source coupled input pair. Transistor M5 is connected in the form of a source follower is a function source coupled pair. The current mirrors formed by M6, M7 and M7, M8 reflects the current in the z port to w the port while the drain currents of M11 and M12 are equal. It should be noted that the approach can be applied to CMOS CCII2s in which the common connection of the terminals are explicitly shown in the circuit schematic. These approach can be also applied for the design of operational mirrored amplifier (OMA) using positive current conveyor (CCII1) instead of CCII2.

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Fig. 4. Simulated DC transfer characteristics of the proposed circuits.

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Fig. 5. Simulated frequency response of the proposed circuits.

3. Simulation results The proposed topologies are simulated with Pspice computer program. The dimensions of MOS devices of

the circuits shown in Fig. 3 are illustrated in Table 1 [4,5]. Device model parameters used for the SPICE simula¨ BI˙TAK YI˙TAL 3m CMOS tions which are taken from TU process are given in Table 2. The simulated DC transfer

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Fig. 6. (a) Current-mode band-pass filter; (b) its frequency domain simulation result using FTFN in Fig. 3 (C1 ˆ C4 ˆ 0.5 nF, R1 ˆ 3 kV, R2 ˆ 1 kV).

characteristics of the proposed circuits are shown in Fig. 4 and the simulated frequency response of the proposed circuits are shown in Fig. 5. Supply voltages for Fig. 3(a) and (b) are taken as 10 and 5 V, respectively. Realisation of a current-mode band-pass filter shown in Fig. 6 is chosen as

an illustrating example of the proposed circuits [11]. The natural frequency and quality factor of the filter are given as: p 3C1 C4 R1 R2 ; Qˆ 3C4 R2 1 C1 R1 2 C4 R1

…3†

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Fig. 7. Variation of THD on output of the filter with input current of the filter using PSPICE simulation results.

1 v ˆ p : 3C1 C4 R1 R2

…4†

The passive components were chosen as C1 ˆ C4 ˆ 0.5 nF, R1 ˆ 3 kV, R2 ˆ 1 kV. Frequency domain Pspice simulation results using the FTFN and ideal frequency response of the filter circuit in Fig. 3(b) are given in Fig. 6 [6]. All the simulations were performed using 1 kV load. The simulation results are found to be in good agreement with the predicted theory. Further, the large signal behaviour of the filter circuit is tested by investigating the dependence of the output harmonic distortion on the input signal amplitude. The results given in Fig. 7 show that the harmonic distortion rapidly increases when the input current exceeds beyond 1400 mA level. For input signal levels lower than 1400 mA the total harmonic distortion remains in acceptable limits of the order of THD ˆ 1%. The Table 3 SPICE simulation results of output current and output voltage of the filter for different load values (IINPP ˆ 1 mA) RLOAD

IOPP

VOPP

THD (%)

1V 100 V 300 V 700 V 1 kV 2 kV 3 kV 4 kV 5 kV

1.1 mA 1.1 mA 1 mA 1 mA 1 mA 0.95 mA 0.9 mA 0.85 mA 0.82 mA

1.2 mV 102 mV 302 mV 501 m 990 mV 1.9 V 2.8 V 3.6 V 4.3 V

1.3 1.3 1.4 1.5 1.6 1.8 2.3 2.6 3.3

dependence of the output current and the output voltage of the filter on the load resistance are for input current Iin ˆ 1000 mA (pp). The simulation results are given in Table 3. It can easily be observed from Table 3 that the large output voltage amplitude even at 105 kHz frequency is provided by the current-mode operation where the output current amplitude is constant in case of a resistive load of the output voltage is determined as the product of the output current and the load resistance. Note that the filter circuit yields output voltage levels up to 4.5 V even at 105 kHz frequency where the harmonic distortion remains in acceptable levels. All the aforementioned simulations were performed using the proposed CMOS FTFN circuit in Fig. 3(b). 4. Conclusion A new and simple approach for the design of the FTFN is introduced. Two new CMOS FTFN configurations are proposed using the approach. The basic performance of the proposed circuit was demonstrated with Pspice computer simulation program. The feasibility of the circuits was tested on the current-mode band-pass filter. The proposed approach can also be used in the design of CMOS OMA realisations.

References [1] C. Toumazou, F.J. Lidjey, D. Haigh, Analog IC Design: The CurrentMode Approach, Peter Peregrinus, London, 1990.

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