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Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS
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INTEGRATION, the VLSI journal 36 (2003) 87–101
Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS$ A. Srivastava*, H.N. Venkata Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, USA Received 23 September 2002; received in revised form 3 July 2003; accepted 7 July 2003
Abstract Multiple-input floating gate MOSFETs and floating gate potential diagrams have been used for the conversion of quaternary-valued input into corresponding binary output in CMOS integrated circuit design environments. The method is demonstrated through the design of a circuit for conversion of quaternary inputs into the corresponding binary bits in a standard 1:5 mm digital CMOS technology. The physical design of the circuit is simulated and tested with SPICE using MOSIS BSIM3 model parameters. Measurements on fabricated devices for the conversion of quaternary input (decimal 0–3) into binary output (binary 00–11) have shown agreement with the corresponding simulated values. The conversion method is simple and compatible with the present CMOS process. The circuit can be embedded in digital CMOS VLSI design architectures. r 2003 Elsevier B.V. All rights reserved. Keywords: MVL; Quaternary logic; CMOS; Floating gate MOSFET; VLSI design; Neuron MOSFET
1. Introduction The performance of two levels (binary logic) is limited due to interconnections, which occupy a large area on a VLSI chip. In a VLSI chip, approximately seventy percent of the area is devoted to interconnection, twenty percent to insulation and ten percent to device [1]. One can achieve a more cost-effective way of utilizing interconnections by using a larger set of signals over the same area in multiple-valued logic (MVL). This also solves the problem of pin-out (the limit to the amount of data that can enter and exit a chip). The main drawback of multiple-valued logic devices is that their design techniques are more complex than those of binary logic devices [2]. $
Part of the work is reported in Proceedings of SPIE (Conference), vol. 4700, 2002. *Corresponding author. Tel.: +1-225-5785622; fax: +1-225-5785200. E-mail address: [email protected] (A. Srivastava).
0167-9260/$ - see front matter r 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0167-9260(03)00049-X
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Binary Data
Quaternary (4-Level) Data
t
Fig. 1. Binary and corresponding quaternary (4-level) data to reduce bandwidth.
Conversion schemes from MVL to binary logic functions are also not straightforward. Multiple decision diagrams (MDD), which are graph structures have been used to generate automatic design procedures for binary function realization. The well-known example is binary decision diagrams (BDD), an MDD with a radix of two [3]. However, the conversion scheme is not simple. Multiple-valued finite state machines have been designed in the form of quaternary sequential/ storage logic array (QSLA), which incorporates binary-to-quaternary encoders and quaternaryto-binary decoders at the primary inputs and outputs, respectively [4]. In present communication systems, multi-level signals are preferred over binary signals to improve the quality of signal processing. A good example is the use of quaternary-level data over the binary bits as shown in Fig. 1, which requires half the bandwidth for transmission of binary data [5]. Conversion from binary data to quaternary data can be easily achieved through digital-to-analog converter (DAC) and subsequent conversion of the analog signal to a multi-level data (quaternary) through an ADC in a transceiver system. Several methods have been proposed to convert quaternary data into binary bits [4,6–8]. Some of these circuits use the method of voltage division [4,6,7]. These circuits have large delays due to large number of transistors and dissipate static power. However, the method given here uses a simple and novel approach to convert quaternary data into binary bits in a standard CMOS technology using multiple-input floating gate MOSFETs. In following sections, a conversion scheme from quaternary-valued input into corresponding binary output is discussed in CMOS design environment using multiple-input floating gate MOSFETs, which is compatible with the standard CMOS process. Simulated and measured results from the fabricated device are presented and discussed.
2. Multiple-input floating gate (MIFG) MOSFET Fig. 2 shows the cross-section of a multiple-input floating gate (MIFG) MOSFET [9]. It consists of an n-MOSFET with an electrically floating-gate electrode. The floating gate in the MOSFET extends over the channel and the field oxide. Arrays of control gates, which are inputs to the transistor, are formed over the floating gate using a second polysilicon layer. Fig. 3 shows capacitive coupling between the multiple-input gates and the floating gate and the channel. In Fig. 3, C1 ; C2 ; C3 ; y; Cn are the coupling capacitors between the floating gate and the inputs. The corresponding terminal voltages are V1 ; V2 ; V3 ; y; Vn ; respectively. C0 is the capacitor
ARTICLE IN PRESS A. Srivastava, H.N. Venkata / INTEGRATION, the VLSI journal 36 (2003) 87–101 V1
V2
V3
89
Vn
Input Gates
Thin Oxide Floating Gate Thin Oxide n+
n+ p-Si
Fig. 2. Basic structure of a multiple-input floating gate MOSFET.
V1
C1
V2
Vn
V3
Cn
C3
C2
ΦF
Floating Gate
C0 VSS
Fig. 3. Relationship among terminal voltages and coupling capacitors of a multiple-input floating gate MOSFET.
between the floating gate and substrate. Vss is the substrate voltage. Q1 ; Q2 ; Q3 ; y; Qn are charges stored in corresponding capacitors C1 ; C2 ; C3 ; y; Cn ; respectively. At any instant, net charge QF ðtÞ on the floating gate is given by [9,10] n n X X ðQi ðtÞÞ ¼ Ci ðFF ðtÞ Vi ðtÞÞ ð1Þ QF ðtÞ ¼ Q0 þ i¼1
i¼0
or QF ðtÞ ¼ FF ðtÞ
n X i¼0
Ci
n X i¼0
Ci Vi ðtÞ;
ð2Þ
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where n is the number of inputs, Q0 is the initial charge present on the floating gate, Qi ðtÞ is the charge present in capacitor Ci and FF ðtÞ is the potential at the floating gate. Setting VSS ¼ 0V and applying the law of conservation of charge at the floating gate, Eq. (2) can be expressed as follows: Pn P ni¼1 Ci Vi ð0Þ i¼1 Ci Vi ðtÞ Pn : ð3Þ FF ðtÞ ¼ FF ð0Þ þ i¼0 Ci Assuming zero initial charge on the floating gate in Eq. (2), Eq. (3) reduces to Pn i¼1 Ci Vi ðtÞ : FF ðtÞ ¼ P n i¼0 Ci
ð4Þ
Switching ON or OFF of the n-MOSFET depends on whether FF ðtÞ is greater than or less than the threshold voltage of the transistor. Multiple-input floating gate CMOS inverter is shown in Fig. 4. V1 ; V2 ; V3 ; y; Vn are input voltages and C1 ; C2 ; C3 ; y; Cn are corresponding input capacitors. Eq. (4) is used to determine voltage on the floating gate of the inverter. Weighted sum of all inputs is performed at the gate and is converted into a multiple-valued input voltage, Vin at the floating gate. The switching of the floating gate CMOS inverter depends on whether Vin (obtained from the weighted sum) is greater
VDD
Vn
IN VOUT V3 CL
V2 V1
VSS Fig. 4. Multiple-input floating gate CMOS inverter.
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than or less than the inverter threshold voltage or inverter switching voltage ðFinv Þ: The switching voltage is computed from the voltage transfer characteristics of a standard CMOS inverter [11,12] and is given by ðFg0 þ Fs1 Þ : ð5Þ Finv ¼ 2 In Eq. (5), Fg0 and Fs1 are the input voltages at which the output Vout is VDD -0.1V and 0.1V, respectively. Hence, the output ðVout Þ of MIFG CMOS inverter is Vout ¼ HIGHð3VÞ
if FF oFinv
¼ INTERMEDIATEðVDD =2Þ if FF ¼ Finv ¼ LOWð0VÞ if FF > Finv :
ð6Þ
The capacitance network in an n-input floating gate CMOS inverter is shown in Fig. 5. The gate oxide capacitance of p-MOSFET, Coxp is between the floating gate and N-well and is connected to VDD : Coxn is between the floating gate and substrate and is connected to VSS : Cp is the capacitance formed between polysilicon floating gate and substrate. Voltage on the floating gate is given by V1 C1 þ V2 C2 þ V3 C3 þ ? þ Vn Cn þ VDD Coxp : ð7Þ FF ¼ C1 þ C2 þ C3 þ ? þ Cn þ Coxn þ Coxp þ Cp VSS is a reference ground potential. In the following section, floating gate potential diagram (FPD) [10] is used for the design of quaternary to binary data output circuit in CMOS using floating gate MOSFETs. In FPD, FF is plotted as a function of multiple-input voltage, Vin :
Coxp
VDD (N-well substrate)
Vn Cn
Cp VSS V3
Coxn C3
V2
Floating Gate C2
V1 C1
Fig. 5. Capacitive network in an n-input floating gate CMOS inverter.
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3. Conversion from quaternary logic (4-level data) to binary bits Table 1 shows the quaternary logic values and corresponding binary bits. Decimal numbers are also included in Table 1. Logic levels 0, 1, 2, 3 are defined as 0V, 1V, 2V and 3V, respectively in a 3V CMOS design. In Table 1, each quaternary input ðVIN Þ has two binary output bits, MSB and LSB. The MSB is logic LOW (0V) for quaternary inputs 0 (0V) and 1 (1V) and is logic HIGH (3V) for quaternary inputs 2 (2V) and 3 (3V). Fig. 6 shows the FPD for the MSB. In Fig. 6, potential on the floating gate is below the switching threshold voltage for quaternary inputs 0 (0V) and 1 (1V) and above the switching threshold voltage for quaternary inputs 2 (2V) and 3 (3V). With an invert operation, MSB of Table 1 is obtained. The corresponding circuit diagram is shown in Fig. 7. The switching threshold line ð1:45VÞ is also shown in the figure. From Fig. 6, the output MSB can be designed with a single capacitor C1 at the input of the floating gate CMOS inverter. Using Eq. (7), we obtain for quaternary input 0 (0V), 0V C1 þ 3V Coxp oFinv ð1:45VÞ: C1 þ Coxn þ Coxp þ Cp
ð8Þ
Table 1 Quaternary logic (4-valued) and corresponding binary bits and decimal number Decimal number
Quaternary logic
Binary bits
0 1 2 3
0 1 2 3
00 01 10 11
γVDD
ΦF,V
Φinv
0(0V)
1.45V
2(2V)
1(1V)
3(3V)
Vin,V
Fig. 6. FPD for the conversion of quaternary to MSB output.
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VDD
W/L = 16.0µm/1.6µm #1 C1 500fF
#2
VIN
MSB
CL W/L = 16.0µm/1.6µm
0.1pF
VSS
Fig. 7. Circuit diagram for implementation of quaternary logic to binary logic—MSB using floating gate MOSFETs.
For the quaternary input 1 (1V), 1V C1 þ 3V Coxp oFinv ð1:45VÞ: C1 þ Coxn þ Coxp þ Cp For the quaternary input 2 (2V), 2V C1 þ 3V Coxp > Finv ð1:45VÞ: C1 þ Coxn þ Coxp þ Cp and for the quaternary input 3 (3V), 3V C1 þ 3V Coxp > Finv ð1:45VÞ: C1 þ Coxn þ Coxp þ Cp
ð9Þ
ð10Þ
ð11Þ
Since the transistor switches so fast, Cox can be considered to be constant [13]. For W =L ¼ 16:0mm=1:6mm; Cox is given by 16:0mm 1:6mm 3:9 8:854F=cm Cox ¼ E30fF: ð12Þ 300 108 cm Taking layout constraints into consideration for 1:5mm CMOS technology, a unit capacitance of 500fF is considered. Hence the input capacitors to the circuit need to be an integer multiple of 500fF. From layout extraction, a unit capacitance of 500fF gives 40fF of parasitic capacitance
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ðCp1 Þ: Cp can be then computed as follows: Cp ¼
40fF C1 : 500fF
ð13Þ
Substituting the values of Coxn (30fF), Coxp (30fF) and Cp using Eqs. (12) and (13) in Eqs. (8)– (11), value of C1 is obtained. The smallest value of C1 that satisfies the above inequalities is 500fF. Substituting the value of C1 in Eq. (13), the value of Cp is 40fF. The output of MIFG inverter needs to be inverted to get final output as shown in the Table 1. Hence a CMOS inverter #2 is introduced at the output of MIFG inverter, which inverts the output as well as buffers, the signal generated by MIFG inverter. From Table 1, the LSB bit is LOW (0V) for logic inputs 0 (0V) and 2 (2V) and is HIGH (3V) for inputs 1 (1V) and 3 (3V). Fig. 8 shows FPD for the LSB. In Fig. 8, the potential on the floating gate is below the switching threshold line for inputs 0 (0V) and 2 (2V) and above the switching threshold line for inputs 1 (1V) and 3 (3V). We also observe that the voltage on floating gate falls below threshold line for input 2 (2V). The slope of the line can be adjusted to obtain an operating range of Finv for reliable circuit operation. The corresponding circuit diagram is shown in Fig. 9. A pre-input gate inverter stage (#3) is required to control the voltage on floating gate, such that the output of the pre-input inverter stage goes LOW (0V) for inputs 2 (2V) and 3 (3V). The capacitors C2 and C3 are the input capacitors for the MIFG inverter. Capacitor C3 is controlled by quaternary input and capacitor C2 is controlled by output of pre-input gate inverter stage. The voltage on the floating gate of MIFG inverter is given by FF ¼
VIN C3 þ V1 C2 þ 3V Coxp : C2 þ C3 þ Coxn þ Coxp þ Cp
ð14Þ
γVDD
ΦF,V
Φinv
0(0V)
1.45V
1(1V)
2(2V)
3(3V)
Vin,V Fig. 8. FPD for the conversion of quaternary to LSB output.
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VDD
C4 500fF
C2 500fF W/L= 16.0µm/ 1.6µm
#4
#3 VIN
W/L= 16.0µm/1.6µm #5 LS B
C3 1000fF W/L= 16.0µm/ 1.6µm
W/L= 16.0µm/1.6µm
CL 0.1pF
VSS
Fig. 9. Circuit diagram for implementation of quaternary logic to binary logic—LSB using floating gate MOSFETs.
Inequalities for four quaternary inputs can be obtained from Eq. (14). For the quaternary input 0 (0V), 0V C3 þ 3V C2 þ 3V Coxp oFinv ð1:45VÞ: C2 þ C3 þ Coxp þ Coxn þ Cp
ð15Þ
For the quaternary input 1 (1V), 1V C3 þ 3V C2 þ 3V Coxp > Finv ð1:45VÞ: C2 þ C3 þ Coxp þ Coxn þ Cp
ð16Þ
For the quaternary input 2 (2V), 2V C3 þ 0V C2 þ 3V Coxp oFinv ð1:45VÞ: C2 þ C3 þ Coxp þ Coxn þ Cp
ð17Þ
For the quaternary input 3 (3V), 3V C3 þ 0V C2 þ 3V Coxp > Finv ð1:45VÞ: C2 þ C3 þ Coxp þ Coxn þ Cp
ð18Þ
A unit capacitance of 500fF gives 40fF of parasitic capacitance ðCp1 Þ: The value of Cp is given by Cp ¼
40fF ðC2 þ C3 Þ : 500fF
ð19Þ
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C2 and C3 are obtained by substituting value of Coxn (30fF), Coxp (30fF) and Cp from Eqs. (12) and (19) in Eqs. (15)–(18). The above inequalities are satisfied when the capacitance of C3 is greater than the capacitance of C2 : Capacitors C2 and C3 are found to be 500fF and 1000fF, which satisfy the above inequalities. Substituting the value of C2 and C3 in Eq. (19), the value of Cp is 120fF. The pre-input inverter stage controlling the capacitor C2 is to be designed such that the output of the inverter stage is HIGH (3V) for inputs 0 (0V) and 1 (1V) and is LOW (0V) for inputs 2 (2V) and 3 (3V). Using Eq. (7), the inequalities are found, for quaternary input 0 (0V), 0V C4 þ 3V Coxp oFinv ð1:45VÞ: C4 þ Coxn þ Coxp þ Cp
ð20Þ
For the quaternary input 1 (1V) 1V C4 þ 3V Coxp oFinv ð1:45VÞ: C4 þ Coxn þ Coxp þ Cp
ð21Þ
For the quaternary input 2 (2V) 2V C4 þ 3V Coxp > Finv ð1:45VÞ: C4 þ Coxn þ Coxp þ Cp For the quaternary input 3 (3V) 3V C4 þ 3V Coxp > Finv ð1:45VÞ: C4 þ Coxn þ Coxp þ Cp
ð22Þ
The value of Cp is given by Cp ¼
40fF C4 : 500fF
ð23Þ
The above inequalities are satisfied when the capacitance of C4 X500fF: The pre-input inverter stage (#3) for the LSB bit is observed to be same as the MIFG inverter (#1) in MSB bit circuit. Hence the output of MIFG inverter of MSB bit can be used to control the capacitor C2 instead of a pre-input inverter stage. Fig. 10 shows the full circuit level implementation of quaternary input into binary bit conversion, which is obtained from Figs. 7 and 9. In Fig. 10, the capacitors are in an integer multiple of 500fF unit size capacitors in AMI 1:5mm n-well CMOS process. The inverter switching threshold voltage ðFinv Þ is 1:45V: The physical design of the circuit is simulated with SPICE using MOSIS BSIM3 model parameters. An output capacitive load of 0.1pF has been included in simulation. A piece-wise linear voltage source with 0:1ns rise time and fall time with 40ns pulse width is given at input of the circuit. Fig. 11 shows the MSB and LSB outputs. The propagation delay is measured from the time where the input reaches 50% of its maximum value to the time where the output reaches 50% of its maximum value. Table 2 summarizes the propagation delays obtained by setting initial conditions of the floating gate voltages to zero. The maximum tpLH ¼ 6ns for input transitions from logic 2ð2VÞ-logic 1ð1VÞ and tpHL ¼ 5ns for input transition from logic 1ð1VÞ-logic 2ð2VÞ are measured from simulations.
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VDD
C1 500fF
#2
#1
MSB CL 0.1pF
VSS VDD Vin C2 500fF #4
#5 LSB CL 0.1pF
C3 1000fF
VSS
Fig. 10. Full circuit diagram for conversion of quaternary (4-valued) logic to binary bits using floating gate MOSFETs.
4. Experimental results Fig. 12 shows the photograph of a fabricated chip by AMI 1:5mm standard CMOS process. Fig. 13 shows the oscilloscope photograph of quaternary input, MSB and LSB outputs. A reduced inverter switching threshold voltage value of 1.15V was measured from the voltage transfer characteristics on five fabricated chips with voltage variation less than 50mV: The observed reduced shift in inverter switching threshold voltage from 1.45–1:15V is due to variation in process-dependent MOS model parameters. The circuit of Fig. 10 was re-simulated from the BSIM3 models parameters of the fabricated chip. The fabricated chip was tested for the input voltage varying in steps from 0 to 3V. Table 3 summarizes the designed and measured quaternary inputs and output bit voltage values. From measured and designed data obtained from simulation, we observe that the maximum measured voltage that results in output corresponding to logic 2 is 1.6V rather than designed 2V: With 1.6V as logic 2, the design was re-simulated for all possible transitions in the input to measure propagation delays. A piece-wise linear input voltage with 5ns rise time and fall time was applied at the input. A 15pF load capacitance was added at the output as probe capacitance. Simulated and measured propagation delays are summarized in Table 4. The conversion circuit shown in Fig. 10 has a total of eight transistors, four MIFG transistors and four CMOS transistors. An approximate of 75% reduction in transistor count is obtained, when compared to previous circuits found in literature [4,6,8], which corresponds to
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Quat-In, V
3 2 1 0
MSB, V
3 2 1 0
LSB, V
3 2 1 0 0.00E+00
1.00E-07
2.00E-07
3.00E-07
4.00E-07
5.00E-07
t, s
Fig. 11. Simulated MSB and LSB output response of the circuit of Fig. 10 for all Possible combinations of the quaternary input. Table 2 Simulated values of propagation delays for the physical design of circuit of Fig. 10 for 0.1pF load capacitance Logic level transition (quaternary logic)
MSB tpd (ns)
LSB tpd (ns)
0-1 1-2 2-3 3-2 2-1 1-0 0-2 2-0 0-3 3-0 1-3 3-1
— 1.92 — — 1.52 — 2.03 1.14 1.51 1.22 1.43 1.63
3.46 4.97 1.19 2.10 6.02 1.02 — — 0.70 0.85 — —
Note: A dash (—) indicates that the data could not be obtained.
significant area reduction though 0.5 and 1pF capacitors are used in design. It is worth mentioning that design can also be implemented using reduced capacitors, which are limited in size due to parasitic capacitance.
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Fig. 12. Chip photograph of a quaternary to binary bits conversion device.
QUAT-IN, V
MSB, V
LSB, V
T, µS
Fig. 13. Oscilloscope photograph of a quaternary input, MSB and LSB outputs. (Horizontal axis: 0:22mS=DIV; Vertical axis: 2V/DIV.)
5. Conclusion A simple conversion scheme from quaternary to binary bit is presented in a standard CMOS process using multiple-input floating gate MOSFETS. The designed circuit was fabricated in AMI 1:5mm n-well CMOS process and was tested for performance. All quaternary logic levels agree with the corresponding binary bits except the logic 2 (2V), which was measured at 1.6V for logic 2 due to possible process variations. The circuit can be easily embedded in digital CMOS design
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Table 3 Designed and measured quaternary input and binary output bit voltage values Quaternary input-design value (V) 0.0 1.0 2.0 3.0
Quaternary input measured value (V) 0.0 1.0 1.6 3.0
MSB
LSB
Simulated (V)
Measured (V)
Simulated (V)
Measured (V)
0.0 0.01 3.0 3.0
0.0 0.01 3.0 3.0
0.0 3.0 0.09 3.0
0.0 3.0 0.0 3.0
Table 4 Measured and simulated propagation delays Logic level transition quaternary logic 0-1 1-2 2-3 3-2 2-1 1-0 0-2 2-0 0-3 3-0 1-3 3-1
MSB
LSB
Simulated tpd (ns)
Measured tpd (ns)
Simulated tpd (ns)
Measured tpd (ns)
— 11 — — 11 — 12 8 11 8 11 10
— 12 — — 12 — 14 9 12 10 12 11
11 13 9 12 17 10 — — 8 7 — —
13 — 10 15 20 11 — — 9 9 — —
Note: A dash (—) indicates that the data could not be obtained.
architectures and used in a sensor readout electronics for transmission of data with reduced bandwidth requirements over a long distance [14]. The circuit could be also integrated with the front-end sensor readout circuit for direct conversion of quaternary-level voltages into corresponding binary-level voltages. The method can also be applied for ternary to binary bit conversion CMOS integrated circuit design [15]. Such conversion designs have useful application to process a larger set of signals in a relatively small area which otherwise would occupy a large space in a binary design due to interconnections.
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[3] R. Bryant, Symbolic Boolean manipulation with ordered binary decision diagrams, ACM Computing Surveys 24 (3) (1992) 293–318. [4] N.R. Shanbhag, D. Nagchoudhuri, R.E. Siferd, G.S. Vishweswaran, Quaternary logic circuits in 2 mm CMOS technology, IEEE J. Solid-State Circuits 25 (1990) 790–799. [5] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, 2001. [6] J.L. Mangin, K.W. Current, Characteristics of prototype CMOS quaternary logic encoder-decoder circuits, IEEE Trans. Comput. C-35 (1986) 157–161. [7] K.W. Current, Current-mode multiple-valued logic circuits, IEEE J. Solid-State Circuits 29 (1994) 95–107. [8] I.M. Thoidis, D. Soudris, I. Karafyllidis, A. Thanailakis, The design of low power multiple-valued logic encoder and decoder circuits, Proceedings of the Sixth IEEE International Conference on Electronics, Circuits and Systems, Vol. 3, September 1999, pp. 1623–1626. [9] T. Shibata, T. Ohmi, An intelligent MOS transistor featuring gate-level weighted sum and threshold operations, IEDM Tech. Dig. (1991) 919–922. [10] T. Shibata, T. Ohmi, A functional MOS transistor featuring gate-level weighted sum and threshold operations, IEEE Trans. Electron Dev. 39 (6) (1992) 1444–1455. [11] A. Luck, S. Jung, R. Brederlow, R. Thewes, K. Goser, W. Weber, On the design robustness of threshold logic gates using multi-input floating gate MOS transistors, IEEE Trans. Electron Dev. 47 (2000) 1231–1239. [12] W. Weber, S.J. Prange, R. Thewes, E. Wohlrab, A. Luck, On the application of the neuron MOS transistor principle for modern VLSI design, IEEE Trans. Electron Dev. 43 (1996) 1700–1708. [13] N. Weste, K. Eshraghian, Principles of CMOS VLSI Design—A Systems Perspective, Section 4.3.2, AddisonWesley, Reading, MA, 1988, p. 125. [14] A. Srivastava, H.N. Venkata, P.K. Ajmera, A novel scheme for a higher bandwidth sensor readout, Proc. SPIE 4700 (2002) 17–28. [15] H.N. Venkata, Ternary and quaternary logic to binary bit conversion CMOS integrated circuit design using multiple input floating gate MOSFETs, MS Thesis, Louisiana State University, Baton Rouge, December 2002.
Ashok Srivastava received B.Sc., B.Sc. (Hons.) and M.Sc. (Physics-Advanced Electronics) degrees from the University of Lucknow, India, in 1968, 1969, and 1970, respectively. He obtained M. Tech. and Ph.D. degrees in Solid State Physics and Semiconductor Electronics area from Indian Institute of Technology, Delhi in 1970 and 1975, respectively. Currently, he is an Associate Professor of Electrical and Computer Engineering at Louisiana State University in Baton Rouge. During a 2001 sabbatical, he has worked at the Philips Research Laboratory, Eindhoven, Netherlands in RF passive integrated circuits design for implementation in MEMS technology for mobile communications. He has previously served as a Scientist at the Central Electronics Engineering Research Institute, Pilani, India, and was on the faculty in EEE Department of Birla Institute of Technology and Science, Pilani, India; Department of Electrical and Computer Engineering of North Carolina State University, Raleigh; State University of New York, New Paltz; University of Cincinnati, Cincinnati and as a UNESCO Fellow; as a Visiting Scientist and UNESCO Fellow at the University of Arizona, Tucson. He is the author of about 70 technical papers, including conference proceedings and book chapter in areas of integrated circuits covering CMOS, Bipolar, BiCMOS, SOI-CMOS and GaAs technologies. His current research interests include low-power digital, analog/mixed-signal CMOS VLSI circuit design; CMOS-MEMS microsystem integration and smart sensors; RF MEMS and integrated circuits; semiconductor device modeling; radiation-hardened integrated circuits; and low-temperature electronics. He is a senior member of IEEE, Electron Devices, Circuits and Systems, and Solid-State Circuits Societies, and member of SPIE, and Cryogenic Society of America. Harish N. Venkata was born in Hyderabad, India on 30 November 1977. He has received his B.S. in Electronics and Communication Engineering from Sri Venkateswara University, Tirupati in 1999, and M.S. in Electrical Engineering from Louisiana State University in 2002. His research interests include multiple-valued logic VLSI design, floating gate devices and capacitor-based architectures. He is currently working as a design engineer at Micron Technology Inc., Texas.
INTEGRATION, the VLSI journal 36 (2003) 87–101
Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS$ A. Srivastava*, H.N. Venkata Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, USA Received 23 September 2002; received in revised form 3 July 2003; accepted 7 July 2003
Abstract Multiple-input floating gate MOSFETs and floating gate potential diagrams have been used for the conversion of quaternary-valued input into corresponding binary output in CMOS integrated circuit design environments. The method is demonstrated through the design of a circuit for conversion of quaternary inputs into the corresponding binary bits in a standard 1:5 mm digital CMOS technology. The physical design of the circuit is simulated and tested with SPICE using MOSIS BSIM3 model parameters. Measurements on fabricated devices for the conversion of quaternary input (decimal 0–3) into binary output (binary 00–11) have shown agreement with the corresponding simulated values. The conversion method is simple and compatible with the present CMOS process. The circuit can be embedded in digital CMOS VLSI design architectures. r 2003 Elsevier B.V. All rights reserved. Keywords: MVL; Quaternary logic; CMOS; Floating gate MOSFET; VLSI design; Neuron MOSFET
1. Introduction The performance of two levels (binary logic) is limited due to interconnections, which occupy a large area on a VLSI chip. In a VLSI chip, approximately seventy percent of the area is devoted to interconnection, twenty percent to insulation and ten percent to device [1]. One can achieve a more cost-effective way of utilizing interconnections by using a larger set of signals over the same area in multiple-valued logic (MVL). This also solves the problem of pin-out (the limit to the amount of data that can enter and exit a chip). The main drawback of multiple-valued logic devices is that their design techniques are more complex than those of binary logic devices [2]. $
Part of the work is reported in Proceedings of SPIE (Conference), vol. 4700, 2002. *Corresponding author. Tel.: +1-225-5785622; fax: +1-225-5785200. E-mail address: [email protected] (A. Srivastava).
0167-9260/$ - see front matter r 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0167-9260(03)00049-X
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Binary Data
Quaternary (4-Level) Data
t
Fig. 1. Binary and corresponding quaternary (4-level) data to reduce bandwidth.
Conversion schemes from MVL to binary logic functions are also not straightforward. Multiple decision diagrams (MDD), which are graph structures have been used to generate automatic design procedures for binary function realization. The well-known example is binary decision diagrams (BDD), an MDD with a radix of two [3]. However, the conversion scheme is not simple. Multiple-valued finite state machines have been designed in the form of quaternary sequential/ storage logic array (QSLA), which incorporates binary-to-quaternary encoders and quaternaryto-binary decoders at the primary inputs and outputs, respectively [4]. In present communication systems, multi-level signals are preferred over binary signals to improve the quality of signal processing. A good example is the use of quaternary-level data over the binary bits as shown in Fig. 1, which requires half the bandwidth for transmission of binary data [5]. Conversion from binary data to quaternary data can be easily achieved through digital-to-analog converter (DAC) and subsequent conversion of the analog signal to a multi-level data (quaternary) through an ADC in a transceiver system. Several methods have been proposed to convert quaternary data into binary bits [4,6–8]. Some of these circuits use the method of voltage division [4,6,7]. These circuits have large delays due to large number of transistors and dissipate static power. However, the method given here uses a simple and novel approach to convert quaternary data into binary bits in a standard CMOS technology using multiple-input floating gate MOSFETs. In following sections, a conversion scheme from quaternary-valued input into corresponding binary output is discussed in CMOS design environment using multiple-input floating gate MOSFETs, which is compatible with the standard CMOS process. Simulated and measured results from the fabricated device are presented and discussed.
2. Multiple-input floating gate (MIFG) MOSFET Fig. 2 shows the cross-section of a multiple-input floating gate (MIFG) MOSFET [9]. It consists of an n-MOSFET with an electrically floating-gate electrode. The floating gate in the MOSFET extends over the channel and the field oxide. Arrays of control gates, which are inputs to the transistor, are formed over the floating gate using a second polysilicon layer. Fig. 3 shows capacitive coupling between the multiple-input gates and the floating gate and the channel. In Fig. 3, C1 ; C2 ; C3 ; y; Cn are the coupling capacitors between the floating gate and the inputs. The corresponding terminal voltages are V1 ; V2 ; V3 ; y; Vn ; respectively. C0 is the capacitor
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V2
V3
89
Vn
Input Gates
Thin Oxide Floating Gate Thin Oxide n+
n+ p-Si
Fig. 2. Basic structure of a multiple-input floating gate MOSFET.
V1
C1
V2
Vn
V3
Cn
C3
C2
ΦF
Floating Gate
C0 VSS
Fig. 3. Relationship among terminal voltages and coupling capacitors of a multiple-input floating gate MOSFET.
between the floating gate and substrate. Vss is the substrate voltage. Q1 ; Q2 ; Q3 ; y; Qn are charges stored in corresponding capacitors C1 ; C2 ; C3 ; y; Cn ; respectively. At any instant, net charge QF ðtÞ on the floating gate is given by [9,10] n n X X ðQi ðtÞÞ ¼ Ci ðFF ðtÞ Vi ðtÞÞ ð1Þ QF ðtÞ ¼ Q0 þ i¼1
i¼0
or QF ðtÞ ¼ FF ðtÞ
n X i¼0
Ci
n X i¼0
Ci Vi ðtÞ;
ð2Þ
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where n is the number of inputs, Q0 is the initial charge present on the floating gate, Qi ðtÞ is the charge present in capacitor Ci and FF ðtÞ is the potential at the floating gate. Setting VSS ¼ 0V and applying the law of conservation of charge at the floating gate, Eq. (2) can be expressed as follows: Pn P ni¼1 Ci Vi ð0Þ i¼1 Ci Vi ðtÞ Pn : ð3Þ FF ðtÞ ¼ FF ð0Þ þ i¼0 Ci Assuming zero initial charge on the floating gate in Eq. (2), Eq. (3) reduces to Pn i¼1 Ci Vi ðtÞ : FF ðtÞ ¼ P n i¼0 Ci
ð4Þ
Switching ON or OFF of the n-MOSFET depends on whether FF ðtÞ is greater than or less than the threshold voltage of the transistor. Multiple-input floating gate CMOS inverter is shown in Fig. 4. V1 ; V2 ; V3 ; y; Vn are input voltages and C1 ; C2 ; C3 ; y; Cn are corresponding input capacitors. Eq. (4) is used to determine voltage on the floating gate of the inverter. Weighted sum of all inputs is performed at the gate and is converted into a multiple-valued input voltage, Vin at the floating gate. The switching of the floating gate CMOS inverter depends on whether Vin (obtained from the weighted sum) is greater
VDD
Vn
IN VOUT V3 CL
V2 V1
VSS Fig. 4. Multiple-input floating gate CMOS inverter.
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than or less than the inverter threshold voltage or inverter switching voltage ðFinv Þ: The switching voltage is computed from the voltage transfer characteristics of a standard CMOS inverter [11,12] and is given by ðFg0 þ Fs1 Þ : ð5Þ Finv ¼ 2 In Eq. (5), Fg0 and Fs1 are the input voltages at which the output Vout is VDD -0.1V and 0.1V, respectively. Hence, the output ðVout Þ of MIFG CMOS inverter is Vout ¼ HIGHð3VÞ
if FF oFinv
¼ INTERMEDIATEðVDD =2Þ if FF ¼ Finv ¼ LOWð0VÞ if FF > Finv :
ð6Þ
The capacitance network in an n-input floating gate CMOS inverter is shown in Fig. 5. The gate oxide capacitance of p-MOSFET, Coxp is between the floating gate and N-well and is connected to VDD : Coxn is between the floating gate and substrate and is connected to VSS : Cp is the capacitance formed between polysilicon floating gate and substrate. Voltage on the floating gate is given by V1 C1 þ V2 C2 þ V3 C3 þ ? þ Vn Cn þ VDD Coxp : ð7Þ FF ¼ C1 þ C2 þ C3 þ ? þ Cn þ Coxn þ Coxp þ Cp VSS is a reference ground potential. In the following section, floating gate potential diagram (FPD) [10] is used for the design of quaternary to binary data output circuit in CMOS using floating gate MOSFETs. In FPD, FF is plotted as a function of multiple-input voltage, Vin :
Coxp
VDD (N-well substrate)
Vn Cn
Cp VSS V3
Coxn C3
V2
Floating Gate C2
V1 C1
Fig. 5. Capacitive network in an n-input floating gate CMOS inverter.
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3. Conversion from quaternary logic (4-level data) to binary bits Table 1 shows the quaternary logic values and corresponding binary bits. Decimal numbers are also included in Table 1. Logic levels 0, 1, 2, 3 are defined as 0V, 1V, 2V and 3V, respectively in a 3V CMOS design. In Table 1, each quaternary input ðVIN Þ has two binary output bits, MSB and LSB. The MSB is logic LOW (0V) for quaternary inputs 0 (0V) and 1 (1V) and is logic HIGH (3V) for quaternary inputs 2 (2V) and 3 (3V). Fig. 6 shows the FPD for the MSB. In Fig. 6, potential on the floating gate is below the switching threshold voltage for quaternary inputs 0 (0V) and 1 (1V) and above the switching threshold voltage for quaternary inputs 2 (2V) and 3 (3V). With an invert operation, MSB of Table 1 is obtained. The corresponding circuit diagram is shown in Fig. 7. The switching threshold line ð1:45VÞ is also shown in the figure. From Fig. 6, the output MSB can be designed with a single capacitor C1 at the input of the floating gate CMOS inverter. Using Eq. (7), we obtain for quaternary input 0 (0V), 0V C1 þ 3V Coxp oFinv ð1:45VÞ: C1 þ Coxn þ Coxp þ Cp
ð8Þ
Table 1 Quaternary logic (4-valued) and corresponding binary bits and decimal number Decimal number
Quaternary logic
Binary bits
0 1 2 3
0 1 2 3
00 01 10 11
γVDD
ΦF,V
Φinv
0(0V)
1.45V
2(2V)
1(1V)
3(3V)
Vin,V
Fig. 6. FPD for the conversion of quaternary to MSB output.
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VDD
W/L = 16.0µm/1.6µm #1 C1 500fF
#2
VIN
MSB
CL W/L = 16.0µm/1.6µm
0.1pF
VSS
Fig. 7. Circuit diagram for implementation of quaternary logic to binary logic—MSB using floating gate MOSFETs.
For the quaternary input 1 (1V), 1V C1 þ 3V Coxp oFinv ð1:45VÞ: C1 þ Coxn þ Coxp þ Cp For the quaternary input 2 (2V), 2V C1 þ 3V Coxp > Finv ð1:45VÞ: C1 þ Coxn þ Coxp þ Cp and for the quaternary input 3 (3V), 3V C1 þ 3V Coxp > Finv ð1:45VÞ: C1 þ Coxn þ Coxp þ Cp
ð9Þ
ð10Þ
ð11Þ
Since the transistor switches so fast, Cox can be considered to be constant [13]. For W =L ¼ 16:0mm=1:6mm; Cox is given by 16:0mm 1:6mm 3:9 8:854F=cm Cox ¼ E30fF: ð12Þ 300 108 cm Taking layout constraints into consideration for 1:5mm CMOS technology, a unit capacitance of 500fF is considered. Hence the input capacitors to the circuit need to be an integer multiple of 500fF. From layout extraction, a unit capacitance of 500fF gives 40fF of parasitic capacitance
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ðCp1 Þ: Cp can be then computed as follows: Cp ¼
40fF C1 : 500fF
ð13Þ
Substituting the values of Coxn (30fF), Coxp (30fF) and Cp using Eqs. (12) and (13) in Eqs. (8)– (11), value of C1 is obtained. The smallest value of C1 that satisfies the above inequalities is 500fF. Substituting the value of C1 in Eq. (13), the value of Cp is 40fF. The output of MIFG inverter needs to be inverted to get final output as shown in the Table 1. Hence a CMOS inverter #2 is introduced at the output of MIFG inverter, which inverts the output as well as buffers, the signal generated by MIFG inverter. From Table 1, the LSB bit is LOW (0V) for logic inputs 0 (0V) and 2 (2V) and is HIGH (3V) for inputs 1 (1V) and 3 (3V). Fig. 8 shows FPD for the LSB. In Fig. 8, the potential on the floating gate is below the switching threshold line for inputs 0 (0V) and 2 (2V) and above the switching threshold line for inputs 1 (1V) and 3 (3V). We also observe that the voltage on floating gate falls below threshold line for input 2 (2V). The slope of the line can be adjusted to obtain an operating range of Finv for reliable circuit operation. The corresponding circuit diagram is shown in Fig. 9. A pre-input gate inverter stage (#3) is required to control the voltage on floating gate, such that the output of the pre-input inverter stage goes LOW (0V) for inputs 2 (2V) and 3 (3V). The capacitors C2 and C3 are the input capacitors for the MIFG inverter. Capacitor C3 is controlled by quaternary input and capacitor C2 is controlled by output of pre-input gate inverter stage. The voltage on the floating gate of MIFG inverter is given by FF ¼
VIN C3 þ V1 C2 þ 3V Coxp : C2 þ C3 þ Coxn þ Coxp þ Cp
ð14Þ
γVDD
ΦF,V
Φinv
0(0V)
1.45V
1(1V)
2(2V)
3(3V)
Vin,V Fig. 8. FPD for the conversion of quaternary to LSB output.
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VDD
C4 500fF
C2 500fF W/L= 16.0µm/ 1.6µm
#4
#3 VIN
W/L= 16.0µm/1.6µm #5 LS B
C3 1000fF W/L= 16.0µm/ 1.6µm
W/L= 16.0µm/1.6µm
CL 0.1pF
VSS
Fig. 9. Circuit diagram for implementation of quaternary logic to binary logic—LSB using floating gate MOSFETs.
Inequalities for four quaternary inputs can be obtained from Eq. (14). For the quaternary input 0 (0V), 0V C3 þ 3V C2 þ 3V Coxp oFinv ð1:45VÞ: C2 þ C3 þ Coxp þ Coxn þ Cp
ð15Þ
For the quaternary input 1 (1V), 1V C3 þ 3V C2 þ 3V Coxp > Finv ð1:45VÞ: C2 þ C3 þ Coxp þ Coxn þ Cp
ð16Þ
For the quaternary input 2 (2V), 2V C3 þ 0V C2 þ 3V Coxp oFinv ð1:45VÞ: C2 þ C3 þ Coxp þ Coxn þ Cp
ð17Þ
For the quaternary input 3 (3V), 3V C3 þ 0V C2 þ 3V Coxp > Finv ð1:45VÞ: C2 þ C3 þ Coxp þ Coxn þ Cp
ð18Þ
A unit capacitance of 500fF gives 40fF of parasitic capacitance ðCp1 Þ: The value of Cp is given by Cp ¼
40fF ðC2 þ C3 Þ : 500fF
ð19Þ
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C2 and C3 are obtained by substituting value of Coxn (30fF), Coxp (30fF) and Cp from Eqs. (12) and (19) in Eqs. (15)–(18). The above inequalities are satisfied when the capacitance of C3 is greater than the capacitance of C2 : Capacitors C2 and C3 are found to be 500fF and 1000fF, which satisfy the above inequalities. Substituting the value of C2 and C3 in Eq. (19), the value of Cp is 120fF. The pre-input inverter stage controlling the capacitor C2 is to be designed such that the output of the inverter stage is HIGH (3V) for inputs 0 (0V) and 1 (1V) and is LOW (0V) for inputs 2 (2V) and 3 (3V). Using Eq. (7), the inequalities are found, for quaternary input 0 (0V), 0V C4 þ 3V Coxp oFinv ð1:45VÞ: C4 þ Coxn þ Coxp þ Cp
ð20Þ
For the quaternary input 1 (1V) 1V C4 þ 3V Coxp oFinv ð1:45VÞ: C4 þ Coxn þ Coxp þ Cp
ð21Þ
For the quaternary input 2 (2V) 2V C4 þ 3V Coxp > Finv ð1:45VÞ: C4 þ Coxn þ Coxp þ Cp For the quaternary input 3 (3V) 3V C4 þ 3V Coxp > Finv ð1:45VÞ: C4 þ Coxn þ Coxp þ Cp
ð22Þ
The value of Cp is given by Cp ¼
40fF C4 : 500fF
ð23Þ
The above inequalities are satisfied when the capacitance of C4 X500fF: The pre-input inverter stage (#3) for the LSB bit is observed to be same as the MIFG inverter (#1) in MSB bit circuit. Hence the output of MIFG inverter of MSB bit can be used to control the capacitor C2 instead of a pre-input inverter stage. Fig. 10 shows the full circuit level implementation of quaternary input into binary bit conversion, which is obtained from Figs. 7 and 9. In Fig. 10, the capacitors are in an integer multiple of 500fF unit size capacitors in AMI 1:5mm n-well CMOS process. The inverter switching threshold voltage ðFinv Þ is 1:45V: The physical design of the circuit is simulated with SPICE using MOSIS BSIM3 model parameters. An output capacitive load of 0.1pF has been included in simulation. A piece-wise linear voltage source with 0:1ns rise time and fall time with 40ns pulse width is given at input of the circuit. Fig. 11 shows the MSB and LSB outputs. The propagation delay is measured from the time where the input reaches 50% of its maximum value to the time where the output reaches 50% of its maximum value. Table 2 summarizes the propagation delays obtained by setting initial conditions of the floating gate voltages to zero. The maximum tpLH ¼ 6ns for input transitions from logic 2ð2VÞ-logic 1ð1VÞ and tpHL ¼ 5ns for input transition from logic 1ð1VÞ-logic 2ð2VÞ are measured from simulations.
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VDD
C1 500fF
#2
#1
MSB CL 0.1pF
VSS VDD Vin C2 500fF #4
#5 LSB CL 0.1pF
C3 1000fF
VSS
Fig. 10. Full circuit diagram for conversion of quaternary (4-valued) logic to binary bits using floating gate MOSFETs.
4. Experimental results Fig. 12 shows the photograph of a fabricated chip by AMI 1:5mm standard CMOS process. Fig. 13 shows the oscilloscope photograph of quaternary input, MSB and LSB outputs. A reduced inverter switching threshold voltage value of 1.15V was measured from the voltage transfer characteristics on five fabricated chips with voltage variation less than 50mV: The observed reduced shift in inverter switching threshold voltage from 1.45–1:15V is due to variation in process-dependent MOS model parameters. The circuit of Fig. 10 was re-simulated from the BSIM3 models parameters of the fabricated chip. The fabricated chip was tested for the input voltage varying in steps from 0 to 3V. Table 3 summarizes the designed and measured quaternary inputs and output bit voltage values. From measured and designed data obtained from simulation, we observe that the maximum measured voltage that results in output corresponding to logic 2 is 1.6V rather than designed 2V: With 1.6V as logic 2, the design was re-simulated for all possible transitions in the input to measure propagation delays. A piece-wise linear input voltage with 5ns rise time and fall time was applied at the input. A 15pF load capacitance was added at the output as probe capacitance. Simulated and measured propagation delays are summarized in Table 4. The conversion circuit shown in Fig. 10 has a total of eight transistors, four MIFG transistors and four CMOS transistors. An approximate of 75% reduction in transistor count is obtained, when compared to previous circuits found in literature [4,6,8], which corresponds to
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Quat-In, V
3 2 1 0
MSB, V
3 2 1 0
LSB, V
3 2 1 0 0.00E+00
1.00E-07
2.00E-07
3.00E-07
4.00E-07
5.00E-07
t, s
Fig. 11. Simulated MSB and LSB output response of the circuit of Fig. 10 for all Possible combinations of the quaternary input. Table 2 Simulated values of propagation delays for the physical design of circuit of Fig. 10 for 0.1pF load capacitance Logic level transition (quaternary logic)
MSB tpd (ns)
LSB tpd (ns)
0-1 1-2 2-3 3-2 2-1 1-0 0-2 2-0 0-3 3-0 1-3 3-1
— 1.92 — — 1.52 — 2.03 1.14 1.51 1.22 1.43 1.63
3.46 4.97 1.19 2.10 6.02 1.02 — — 0.70 0.85 — —
Note: A dash (—) indicates that the data could not be obtained.
significant area reduction though 0.5 and 1pF capacitors are used in design. It is worth mentioning that design can also be implemented using reduced capacitors, which are limited in size due to parasitic capacitance.
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Fig. 12. Chip photograph of a quaternary to binary bits conversion device.
QUAT-IN, V
MSB, V
LSB, V
T, µS
Fig. 13. Oscilloscope photograph of a quaternary input, MSB and LSB outputs. (Horizontal axis: 0:22mS=DIV; Vertical axis: 2V/DIV.)
5. Conclusion A simple conversion scheme from quaternary to binary bit is presented in a standard CMOS process using multiple-input floating gate MOSFETS. The designed circuit was fabricated in AMI 1:5mm n-well CMOS process and was tested for performance. All quaternary logic levels agree with the corresponding binary bits except the logic 2 (2V), which was measured at 1.6V for logic 2 due to possible process variations. The circuit can be easily embedded in digital CMOS design
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Table 3 Designed and measured quaternary input and binary output bit voltage values Quaternary input-design value (V) 0.0 1.0 2.0 3.0
Quaternary input measured value (V) 0.0 1.0 1.6 3.0
MSB
LSB
Simulated (V)
Measured (V)
Simulated (V)
Measured (V)
0.0 0.01 3.0 3.0
0.0 0.01 3.0 3.0
0.0 3.0 0.09 3.0
0.0 3.0 0.0 3.0
Table 4 Measured and simulated propagation delays Logic level transition quaternary logic 0-1 1-2 2-3 3-2 2-1 1-0 0-2 2-0 0-3 3-0 1-3 3-1
MSB
LSB
Simulated tpd (ns)
Measured tpd (ns)
Simulated tpd (ns)
Measured tpd (ns)
— 11 — — 11 — 12 8 11 8 11 10
— 12 — — 12 — 14 9 12 10 12 11
11 13 9 12 17 10 — — 8 7 — —
13 — 10 15 20 11 — — 9 9 — —
Note: A dash (—) indicates that the data could not be obtained.
architectures and used in a sensor readout electronics for transmission of data with reduced bandwidth requirements over a long distance [14]. The circuit could be also integrated with the front-end sensor readout circuit for direct conversion of quaternary-level voltages into corresponding binary-level voltages. The method can also be applied for ternary to binary bit conversion CMOS integrated circuit design [15]. Such conversion designs have useful application to process a larger set of signals in a relatively small area which otherwise would occupy a large space in a binary design due to interconnections.
References [1] J.T. Butler, Multiple-Valued Logic in VLSI, IEEE Computer Society Press Technology Series, Los Alamitos, CA, 1991. [2] S.L. Hurst, Two decades of multiple-valued logic—an invited tutorial, Proc. IEEE International Symposium on Multiple-Valued Logic, May 1998, p. 164.
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Ashok Srivastava received B.Sc., B.Sc. (Hons.) and M.Sc. (Physics-Advanced Electronics) degrees from the University of Lucknow, India, in 1968, 1969, and 1970, respectively. He obtained M. Tech. and Ph.D. degrees in Solid State Physics and Semiconductor Electronics area from Indian Institute of Technology, Delhi in 1970 and 1975, respectively. Currently, he is an Associate Professor of Electrical and Computer Engineering at Louisiana State University in Baton Rouge. During a 2001 sabbatical, he has worked at the Philips Research Laboratory, Eindhoven, Netherlands in RF passive integrated circuits design for implementation in MEMS technology for mobile communications. He has previously served as a Scientist at the Central Electronics Engineering Research Institute, Pilani, India, and was on the faculty in EEE Department of Birla Institute of Technology and Science, Pilani, India; Department of Electrical and Computer Engineering of North Carolina State University, Raleigh; State University of New York, New Paltz; University of Cincinnati, Cincinnati and as a UNESCO Fellow; as a Visiting Scientist and UNESCO Fellow at the University of Arizona, Tucson. He is the author of about 70 technical papers, including conference proceedings and book chapter in areas of integrated circuits covering CMOS, Bipolar, BiCMOS, SOI-CMOS and GaAs technologies. His current research interests include low-power digital, analog/mixed-signal CMOS VLSI circuit design; CMOS-MEMS microsystem integration and smart sensors; RF MEMS and integrated circuits; semiconductor device modeling; radiation-hardened integrated circuits; and low-temperature electronics. He is a senior member of IEEE, Electron Devices, Circuits and Systems, and Solid-State Circuits Societies, and member of SPIE, and Cryogenic Society of America. Harish N. Venkata was born in Hyderabad, India on 30 November 1977. He has received his B.S. in Electronics and Communication Engineering from Sri Venkateswara University, Tirupati in 1999, and M.S. in Electrical Engineering from Louisiana State University in 2002. His research interests include multiple-valued logic VLSI design, floating gate devices and capacitor-based architectures. He is currently working as a design engineer at Micron Technology Inc., Texas.