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CMOS low power split-drain MAGFET based magnetic field strength sensor
Microelectronics Journal 100 (2020) 104759
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
CMOS low power split-drain MAGFET based magnetic field strength sensor Shuk-Fun Lai a , Wing-Shan Tam b, ∗ , Chi-Wah Kok b , Hei Wong a a b
Department of Electronic Engineering, City University of Hong Kong, Hong Kong, China Canaan Semiconductor Limited, Hong Kong, China
A R T I C L E
I N F O
Keywords: MAGFET Magnetic sensor Time-to-digital conversion
A B S T R A C T
A low-power sectorial split-drain MAGFET (SSD-MAGFET) based magnetic field strength sensor consists of a simple counter-based time-to-digital converter was proposed, which converts the magnetic field strength into a digital value by observing the relative drain voltage difference in the SSD-MAGFET, thus eliminating the adverse effect of device and circuit noises without the need of sophisticated operational amplifier nor precise voltage reference. Complete digital readout of the magnetic field strength, field polarity and conversion time information facilitates the seamless integration of the proposed circuit to read-time application. The proposed circuit is fully compatible with standard CMOS process and the presented design example was implemented on 2.5 𝜇 m metal gate CMOS process which achieves conversion accuracy is of 1.226 mT/bit for the field range of a maximum dynamic range of ±313.96 mT, and the minimum conversion rate is 17.6 Hz where the whole chip consumes an average of 67.5 mW at supply voltage of 5 V, which is suitable for seamless integration with all sorts of MCU applications.
1. Introduction With technology advancement in future vehicles and the development of Internet of Things (IoT) technology, there is increasing demand in magnetic sensors for applications, such as motor driving, motion detection, current measurement, biomedical sensing, etc. Lots of researches have been devoted to improve the sensitivity and stability of the magnetic sensors by exploiting their geometry, structures and materials applied to construct the sensors [1–3]. Besides, a variety of circuit techniques are developed to suppress sensor and circuit noises [4–6]. Moreover, with the new demand in IoT application, the readout of the magnetic sensor is migrating from analog to digital, such as to facilitate the integration of the sensors with external micro-processing units, or further fulfilling the real-time readout application [7–9]. Among a variety of solid-state magnetic sensing devices, split-drain magnetic fieldeffect transistor (SD-MAGFET) is a prominent device for monolithic magnetic sensor because it can be fully integrated into standard CMOS process. Moreover, SD-MAGFET consumes less power when compared to the conventional Hall plate devices, and in particular, the sectorial SD-MAGFET (SSD-MAGFET) is regarded to be able to achieve better magnetic sensitivity than other type of SD-MAGFETs in the same silicon area [10,11]. When the drains of the SD-MAGFET are connected to two current sources, the difference voltage between the two drains will
be proportional to the magnetic field strength applied to the channel of the SD-MAGFET, where the difference voltage is also known as the Hall voltage, which can be easily digitized, or converted into differential current. Nonetheless, SSD-MAGFET has the same drawback as that of Hall plate where it suffers from sensing noise and device offset problems, which are process or layout dependent, or are generated in the course of sampling by the subsequent conversion circuits. Both sensing noise and circuit noise are error sources that hamper the linearity and accuracy of the magnetic sensor. With the SSD-MAGFET as the core magnetic field sensing element of the proposed circuit, its noise characteristic has the crucial effect on the overall noise performance of the proposed circuit. The SSD-MAGFET is low frequency 1/f dominated [12,13] which can be effectively suppressed by common correlation double sampling (CDS) or related noise canceling techniques widely adopted in sensor applications. CDS is a simple circuit technique applied to deal with sampling noise and device offset with the aid of sample-and-hold circuits [14], at the cost of complicated circuitry and high power consumption. To avoid using sampleand-hold circuit, the cross-coupled sensing elements with signal conditional circuit was proposed. However, the efficiency of the circuit is low because of the extra power required to drive multiple sensing elements. Furthermore, the noise and offset of the resulting circuit is highly dependent on the performance of the operational amplifier [6] which
∗ Corresponding author. E-mail address: [email protected] (W.-S. Tam). https://doi.org/10.1016/j.mejo.2020.104759 Received 29 April 2019; Received in revised form 17 February 2020; Accepted 16 March 2020 Available online 3 April 2020 0026-2692/© 2020 Elsevier Ltd. All rights reserved.
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Microelectronics Journal 100 (2020) 104759
in turn increased the required complexity of the overall sensing circuit. Current spinning technique can be applied to sensing devices to produce differential current proportional to the magnetic field strength, which can be applied to cancel the error aroused from the offset of the sensing device [4,5]. However, the use of chopper stabilized current integrator is indispensable in current spinning technique, which requires careful design of low-pass filter to eliminate the effect of the chopper frequency at the output. To overcome the requirement of high complexity analog circuitry, the noise and offset cancellation can be rendered in the digital domain by applying simple analog-to-digital front-end to convert the analog output of the sensing element into a digital value [7,8,15,16]. Therefore, our proposed circuit proposed to convert the magnetic field strength into time signal by integrating the relative difference of the induced drain voltages of the SSD-MAGFET, such that the noise on the SSD-MAGFET can be effectively suppressed similar to the noise cancellation approach presented in literature [9]. A complete digital conversion front-end by self comparing and integrating the time delay between the sensed signal and its delayed version has been proposed in Ref. [9], which achieves ultra-low power implementation and it does not require the use of internal reference circuit. Ref. [17] also proposed a time-to-digital converter which converts the magnetic field strength sensed by the magnetic-impedance (MI) sensor consists of a pick-up coil and an amorphous wire. The MI sensor is driven by an alternative pulse to pick up the magnetic field in longitudinal direction of the wire. The output of the MI sensor is treated as the supply voltage to the inverter-based delay line on the FPGA, known as ring delay line (RDL), where its output is coupled to a fixed counter. The pulse width of the output of the RDL is integrated by the counter-based time-toanalog converter, where the output of the fixed counter is the digitized value of the sensed magnetic field strength. It should be noted that the delay time of the output of RDL is linearly proportional to the sensed magnetic field strength, thus the counter output value. The circuit presented in Ref. [17] is efficient in reducing the component count and achieves high resolution, but the MI sensor cannot be integrated with the controller circuit. In Ref. [18], a modified time integrator dedicated in converting the difference voltage of the SSD-MAGFET into a pulsewidth-modulated (PWM) signal was proposed, where the SSD-MAGFET is biased with simple resistors without the need of complicated driving circuits. In this paper, a SSD-MAGFET based magnetic sensor that adopts a similar time integrator approach is proposed. The integrator is incorporated with a counter-based time-to-digital converter, which achieves simple conversion to the SSD-MAGFET readout without complicated circuitry. Moreover, conversion cycle of the counter-based converter is self-adjusted according to the signal to be converted, such that the conversion efficiency can be improved. In the meantime, a digital readout for the field strength, the field polarity and the rate of change of field strength is readily available, which provides the essential information for real-time processing without stringent need of external signal processing unit. The proposed circuit is simple and CMOS compatible including the sensing elements, which makes the proposed circuit suitable for battery-powered IoT application.
Fig. 1. Schematic of the proposed sensor determining the rate of change of magnetic field.
age of the SSD-MAGFET is proportional to the magnetic field strength B acting on the device [10], such that V1 − V2 = KB,
(1)
where K is the conversion gain of the SSD-MAGFET, and the sign of B is the polarity of the applied magnetic field, where positive sign and negative sign refer to the north and south poles respectively. Initially (t = t0 ), the capacitor C is empty and hence VC = GND. Therefore, the outputs of the comparators A1 and A2 will be equal to O1 = O2 = VDD , thus the output of NAND1 equals GND which biases transistor M2 to cutoff. As a result, the capacitor C is being charged up by the current source IC , and at time t0 , the capacitor voltage VC is given by V C (t ) =
IC t . C
(2)
Without loss of generality, assume the magnetic field B is of south pole, which will induce V1 > V2 . As long as VC (t) < V2 , the output of the two comparator will be O1 = O2 = VDD . At time t1 , C has been charged with t1 − t0 seconds to achieve VC (t1 − t0 ) = V2 , the comparator output O2 = GND, which will toggle the NAND1 output to VDD , and turn M2 on. This will alter the charging current to C from IC to IC − ID . At the same time, the output of EXOR1 changes from GND to VDD , which allows the clock signal OSC1 with frequency f to pass through AND2 to clock into COUNTER1. The value of O1 is clocked into the D-flipflop (DF1) at the same time, which indicates the polarity of the field strength. The COUNTER1 will store the number of clock cycles up to the time when VC is high enough to turn both O1 and O2 to GND. This happens on t = t2 and is given by
2. Proposed circuit Showing in Fig. 1 is the schematic of the proposed circuit, which consists of a SSD-MAGFET, two comparators (A1 and A2 ), two current sources (ID and IC ) and a number of digital gates, which serves as a digital integrator to convert the Hall voltage (V1 − V2 ) into a digital value. The SSD-MAGFET is biased into saturation mode by adjusting its gate voltage at Vb to promote the linearity in converting the magnetic field strength into the differential drain voltages of the SSD-MAGFET [10]. The two resistors R1 and R2 are connected to the two drains of the SSD-MAGFET, where the values of R1 and R2 are chosen (through trimming in actual implementation) to equalize the two drain voltages (i.e. V1 and V2 ) when there is no magnetic field applied, such that the offset in the SSD-MAGFET can be mitigated. The differential drain volt-
t2 =
C (V 1 − V 2 ) + t1 . IC − ID
(3)
At the same time, the output of NOR1 will turn to VDD from GND, and trigger the one-shot device to generate a pulse with duration TS second at O3 , where TS is the reset time. The time duration TS is set to be long enough to turn M1 on to discharge C and bring VC to GND and the circuit is reset to the initial state (t = t0 ) with an empty C and both O1 and O2 at VDD . Besides resetting the circuit, the O3 pulse will also help to latch the values in COUNTER1 and COUNTER2 into LATCH1 and LATCH2, 2
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Microelectronics Journal 100 (2020) 104759
respectively. Let’s denote N1 and N2 as the count numbers latched in LATCH1 and LATCH2, respectively. The conversion period (tp ) can be obtained from N1 as tp = t2 − t1 = ⇒ N1 =
N1 C = (V − V 2 ) f IC − ID 1
fC(V1 − V2 ) fCKB = . IC − ID IC − ID
(4) (5)
It should be noted that N1 is linearly proportional to B. The output of DF1 will also be latched to the most significant bit (MSB) of the LATCH1, which is the value of O1 at t1 . O1 will be VDD when B is of south pole, and will be GND when B is of north pole. The N2 is the number of clocks in between two consecutive O3 pulses, i.e. the time between two initial states/conversion cycles denoted by tmax = t2 − t0 + TS , and is given by N2 = f tmax .
Fig. 2. Measured difference drain voltages (V1 − V2 ) of the SSD-MAGFET in the field range of −300 mT–300 mT.
(6)
It should be noted that the output of NOT1 is an inverted O3 , which resets the counters when O3 =VDD . Consider two consecutive conversion cycles, the (𝓁 + 1)th and the 𝓁th cycles, where the difference of the corresponding values in LATCH1 is given by
ΔN1 = N1,𝓁 +1 − N1,𝓁 ,
Table 1 Summary of the performance of the proposed circuit.
(7)
with N1,𝓁 +1 being the value of LATCH1 of the (𝓁 + 1)th cycle and N1,𝓁 being the value of LATCH1 of the 𝓁th cycle. Similarly, the difference of the corresponding values in LATCH2 at the (𝓁 + 1)th and the 𝓁th cycles can be computed as
ΔN2 = N2,𝓁 +1 − N2,𝓁 ,
(8)
where N2,𝓁 +1 is the value of LATCH2 at the (𝓁 + 1)th cycle and N2,𝓁 is the value of LATCH2 at the 𝓁th cycle. Hence, the rate of change of magnetic field strength can be computed as BR =
B𝓁 +1 − B𝓁 ΔN1 (IC − ID ) ΔN1 = ∝ , tmax,𝓁 +1 − tmax,𝓁 ΔN2 CK ΔN2
|I − I | Bmax = || C D || . 2nob1 | fCK |
2.5 𝜇 m Metal Gate CMOS Process 18 kHz 9-bit (MSB: polarity of field strength) 10-bit 17.6 Hz 5V ±313.96 mT 1.226 mT/bit 67.5 mW
in order to speed up the charging of C to bring VC to the appropriate voltage for the conversion of the difference voltage without sacrificing Bres . A greater IC could reduce t1 − t0 , thus shorten tmax . Nonetheless, greater IC would increase the current consumption of the circuit.
3. Experiment The SSD-MAGFET was fabricated in 2.5 𝜇m metal gate CMOS process. All circuit blocks in the proposed circuit, including the SSDMAGFET, the current sources, the comparators and logic circuits are fabricated. A beta-multiplier reference circuit [15] was implemented to generate a reference current, and it is further scaled to IC and ID through current mirrors. The comparators were implemented by a simple unbuffered two-stage operational amplifier with an N-channel input pair [19]. To achieve higher sensitivity, the SSD-MAGFET was biased in saturation mode by applying Vb = 1.4 V with VDD = 5 V, R1 = R2 = 56 kΩ (before trimming is being applied to equalize the difference voltage between V1 and V2 ). Fig. 2 shows the plot of the measured difference voltage (V1 − V2 ) as a function of magnetic field strength from −300 mT to 300 mT measured by ATTEN oscilloscope ADS 1062CAL, where the magnetic field is generated by permanent magnets with field strength measured by AlphaLab Gaussmeter GM2. It can be observed that the SSD-MAGFET converts the magnetic field strength into difference voltage linearly with the conversion gain given by the slope of the plot in Fig. 2, i.e. K = −302 mV/T. With f = 18 kHz, C = 150 nF, IC = 180 𝜇 A, ID = 179 𝜇 A, nob1 = 9-bit (1 polarity bit plus 8 data bits) and nob2 = 10-bit, it was found that Bmax = 313.96 mT and Bres = 1.226 mT/bit as depicted in Eq. (10) and Eq. (11), respectively. The performance of the implemented circuit is summarized in Table 1.
(10)
where nob1 is the bit length of COUNTER1. It should be noted that to achieve accurate conversion, tmax > tp + TS , such that nob2 has to be greater than nob1 to make the circuit practical. The resolution of the proposed circuit (Bres ) is determined by the magnetic field strength that can be represented by one bit of data in COUNTER1, and is given by Bres =
Values
Technology Oscillating Frequency f Readout Resolution for N1 Readout Resolution for N2 Minimum Conversion Rate f∕(2nob2 ) Power Supply, VDD Dynamic Range, Bmax Resolution, Bres Power Dissipation
(9)
where B𝓁 +1 and B𝓁 are the magnetic field strength sensed by the sensor at the (𝓁 + 1)th and the 𝓁th cycles, respectively, and tmax,𝓁 +1 and tmax,𝓁 are the conversion period for the (𝓁 + 1)th and the 𝓁th cycles, respectively. To complete the conversion, the number of bits of COUNTER2 (nob2) has to be long enough to accommodate tmax , which is given by nob2 > log2 ⌈tmax · f ⌉. For a particular nob2 and f, the minimum conversion rate of the proposed circuit is given by f∕2nob2 . It should be noted that the conversion rate of the proposed circuit is not a constant as the conversion cycle is determined to be complete and reset to initial state once VC reaches V1 or V2 , whichever is the higher value. The maximum magnitude of the magnetic field strength (Bmax ) that can be readout from each conversion is equivalent to the maximum V1 − V2 that can be resolved for a particular values of IC , ID , f, C, nob1 and K, and is given by | 2nob1 (I − I ) | | C D | Bmax = | |, | | fCK | |
Parameters
(11)
It should be noted that the charging current to capacitor C is reduced from IC to IC − ID from the period of t1 − t0 to t2 − t1 , respectively, 3
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4. Results and discussions
circuit. Therefore, it results in a design dilemma in the proposed circuit, where the appropriate Bmax and Bres would be application dependent. To better understand the operation of the proposed circuit, the timing diagram of the gate voltage applied to the transistor M1 (VM1,g ) and the ramp voltage (VC ) subject to a magnetic field strength of −200 mT is illustrated in Fig. 3. Consider t0 = 0, the circuit is initialized to bring VC = 0 V and enable the COUNTER2 to start counting the clocks generated by OSC1. The current IC charge the capacitor C and VC is increased linearly. When VC = V2 is reached (i.e. t = t1 and t1 − t0 = T1 = 1 ms), O2 will switch from VDD to GND, thus the output of NAND1 becomes VDD which turns M2 on. Since only one of the inputs of EXOR1 is in VDD (O1 in this case), the output of EXOR1 will switch from GND to VDD to clock in the O1 value to the DF1 and operate with AND2 to enable COUNTER1 to count the clocks generated by OSC1. The charging current will be reduced to IC − ID once M2 is turned on. In the meantime, COUNTER1 is triggered to count the clocks generated by OSC1. The reduced IC − ID continues to charge the capacitor C until VC = V1 is reached (i.e. t = t2 and tp = t2 − t1 = T2 = 9 ms), O2 will be turned to VDD from GND, which triggers the one-shot reset signal O3 with pulse width of TS . In the implemented circuit, TS was set at 1 ms. During TS , O3 is in VDD , the values in COUNTER1 and COUNTER2 are latched into LATCH1 and LATCH2, respectively. The value in DF1 is also latched into the MSB of LATCH1 at the same time. Both COUNTER1 and COUNTER2 are reset once the latching is complete. The digital output presented by LATCH1 and LATCH2 are N1 (i.e. tp ) and N2 (i.e. tmax ), respectively. The tp and tmax were measured to be 9 ms and 11 ms, respectively. When O3 =VDD , M1 will be turned on to discharge capacitor C to bring VC back to 0 V (the circuit is reset to initial state). It should be noted that in the implemented circuit, O1 is VDD when VC = V2 , therefore, the MSB of LATCH1 value will be in logic high, which indicates the magnetic field is in south pole. When a magnetic field in north pole is applied, V2 > V1 , such that O1 will be in GND at t = t1 and the value in the MSB of LATCH1 will be in logic low. As the MSB of LATCH1 is reserved for carrying the polarity information, a 9-bit LATCH1 was chosen. With the design requirement that nob2 > nob1, a 10-bit COUNTER2 and LATCH2 were chosen. Hence, the minimum conversion rate is f∕2nob2 = 17.6 Hz and the dynamic range is ±313.9 mT, which is suitable for magnetic sensors used in human interface system, such as rotating knobs, where the angle of rotation can be readout by having the human turning a polarized magnet on top of the SSD-MAGFET sensor. For applications that need higher operating frequency, the clock rate f could be increased and the maximum clock rate is process dependent, where the maximum f that can be achieved by the adopted 2.5 𝜇m metal gate process is up to 800 kHz. Furthermore, it should be noted that when f is increased by n-times, the value of C should be reduced by n-times such that total power consumption and conversion accuracy would not be altered disregarding the operating frequency of the circuit and the conversion time of the circuit. Compared the proposed circuit with that in Ref. [17], instead of varying the delay time of the ring oscillator, the time integration is achieved by converting the time for charging and discharging the capacitor C, with its voltage compared to the sensed voltage of the SSDMAGFET, where the linearity in charging up of a voltage on a capacitor is easily maintained through simple constant current source, while it is difficult to build a ring oscillator with oscillating frequency linearly related to the supply voltage. Therefore, the conversion linearity of the proposed circuit is more easily maintained when compared to that of the circuit reported in Ref. [17]. The 1/f noise spectral density of CMOS split-drain MAGFET is in the level of hundred nT/Hz [13] where the noise components of sensors in the proposed circuit is approximately 0.02 mT with internal clock set as 18 kHz. The noise level for the sensing element is lower than the resolution of the proposed circuit at 1.226 mT/bit, which confirms the noise effect of the sensing element is not significant.
The proposed circuit has a number of advantages when compared to traditional magnetic sensors [1,9,16], in which the proposed circuit does not only provide direct readout of the sensed magnetic field strength and field polarity, it also provides a means to generate the rate of change of magnetic field information directly from two consecutive sensing cycles without the need of an accurate time reference, and complicated sample-and-hold system. Since (V1 − V2 ) is retrieved by measuring V1 and V2 independently, and they are compared with the same voltage VC in complimentary manner with both V1 and V2 connected to the positive terminals of A1 and A2 , respectively, such that the input offset voltage imposed by the comparators will be mitigated. Due to layout mismatch between the two drains of the SSD-MAGFET, it’s drain voltages V1 and V2 have offset even when there is no magnetic field applied to the system (see Fig. 2). We propose to mitigate this problem by trimming the resistance of the resistors R1 and R2 that provides the current to the SSD-MAGFET. As a result, the magnetic field strength applied on the SSD-MAGFET can be extracted by comparing V1 and V2 to a common voltage VC , and generating the corresponding digital outputs O1 and O2 , which allow the conversion of the analog difference voltage (V1 − V2 ) into time information by counting the time difference between both O1 and O2 reaching VDD using the counter-based converter. Since errors appear on both drains will be canceled out with the detection being achieved by converting the difference voltage, no additional noise removal circuit is required. Furthermore, the conversion of the time difference between both O1 and O2 is continuous until both of them reaching VDD , such that the proposed circuit does not require the use of sample-and-hold circuits, which is simple when compared to traditional Hall sensor based system. Moreover, the proposed circuit does not require the use of sophisticated high gain amplifier to amplify the small Hall voltage [5,20], which avoids the amplification of input offset and noise aroused by the amplifiers simultaneously, thus improving the reliability and system vulnerability. In the proposed work, A1 and A2 can be implemented by simple single stage differential pair, which achieves low power operation and is fully compatible with CMOS implementation. It should be noted that even when a fixed resistance R1 and R2 are being applied without trimming to eliminate the offset of the SSD-MAGFET, the non-zero readout can be pre-stored and be used to rectify the initial offset problem during later data manipulation. It should be further noted that, the choice of R1 and R2 would affect the voltages of V1 and V2 , respectively, which would affect the duration of t1 − t0 which will be increased by greater values of V1 or V2 . As depicted by Eq. (11), the Bres can be improved (by reducing its magnitude) by reducing IC − ID , increasing C, increasing f or increasing K. Increasing the conversion gain of the SSD-MAGFET K will increase its size or fabricate it in non-CMOS compatible process, and is therefore considered to be non-favorable. Increasing f will require to use CMOS process with higher operating frequency, which will increase the fabrication cost, and power consumption. Reducing IC − ID can improve the resolution and at the same time reduce the power consumption of the circuit. Noted that with IC > > IC − ID , the conversion time (t2 − t1 ) > > (t1 − t0 ), and therefore, reducing IC − ID will increase tp , and hence the tmax . In other words, the application of a large IC helps to mitigate the long conversion time problem in traditional time-to-digital converter because of the initial drain voltage of the SSD-MAGFET under no magnetic field. Increasing C is simple, but that will elongate the tp , and increase the power consumption, since whatever charged to C will be discharged in the next conversion cycle. However, increasing C is the most easy way to allow user to adjust the conversion accuracy, which can be altered through off-chip adjustment. The Bmax and Bres have counter effects on the performance of the circuit. The smaller the Bres , the finer the step size of COUNTER1, whereas the larger the Bmax , the greater the field strength that can be detected by the
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Resources. C.W. Kok: Conceptualization, Methodology, Writing – Original draft preparation, review & editing. H. Wong – Supervision, Resources, Writing – review. Declaration of interests The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. References [1] H. Blanchard, M.F. De, B.J. Hu, R.S. Popovic, Highly sensitive Hall sensor in CMOS technology, Ses. Actuat. 82 (2000) 144–148. [2] R.S. Popovic, Z. Randjelovic, D. Manic, Integrated Hall-effect magnetic sensors, Sensor. Actuator. 91 (2001) 46–50. [3] Y. Nishitani, M. Endo, F. Matsukura, H. Ohno, Magnetic anisotropy in a ferromagnetic (Ga,Mn)Sb thin film, Phys. E Low-dimens. Syst. Nanostruct. 42 (10) (2010) 2681–2684. [4] H. Huang, D. Wang, X. Yue, A monolithic CMOS magnetic Hall sensor with high sensitivity and linearity characteristics, Sensors 15 (10) (Oct. 2015) 27359–27373. [5] H. Heidari, E. Bonizzoni, U. Gatti, F. Maloberti, A CMOS current-mode magnetic Hall sensor with integrated front-end, IEEE Trans. Circ. Syst. I: Reg. Pap. 62 (5) (Apr. 2015) 1270–1278. [6] Y. Xu, H.B. Pan, S.Z. He, L. Li, A highly sensitive CMOS digital Hall Sensor for low magnetic field applications, Sesnors 12 (2) (Feb. 2012) 2162–2174. [7] S.L. Chen, C.H. Kuo, S.I. Liu, CMOS mangietc field to frequency converter, IEEE Sens. J. 3 (2) (Apr. 2013) 241–245. [8] C. Azcona, B. Calvo, S. Celma, N. Medrano, P.A. Martinez, Ratiometric voltage-to-frequency converter for long-life autonomous portable equipment, IEEE Sens. J. 13 (6) (Jun. 2013) 2382–2390. [9] A. Yelkenci, O.Z. Batur, B. Sarioglu, Ultra low power all-digital CMOS sensor read out circuit for optically powered biomedical systems, in: Proc of the 9th Int Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI), Oct. 2016. [10] Z.Y. Yang, S.L. Siu, W.S. Tam, C.W. Kok, C.W. Leung, P.T. Lai, et al., Transient sensitivity of sectorial split-drain magnetic field-effect transistor, IEEE Trans. Magn. 49 (7) (2013) 4048–4051. [11] Q. Guo, D. Zhu, Y. Yao, CMOS magnetic sensor integrated circuit with sectorial MAGFET, Sens. Actuat. A-Phys. 126 (2006) 154–158. [12] A. Chovet, C.S. Roumenin, G. Dimopoulos, N. Mathieu, Comparison of noise properties of different magnetic-field semiconductor integrated sensors, Sensor. Actuator. A21-A23 (1990) 790–794. [13] N. Mathieu, P. Giordano, A. Chovet, Si MAGFETs optimized for sensitivity and noise properties, Sens. Actuat. A Phys. 32 (1–3) (Apr. 1992) 656–660. [14] R.J. Baker, CMOS Circuit Design, Layout, and Simulation, fourth ed., Wiley-IEEE Press, 2019. [15] C.W. Kok, W.S. Tam, CMOS Voltage References: an Analytical and Practical Perspective, first ed., Wiley-IEEE Press, 2013. [16] Z.B. Randjelovic, M. Kayal, R. Popovic, H. Blanchard, Highy sensitive Hall magnetic sensor microsystem in CMOS technology, IEEE J. Solid-State Circ. 37 (2) (Feb. 2002) 151–159. [17] S. Tajima, P. Wu, Y. Okuda, T. Watanabe, T. Uchiyama, Magneto-impedance sensor based on time analog to digital converter (TAD) for circuit integration, IEEE Trans. Magn. 51 (11) (Nov. 2015) 1–4. [18] S.F. Lai, W.K. Ng, W.S. Tam, C.W. Kok, H. Wong, A Low Power CMOS magnetic field sensor consisting of a MAGFET and a pulse width modulated readout circuit, in: Proc of IEEE International Conference on Electron Devices and Solid-State Circuits, Oct. 2017, pp. 1–2. [19] P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2016. [20] Y.J. Min, C.K. Kwon, H.K. Kim, C. Kim, S.W. Kim, A CMOS magnetic Hall sensor using a switched biasing amplifier, IEEE Sens. J. 12 (5) (May 2012) 1195–1196.
Fig. 3. Illustrative timing diagram of the ramp voltage VC and the gate voltage of M1 of the proposed circuit subject to a magnetic field strength of −200 mT.
5. Conclusion A low-power high-resolution SSD-MAGFET based magnetic sensor implemented in 2.5 𝜇 m metal gate CMOS process was proposed. The proposed circuit provides digital information about the polarity, strength of the magnetic field and rate of change in field strength acting on the SSD-MAGFET. The digital readout allows seamless integration to the MCU system with digital I/O only. The proposed circuit does not require the use of sophisticated amplifier nor precise voltage reference to convert the difference drain voltage of the SSD-MAGFET. Instead, only simple time integrator is applied to provide high dynamic range and high resolution direct digital readout. Moreover, the conversion noise and conversion offset of the SSD-MAGFET were canceled out in the extraction of the differential drain voltage, without the help of sample-and-hold nor complicated noise removal circuitry. The proposed circuit consumes 67.5 mW at supply voltage of 5 V. It achieves high accuracy of 1.226 mT/bit for the field range of ±313.96 mT with minimum conversion rate of 17.6 Hz with an internal clock rate of 18 kHz. The conversion rate can be improved by increasing internal clock rate without sacrificing the conversion accuracy by adjusting the off-chip capacitor appropriately. Higher performance in terms of the compactness of the silicon size, and the lower power consumption is expected by implementing the proposed circuit with more advanced CMOS technology. However, the 2.5 𝜇 m CMOS technology only requires 5 masks to complete the design, which is an extremely low cost technology, while the fabricated chip presented in the experimental section has shown that high performance magnetic sensor can be achieved with 2.5 𝜇m CMOS technology. As a result, an excellent cost/performance tradeoff can be obtained with the proposed magnetic sensor fabricated on 2.5 𝜇 m CMOS technology for current market. Author statement S.F. Lai: Writing – Original draft preparation, Formal analysis. W.S. Tam: Writing – Review & editing, Investigation, Methodology,
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Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
CMOS low power split-drain MAGFET based magnetic field strength sensor Shuk-Fun Lai a , Wing-Shan Tam b, ∗ , Chi-Wah Kok b , Hei Wong a a b
Department of Electronic Engineering, City University of Hong Kong, Hong Kong, China Canaan Semiconductor Limited, Hong Kong, China
A R T I C L E
I N F O
Keywords: MAGFET Magnetic sensor Time-to-digital conversion
A B S T R A C T
A low-power sectorial split-drain MAGFET (SSD-MAGFET) based magnetic field strength sensor consists of a simple counter-based time-to-digital converter was proposed, which converts the magnetic field strength into a digital value by observing the relative drain voltage difference in the SSD-MAGFET, thus eliminating the adverse effect of device and circuit noises without the need of sophisticated operational amplifier nor precise voltage reference. Complete digital readout of the magnetic field strength, field polarity and conversion time information facilitates the seamless integration of the proposed circuit to read-time application. The proposed circuit is fully compatible with standard CMOS process and the presented design example was implemented on 2.5 𝜇 m metal gate CMOS process which achieves conversion accuracy is of 1.226 mT/bit for the field range of a maximum dynamic range of ±313.96 mT, and the minimum conversion rate is 17.6 Hz where the whole chip consumes an average of 67.5 mW at supply voltage of 5 V, which is suitable for seamless integration with all sorts of MCU applications.
1. Introduction With technology advancement in future vehicles and the development of Internet of Things (IoT) technology, there is increasing demand in magnetic sensors for applications, such as motor driving, motion detection, current measurement, biomedical sensing, etc. Lots of researches have been devoted to improve the sensitivity and stability of the magnetic sensors by exploiting their geometry, structures and materials applied to construct the sensors [1–3]. Besides, a variety of circuit techniques are developed to suppress sensor and circuit noises [4–6]. Moreover, with the new demand in IoT application, the readout of the magnetic sensor is migrating from analog to digital, such as to facilitate the integration of the sensors with external micro-processing units, or further fulfilling the real-time readout application [7–9]. Among a variety of solid-state magnetic sensing devices, split-drain magnetic fieldeffect transistor (SD-MAGFET) is a prominent device for monolithic magnetic sensor because it can be fully integrated into standard CMOS process. Moreover, SD-MAGFET consumes less power when compared to the conventional Hall plate devices, and in particular, the sectorial SD-MAGFET (SSD-MAGFET) is regarded to be able to achieve better magnetic sensitivity than other type of SD-MAGFETs in the same silicon area [10,11]. When the drains of the SD-MAGFET are connected to two current sources, the difference voltage between the two drains will
be proportional to the magnetic field strength applied to the channel of the SD-MAGFET, where the difference voltage is also known as the Hall voltage, which can be easily digitized, or converted into differential current. Nonetheless, SSD-MAGFET has the same drawback as that of Hall plate where it suffers from sensing noise and device offset problems, which are process or layout dependent, or are generated in the course of sampling by the subsequent conversion circuits. Both sensing noise and circuit noise are error sources that hamper the linearity and accuracy of the magnetic sensor. With the SSD-MAGFET as the core magnetic field sensing element of the proposed circuit, its noise characteristic has the crucial effect on the overall noise performance of the proposed circuit. The SSD-MAGFET is low frequency 1/f dominated [12,13] which can be effectively suppressed by common correlation double sampling (CDS) or related noise canceling techniques widely adopted in sensor applications. CDS is a simple circuit technique applied to deal with sampling noise and device offset with the aid of sample-and-hold circuits [14], at the cost of complicated circuitry and high power consumption. To avoid using sampleand-hold circuit, the cross-coupled sensing elements with signal conditional circuit was proposed. However, the efficiency of the circuit is low because of the extra power required to drive multiple sensing elements. Furthermore, the noise and offset of the resulting circuit is highly dependent on the performance of the operational amplifier [6] which
∗ Corresponding author. E-mail address: [email protected] (W.-S. Tam). https://doi.org/10.1016/j.mejo.2020.104759 Received 29 April 2019; Received in revised form 17 February 2020; Accepted 16 March 2020 Available online 3 April 2020 0026-2692/© 2020 Elsevier Ltd. All rights reserved.
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in turn increased the required complexity of the overall sensing circuit. Current spinning technique can be applied to sensing devices to produce differential current proportional to the magnetic field strength, which can be applied to cancel the error aroused from the offset of the sensing device [4,5]. However, the use of chopper stabilized current integrator is indispensable in current spinning technique, which requires careful design of low-pass filter to eliminate the effect of the chopper frequency at the output. To overcome the requirement of high complexity analog circuitry, the noise and offset cancellation can be rendered in the digital domain by applying simple analog-to-digital front-end to convert the analog output of the sensing element into a digital value [7,8,15,16]. Therefore, our proposed circuit proposed to convert the magnetic field strength into time signal by integrating the relative difference of the induced drain voltages of the SSD-MAGFET, such that the noise on the SSD-MAGFET can be effectively suppressed similar to the noise cancellation approach presented in literature [9]. A complete digital conversion front-end by self comparing and integrating the time delay between the sensed signal and its delayed version has been proposed in Ref. [9], which achieves ultra-low power implementation and it does not require the use of internal reference circuit. Ref. [17] also proposed a time-to-digital converter which converts the magnetic field strength sensed by the magnetic-impedance (MI) sensor consists of a pick-up coil and an amorphous wire. The MI sensor is driven by an alternative pulse to pick up the magnetic field in longitudinal direction of the wire. The output of the MI sensor is treated as the supply voltage to the inverter-based delay line on the FPGA, known as ring delay line (RDL), where its output is coupled to a fixed counter. The pulse width of the output of the RDL is integrated by the counter-based time-toanalog converter, where the output of the fixed counter is the digitized value of the sensed magnetic field strength. It should be noted that the delay time of the output of RDL is linearly proportional to the sensed magnetic field strength, thus the counter output value. The circuit presented in Ref. [17] is efficient in reducing the component count and achieves high resolution, but the MI sensor cannot be integrated with the controller circuit. In Ref. [18], a modified time integrator dedicated in converting the difference voltage of the SSD-MAGFET into a pulsewidth-modulated (PWM) signal was proposed, where the SSD-MAGFET is biased with simple resistors without the need of complicated driving circuits. In this paper, a SSD-MAGFET based magnetic sensor that adopts a similar time integrator approach is proposed. The integrator is incorporated with a counter-based time-to-digital converter, which achieves simple conversion to the SSD-MAGFET readout without complicated circuitry. Moreover, conversion cycle of the counter-based converter is self-adjusted according to the signal to be converted, such that the conversion efficiency can be improved. In the meantime, a digital readout for the field strength, the field polarity and the rate of change of field strength is readily available, which provides the essential information for real-time processing without stringent need of external signal processing unit. The proposed circuit is simple and CMOS compatible including the sensing elements, which makes the proposed circuit suitable for battery-powered IoT application.
Fig. 1. Schematic of the proposed sensor determining the rate of change of magnetic field.
age of the SSD-MAGFET is proportional to the magnetic field strength B acting on the device [10], such that V1 − V2 = KB,
(1)
where K is the conversion gain of the SSD-MAGFET, and the sign of B is the polarity of the applied magnetic field, where positive sign and negative sign refer to the north and south poles respectively. Initially (t = t0 ), the capacitor C is empty and hence VC = GND. Therefore, the outputs of the comparators A1 and A2 will be equal to O1 = O2 = VDD , thus the output of NAND1 equals GND which biases transistor M2 to cutoff. As a result, the capacitor C is being charged up by the current source IC , and at time t0 , the capacitor voltage VC is given by V C (t ) =
IC t . C
(2)
Without loss of generality, assume the magnetic field B is of south pole, which will induce V1 > V2 . As long as VC (t) < V2 , the output of the two comparator will be O1 = O2 = VDD . At time t1 , C has been charged with t1 − t0 seconds to achieve VC (t1 − t0 ) = V2 , the comparator output O2 = GND, which will toggle the NAND1 output to VDD , and turn M2 on. This will alter the charging current to C from IC to IC − ID . At the same time, the output of EXOR1 changes from GND to VDD , which allows the clock signal OSC1 with frequency f to pass through AND2 to clock into COUNTER1. The value of O1 is clocked into the D-flipflop (DF1) at the same time, which indicates the polarity of the field strength. The COUNTER1 will store the number of clock cycles up to the time when VC is high enough to turn both O1 and O2 to GND. This happens on t = t2 and is given by
2. Proposed circuit Showing in Fig. 1 is the schematic of the proposed circuit, which consists of a SSD-MAGFET, two comparators (A1 and A2 ), two current sources (ID and IC ) and a number of digital gates, which serves as a digital integrator to convert the Hall voltage (V1 − V2 ) into a digital value. The SSD-MAGFET is biased into saturation mode by adjusting its gate voltage at Vb to promote the linearity in converting the magnetic field strength into the differential drain voltages of the SSD-MAGFET [10]. The two resistors R1 and R2 are connected to the two drains of the SSD-MAGFET, where the values of R1 and R2 are chosen (through trimming in actual implementation) to equalize the two drain voltages (i.e. V1 and V2 ) when there is no magnetic field applied, such that the offset in the SSD-MAGFET can be mitigated. The differential drain volt-
t2 =
C (V 1 − V 2 ) + t1 . IC − ID
(3)
At the same time, the output of NOR1 will turn to VDD from GND, and trigger the one-shot device to generate a pulse with duration TS second at O3 , where TS is the reset time. The time duration TS is set to be long enough to turn M1 on to discharge C and bring VC to GND and the circuit is reset to the initial state (t = t0 ) with an empty C and both O1 and O2 at VDD . Besides resetting the circuit, the O3 pulse will also help to latch the values in COUNTER1 and COUNTER2 into LATCH1 and LATCH2, 2
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respectively. Let’s denote N1 and N2 as the count numbers latched in LATCH1 and LATCH2, respectively. The conversion period (tp ) can be obtained from N1 as tp = t2 − t1 = ⇒ N1 =
N1 C = (V − V 2 ) f IC − ID 1
fC(V1 − V2 ) fCKB = . IC − ID IC − ID
(4) (5)
It should be noted that N1 is linearly proportional to B. The output of DF1 will also be latched to the most significant bit (MSB) of the LATCH1, which is the value of O1 at t1 . O1 will be VDD when B is of south pole, and will be GND when B is of north pole. The N2 is the number of clocks in between two consecutive O3 pulses, i.e. the time between two initial states/conversion cycles denoted by tmax = t2 − t0 + TS , and is given by N2 = f tmax .
Fig. 2. Measured difference drain voltages (V1 − V2 ) of the SSD-MAGFET in the field range of −300 mT–300 mT.
(6)
It should be noted that the output of NOT1 is an inverted O3 , which resets the counters when O3 =VDD . Consider two consecutive conversion cycles, the (𝓁 + 1)th and the 𝓁th cycles, where the difference of the corresponding values in LATCH1 is given by
ΔN1 = N1,𝓁 +1 − N1,𝓁 ,
Table 1 Summary of the performance of the proposed circuit.
(7)
with N1,𝓁 +1 being the value of LATCH1 of the (𝓁 + 1)th cycle and N1,𝓁 being the value of LATCH1 of the 𝓁th cycle. Similarly, the difference of the corresponding values in LATCH2 at the (𝓁 + 1)th and the 𝓁th cycles can be computed as
ΔN2 = N2,𝓁 +1 − N2,𝓁 ,
(8)
where N2,𝓁 +1 is the value of LATCH2 at the (𝓁 + 1)th cycle and N2,𝓁 is the value of LATCH2 at the 𝓁th cycle. Hence, the rate of change of magnetic field strength can be computed as BR =
B𝓁 +1 − B𝓁 ΔN1 (IC − ID ) ΔN1 = ∝ , tmax,𝓁 +1 − tmax,𝓁 ΔN2 CK ΔN2
|I − I | Bmax = || C D || . 2nob1 | fCK |
2.5 𝜇 m Metal Gate CMOS Process 18 kHz 9-bit (MSB: polarity of field strength) 10-bit 17.6 Hz 5V ±313.96 mT 1.226 mT/bit 67.5 mW
in order to speed up the charging of C to bring VC to the appropriate voltage for the conversion of the difference voltage without sacrificing Bres . A greater IC could reduce t1 − t0 , thus shorten tmax . Nonetheless, greater IC would increase the current consumption of the circuit.
3. Experiment The SSD-MAGFET was fabricated in 2.5 𝜇m metal gate CMOS process. All circuit blocks in the proposed circuit, including the SSDMAGFET, the current sources, the comparators and logic circuits are fabricated. A beta-multiplier reference circuit [15] was implemented to generate a reference current, and it is further scaled to IC and ID through current mirrors. The comparators were implemented by a simple unbuffered two-stage operational amplifier with an N-channel input pair [19]. To achieve higher sensitivity, the SSD-MAGFET was biased in saturation mode by applying Vb = 1.4 V with VDD = 5 V, R1 = R2 = 56 kΩ (before trimming is being applied to equalize the difference voltage between V1 and V2 ). Fig. 2 shows the plot of the measured difference voltage (V1 − V2 ) as a function of magnetic field strength from −300 mT to 300 mT measured by ATTEN oscilloscope ADS 1062CAL, where the magnetic field is generated by permanent magnets with field strength measured by AlphaLab Gaussmeter GM2. It can be observed that the SSD-MAGFET converts the magnetic field strength into difference voltage linearly with the conversion gain given by the slope of the plot in Fig. 2, i.e. K = −302 mV/T. With f = 18 kHz, C = 150 nF, IC = 180 𝜇 A, ID = 179 𝜇 A, nob1 = 9-bit (1 polarity bit plus 8 data bits) and nob2 = 10-bit, it was found that Bmax = 313.96 mT and Bres = 1.226 mT/bit as depicted in Eq. (10) and Eq. (11), respectively. The performance of the implemented circuit is summarized in Table 1.
(10)
where nob1 is the bit length of COUNTER1. It should be noted that to achieve accurate conversion, tmax > tp + TS , such that nob2 has to be greater than nob1 to make the circuit practical. The resolution of the proposed circuit (Bres ) is determined by the magnetic field strength that can be represented by one bit of data in COUNTER1, and is given by Bres =
Values
Technology Oscillating Frequency f Readout Resolution for N1 Readout Resolution for N2 Minimum Conversion Rate f∕(2nob2 ) Power Supply, VDD Dynamic Range, Bmax Resolution, Bres Power Dissipation
(9)
where B𝓁 +1 and B𝓁 are the magnetic field strength sensed by the sensor at the (𝓁 + 1)th and the 𝓁th cycles, respectively, and tmax,𝓁 +1 and tmax,𝓁 are the conversion period for the (𝓁 + 1)th and the 𝓁th cycles, respectively. To complete the conversion, the number of bits of COUNTER2 (nob2) has to be long enough to accommodate tmax , which is given by nob2 > log2 ⌈tmax · f ⌉. For a particular nob2 and f, the minimum conversion rate of the proposed circuit is given by f∕2nob2 . It should be noted that the conversion rate of the proposed circuit is not a constant as the conversion cycle is determined to be complete and reset to initial state once VC reaches V1 or V2 , whichever is the higher value. The maximum magnitude of the magnetic field strength (Bmax ) that can be readout from each conversion is equivalent to the maximum V1 − V2 that can be resolved for a particular values of IC , ID , f, C, nob1 and K, and is given by | 2nob1 (I − I ) | | C D | Bmax = | |, | | fCK | |
Parameters
(11)
It should be noted that the charging current to capacitor C is reduced from IC to IC − ID from the period of t1 − t0 to t2 − t1 , respectively, 3
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4. Results and discussions
circuit. Therefore, it results in a design dilemma in the proposed circuit, where the appropriate Bmax and Bres would be application dependent. To better understand the operation of the proposed circuit, the timing diagram of the gate voltage applied to the transistor M1 (VM1,g ) and the ramp voltage (VC ) subject to a magnetic field strength of −200 mT is illustrated in Fig. 3. Consider t0 = 0, the circuit is initialized to bring VC = 0 V and enable the COUNTER2 to start counting the clocks generated by OSC1. The current IC charge the capacitor C and VC is increased linearly. When VC = V2 is reached (i.e. t = t1 and t1 − t0 = T1 = 1 ms), O2 will switch from VDD to GND, thus the output of NAND1 becomes VDD which turns M2 on. Since only one of the inputs of EXOR1 is in VDD (O1 in this case), the output of EXOR1 will switch from GND to VDD to clock in the O1 value to the DF1 and operate with AND2 to enable COUNTER1 to count the clocks generated by OSC1. The charging current will be reduced to IC − ID once M2 is turned on. In the meantime, COUNTER1 is triggered to count the clocks generated by OSC1. The reduced IC − ID continues to charge the capacitor C until VC = V1 is reached (i.e. t = t2 and tp = t2 − t1 = T2 = 9 ms), O2 will be turned to VDD from GND, which triggers the one-shot reset signal O3 with pulse width of TS . In the implemented circuit, TS was set at 1 ms. During TS , O3 is in VDD , the values in COUNTER1 and COUNTER2 are latched into LATCH1 and LATCH2, respectively. The value in DF1 is also latched into the MSB of LATCH1 at the same time. Both COUNTER1 and COUNTER2 are reset once the latching is complete. The digital output presented by LATCH1 and LATCH2 are N1 (i.e. tp ) and N2 (i.e. tmax ), respectively. The tp and tmax were measured to be 9 ms and 11 ms, respectively. When O3 =VDD , M1 will be turned on to discharge capacitor C to bring VC back to 0 V (the circuit is reset to initial state). It should be noted that in the implemented circuit, O1 is VDD when VC = V2 , therefore, the MSB of LATCH1 value will be in logic high, which indicates the magnetic field is in south pole. When a magnetic field in north pole is applied, V2 > V1 , such that O1 will be in GND at t = t1 and the value in the MSB of LATCH1 will be in logic low. As the MSB of LATCH1 is reserved for carrying the polarity information, a 9-bit LATCH1 was chosen. With the design requirement that nob2 > nob1, a 10-bit COUNTER2 and LATCH2 were chosen. Hence, the minimum conversion rate is f∕2nob2 = 17.6 Hz and the dynamic range is ±313.9 mT, which is suitable for magnetic sensors used in human interface system, such as rotating knobs, where the angle of rotation can be readout by having the human turning a polarized magnet on top of the SSD-MAGFET sensor. For applications that need higher operating frequency, the clock rate f could be increased and the maximum clock rate is process dependent, where the maximum f that can be achieved by the adopted 2.5 𝜇m metal gate process is up to 800 kHz. Furthermore, it should be noted that when f is increased by n-times, the value of C should be reduced by n-times such that total power consumption and conversion accuracy would not be altered disregarding the operating frequency of the circuit and the conversion time of the circuit. Compared the proposed circuit with that in Ref. [17], instead of varying the delay time of the ring oscillator, the time integration is achieved by converting the time for charging and discharging the capacitor C, with its voltage compared to the sensed voltage of the SSDMAGFET, where the linearity in charging up of a voltage on a capacitor is easily maintained through simple constant current source, while it is difficult to build a ring oscillator with oscillating frequency linearly related to the supply voltage. Therefore, the conversion linearity of the proposed circuit is more easily maintained when compared to that of the circuit reported in Ref. [17]. The 1/f noise spectral density of CMOS split-drain MAGFET is in the level of hundred nT/Hz [13] where the noise components of sensors in the proposed circuit is approximately 0.02 mT with internal clock set as 18 kHz. The noise level for the sensing element is lower than the resolution of the proposed circuit at 1.226 mT/bit, which confirms the noise effect of the sensing element is not significant.
The proposed circuit has a number of advantages when compared to traditional magnetic sensors [1,9,16], in which the proposed circuit does not only provide direct readout of the sensed magnetic field strength and field polarity, it also provides a means to generate the rate of change of magnetic field information directly from two consecutive sensing cycles without the need of an accurate time reference, and complicated sample-and-hold system. Since (V1 − V2 ) is retrieved by measuring V1 and V2 independently, and they are compared with the same voltage VC in complimentary manner with both V1 and V2 connected to the positive terminals of A1 and A2 , respectively, such that the input offset voltage imposed by the comparators will be mitigated. Due to layout mismatch between the two drains of the SSD-MAGFET, it’s drain voltages V1 and V2 have offset even when there is no magnetic field applied to the system (see Fig. 2). We propose to mitigate this problem by trimming the resistance of the resistors R1 and R2 that provides the current to the SSD-MAGFET. As a result, the magnetic field strength applied on the SSD-MAGFET can be extracted by comparing V1 and V2 to a common voltage VC , and generating the corresponding digital outputs O1 and O2 , which allow the conversion of the analog difference voltage (V1 − V2 ) into time information by counting the time difference between both O1 and O2 reaching VDD using the counter-based converter. Since errors appear on both drains will be canceled out with the detection being achieved by converting the difference voltage, no additional noise removal circuit is required. Furthermore, the conversion of the time difference between both O1 and O2 is continuous until both of them reaching VDD , such that the proposed circuit does not require the use of sample-and-hold circuits, which is simple when compared to traditional Hall sensor based system. Moreover, the proposed circuit does not require the use of sophisticated high gain amplifier to amplify the small Hall voltage [5,20], which avoids the amplification of input offset and noise aroused by the amplifiers simultaneously, thus improving the reliability and system vulnerability. In the proposed work, A1 and A2 can be implemented by simple single stage differential pair, which achieves low power operation and is fully compatible with CMOS implementation. It should be noted that even when a fixed resistance R1 and R2 are being applied without trimming to eliminate the offset of the SSD-MAGFET, the non-zero readout can be pre-stored and be used to rectify the initial offset problem during later data manipulation. It should be further noted that, the choice of R1 and R2 would affect the voltages of V1 and V2 , respectively, which would affect the duration of t1 − t0 which will be increased by greater values of V1 or V2 . As depicted by Eq. (11), the Bres can be improved (by reducing its magnitude) by reducing IC − ID , increasing C, increasing f or increasing K. Increasing the conversion gain of the SSD-MAGFET K will increase its size or fabricate it in non-CMOS compatible process, and is therefore considered to be non-favorable. Increasing f will require to use CMOS process with higher operating frequency, which will increase the fabrication cost, and power consumption. Reducing IC − ID can improve the resolution and at the same time reduce the power consumption of the circuit. Noted that with IC > > IC − ID , the conversion time (t2 − t1 ) > > (t1 − t0 ), and therefore, reducing IC − ID will increase tp , and hence the tmax . In other words, the application of a large IC helps to mitigate the long conversion time problem in traditional time-to-digital converter because of the initial drain voltage of the SSD-MAGFET under no magnetic field. Increasing C is simple, but that will elongate the tp , and increase the power consumption, since whatever charged to C will be discharged in the next conversion cycle. However, increasing C is the most easy way to allow user to adjust the conversion accuracy, which can be altered through off-chip adjustment. The Bmax and Bres have counter effects on the performance of the circuit. The smaller the Bres , the finer the step size of COUNTER1, whereas the larger the Bmax , the greater the field strength that can be detected by the
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Resources. C.W. Kok: Conceptualization, Methodology, Writing – Original draft preparation, review & editing. H. Wong – Supervision, Resources, Writing – review. Declaration of interests The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. References [1] H. Blanchard, M.F. De, B.J. Hu, R.S. Popovic, Highly sensitive Hall sensor in CMOS technology, Ses. Actuat. 82 (2000) 144–148. [2] R.S. Popovic, Z. Randjelovic, D. Manic, Integrated Hall-effect magnetic sensors, Sensor. Actuator. 91 (2001) 46–50. [3] Y. Nishitani, M. Endo, F. Matsukura, H. Ohno, Magnetic anisotropy in a ferromagnetic (Ga,Mn)Sb thin film, Phys. E Low-dimens. Syst. Nanostruct. 42 (10) (2010) 2681–2684. [4] H. Huang, D. Wang, X. Yue, A monolithic CMOS magnetic Hall sensor with high sensitivity and linearity characteristics, Sensors 15 (10) (Oct. 2015) 27359–27373. [5] H. Heidari, E. Bonizzoni, U. Gatti, F. Maloberti, A CMOS current-mode magnetic Hall sensor with integrated front-end, IEEE Trans. Circ. Syst. I: Reg. Pap. 62 (5) (Apr. 2015) 1270–1278. [6] Y. Xu, H.B. Pan, S.Z. He, L. Li, A highly sensitive CMOS digital Hall Sensor for low magnetic field applications, Sesnors 12 (2) (Feb. 2012) 2162–2174. [7] S.L. Chen, C.H. Kuo, S.I. Liu, CMOS mangietc field to frequency converter, IEEE Sens. J. 3 (2) (Apr. 2013) 241–245. [8] C. Azcona, B. Calvo, S. Celma, N. Medrano, P.A. Martinez, Ratiometric voltage-to-frequency converter for long-life autonomous portable equipment, IEEE Sens. J. 13 (6) (Jun. 2013) 2382–2390. [9] A. Yelkenci, O.Z. Batur, B. Sarioglu, Ultra low power all-digital CMOS sensor read out circuit for optically powered biomedical systems, in: Proc of the 9th Int Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI), Oct. 2016. [10] Z.Y. Yang, S.L. Siu, W.S. Tam, C.W. Kok, C.W. Leung, P.T. Lai, et al., Transient sensitivity of sectorial split-drain magnetic field-effect transistor, IEEE Trans. Magn. 49 (7) (2013) 4048–4051. [11] Q. Guo, D. Zhu, Y. Yao, CMOS magnetic sensor integrated circuit with sectorial MAGFET, Sens. Actuat. A-Phys. 126 (2006) 154–158. [12] A. Chovet, C.S. Roumenin, G. Dimopoulos, N. Mathieu, Comparison of noise properties of different magnetic-field semiconductor integrated sensors, Sensor. Actuator. A21-A23 (1990) 790–794. [13] N. Mathieu, P. Giordano, A. Chovet, Si MAGFETs optimized for sensitivity and noise properties, Sens. Actuat. A Phys. 32 (1–3) (Apr. 1992) 656–660. [14] R.J. Baker, CMOS Circuit Design, Layout, and Simulation, fourth ed., Wiley-IEEE Press, 2019. [15] C.W. Kok, W.S. Tam, CMOS Voltage References: an Analytical and Practical Perspective, first ed., Wiley-IEEE Press, 2013. [16] Z.B. Randjelovic, M. Kayal, R. Popovic, H. Blanchard, Highy sensitive Hall magnetic sensor microsystem in CMOS technology, IEEE J. Solid-State Circ. 37 (2) (Feb. 2002) 151–159. [17] S. Tajima, P. Wu, Y. Okuda, T. Watanabe, T. Uchiyama, Magneto-impedance sensor based on time analog to digital converter (TAD) for circuit integration, IEEE Trans. Magn. 51 (11) (Nov. 2015) 1–4. [18] S.F. Lai, W.K. Ng, W.S. Tam, C.W. Kok, H. Wong, A Low Power CMOS magnetic field sensor consisting of a MAGFET and a pulse width modulated readout circuit, in: Proc of IEEE International Conference on Electron Devices and Solid-State Circuits, Oct. 2017, pp. 1–2. [19] P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2016. [20] Y.J. Min, C.K. Kwon, H.K. Kim, C. Kim, S.W. Kim, A CMOS magnetic Hall sensor using a switched biasing amplifier, IEEE Sens. J. 12 (5) (May 2012) 1195–1196.
Fig. 3. Illustrative timing diagram of the ramp voltage VC and the gate voltage of M1 of the proposed circuit subject to a magnetic field strength of −200 mT.
5. Conclusion A low-power high-resolution SSD-MAGFET based magnetic sensor implemented in 2.5 𝜇 m metal gate CMOS process was proposed. The proposed circuit provides digital information about the polarity, strength of the magnetic field and rate of change in field strength acting on the SSD-MAGFET. The digital readout allows seamless integration to the MCU system with digital I/O only. The proposed circuit does not require the use of sophisticated amplifier nor precise voltage reference to convert the difference drain voltage of the SSD-MAGFET. Instead, only simple time integrator is applied to provide high dynamic range and high resolution direct digital readout. Moreover, the conversion noise and conversion offset of the SSD-MAGFET were canceled out in the extraction of the differential drain voltage, without the help of sample-and-hold nor complicated noise removal circuitry. The proposed circuit consumes 67.5 mW at supply voltage of 5 V. It achieves high accuracy of 1.226 mT/bit for the field range of ±313.96 mT with minimum conversion rate of 17.6 Hz with an internal clock rate of 18 kHz. The conversion rate can be improved by increasing internal clock rate without sacrificing the conversion accuracy by adjusting the off-chip capacitor appropriately. Higher performance in terms of the compactness of the silicon size, and the lower power consumption is expected by implementing the proposed circuit with more advanced CMOS technology. However, the 2.5 𝜇 m CMOS technology only requires 5 masks to complete the design, which is an extremely low cost technology, while the fabricated chip presented in the experimental section has shown that high performance magnetic sensor can be achieved with 2.5 𝜇m CMOS technology. As a result, an excellent cost/performance tradeoff can be obtained with the proposed magnetic sensor fabricated on 2.5 𝜇 m CMOS technology for current market. Author statement S.F. Lai: Writing – Original draft preparation, Formal analysis. W.S. Tam: Writing – Review & editing, Investigation, Methodology,
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