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CMOS process review with implications for ion implantation
96
Nuclear Instruments and Methods in Physics Research B21 (1987) 96-103 North-Holland, Amsterdam
CMOS PROCESS REVIEW WITH IMPLICATIONS FOR ION IMPLANTATION T.E. S E I D E L Diamond Cubic Corporation, Oceanside, CA 92054, USA
Ion implantation has been an essential technology for the development of CMOS processes. This paper reviews the origins of the various uses of implantation in CMOS, and discusses present and future applications. There are four parts: i. Design rule history, 2. Discussion of CMOS technologies, 3. Technical issues, 4. Implant usage and implications for CMOS. Key references for this paper are those of Chen [1], Parrillo et al. [2], Bastami [3], Borland [4] and the 1986 Symposium on VLSI Technology [5].
1. Design rule history Fig. 1 shows the leading edge production design rules, plotted against the year of their introduction. The "design rule" is defined as the arithmetic average for minimum feature size of: gate and source and drain region (GASAD), gate, window and contact. In 1986, the leading edge prove-in is about 1.1 ttm [1]. There has been a steady progression from 5.0 to 1.0 gm since 1975 [3], and further progress toward 0.8 and 0.5 #m is expected. Bastami expects 0.3 #m to be in production by 1995 [3]. This presumes that incremental improvement in speed and current performance can be obtained by further scaling, that the thermal limit of 4 k T - 0.1 V will not make room temperature operation poor from noise margin, and that reduced voltage operation is acceptable. Also shown in fig. 1 is the gate oxide thickness which has been scaling linearly with the feature sizes. The integrity of thin gate oxides during implant has been a yield problem for several years, and it is a critical challenge for implant applications. Also shown in fig. 1 are the various major technologies that have been introduced along with the design rule progression. At and above - 2 . 0 gm a LOCOS isolation technology can be used, where oxide step heights are partially recessed and "bird's beak" crosssectional topology gives significant lateral encroachment to the G A S A D region. For - 1 . 0 gm technology a number of innovations are used. They are: recessed FOX isolation [6-8], side-wall oxide on the GOX, direct field implants with little thermal diffusion, silicide contacts, polycide gates, lightly doped drains (LDD) [9], contact filling and retrograde wells. Many of these innovations will be discussed below in the context of implant usage. In order to obtain 0.5 #m feature sizes, it is likely that other isolation techniques will be used and further developed, such as trench isolation, selective epitaxial
growth (SEG), or some form of silicon on insulator (SOI) [10].
2. Discussion of CMOS technologies 2.1. P-weU
The earliest CMOS was implemented in P-well technology. In the early 70s, positive interface charge was a control problem and implantation was not yet fully accepted. With bipolar base diffusion furnaces in operation, and the need to dope the well surface concentration to levels that exceeded the maximum positive interface charge, it was natural to select a P-well approach, which avoided surface inversion. A standard P-well cross section is shown in fig. 2. The diffused P-well suffered from reproducibility and limited the control of the threshold voltages. Since the charge in a P-well is - 1 0 1 3 / c m 2, this is a natural application for implantation. Poly was doped by phosphorus diffusion. This was and is good practice if technically appropriate. There is no gate oxide breakdown issue, glass removal is simple since poly at the doping stage may be unpattemed. Today however one may wish to use different dopants for n and p channel transistors and this suggests implantation. In the oldest P-well processing, the source and drains were diffused from doped glass sources. In retrospect, there were no channeling effects and no gate oxide breakdown problems, however there was a problem of removing the glass after diffusion. If the glass was under etched, glass remained and gave contact problems, if over etched undercutting of the gate oxide would lead to source-gate and drain-gate leakage. Early attempts to use diffusion technology for self-aligned source and drain P-well CMOS were abandoned. Today however, side wall oxide spacer tech-
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T.E. Seidel / CMOS process review
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niques are well developed. It would seem that an opportunity exists to re-explore the use of diffused boron p+ source and drain junctions. An LPCVD deposited BSG glass would provide a diffused source which has advantages: (i) has no channeling control problems, (ii) has no gate oxide breakdown problem, (iii) low capital and operational cost. However, the disadvantages are: (i) an extra glass removal step, (ii) perhaps an extra masking step, (iii) perhaps an oxinitride layer for the P-channel to avoid diffusion thru the gate oxide. Presently, low energy implantation into the sourcedrain regions where contact silicides already exist would seem to solve the implant channeling problem [11]. The P-well technology also offers opportunity to use high energy boron implants (as opposed to very high energy implants for phosphorus) to effect a retrograde P-well [12], latchup free structure. Threshold adjust implants are also done. The device characteristics of P-well technology result in the better transistor (the NMOS) having degraded performance in comparison to an N-well approach:
junction capacitance is high because of the relatively high P-well doping, the body effect is prominent i.e. transconductance is relatively poor, and hot electron effects are prominent. The NMOS transistor "defaults", it is degraded down towards the PMOS performance [1]. Today's use is mainly for SRAM devices, the NMOS and PMOS are "balanced", the NMOS has good punch thru characteristics and the NMOS has soft error immunity as it is placed in the P-well [3].
2.2. The effect of 4,.,~ offset Before discussing other "well" technologies, the impact of ~ms on the symmetry of thresholds should be briefly discussed. This issue plays an important role on the direction of technology development. Fig. 3 shows the schematic dependence of threshold voltage for NMOS and PMOS transistors as a function of body doping. The model assumes a long channel, uniform doped case. The threshold voltage is: to
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where q~ms is the metal (gate) simiconductor work function, Qi is the interface charge, ~¢ is the fermi-potential and t 0, c0,A 0 are oxide thickness, dielectric constant and area respectively and N b is the body doping. In the schematic a negative ~ms appropriate to phosphorus doped poly is used and t o of - 500 A was used. As the body doping N b is increased thresholds increase as the ~ b for both N and PMOS transistors. However, ~ms creates an offset, so for useful doping concentrations of --1016/cm 3 the VTp and VTn values are significantly I. REVIEWS
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different. V.r, for example may be +0.6 volt, while VTp is - 1 . 6 volt. Even if N b were adjusted the threshold would not reach - 0.6 V, since the dependence on Nb is weak. In the past the problem of addressing the @ms offset was to "threshold adjust" by implanting a surface layer of charge such that a voltage shift of the desired amount would be obtained: Qs -= Co AVT, where Qs is the ion implant dose. If the threshold implant is not very shallow, high subthreshold leakage degrades device performance. Approaches to obtain symmetric threshold characteristics include selection of alternate gate materials such as MoSi 2 or other metals or metal silicides. However, selective implant doping the gate poly (n-type poly for NMOS and p-type poly for PMOS) could be used. N
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One limiting problem with P-well technology at small design rules is avalanche effects in the NMOS transistor. Charge injected into the gate oxides causes gate instabilities or gate reliability problems. This is particularly true with small design rules - 1.0 #m, when trying to maintain high supply voltages, i.e. 5 V. It was recognized that the NMOS avalanche effects could be reduced by going to an N-well structure, thus reducing the electric field for the field-sensitive NMOS transistor [14].
Since the N-well structure is built on p substrate material, IC houses which already have established N M O S technology could readily transfer all process technology and simulations from NMOS to CMOS by
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and P type poly would result in relatively higher N b for lower thresholds and allow smaller design rules. In other words, appropriately doped poly would scale better. Implantation can play a role by doping poly gates. However, the speed performance of ICs is also determined by the conductivity of interconnects, so overall performance may in fact favor a metal or metal silicide gate with more or less symmetric @ms properties. Recently Noguchi et al. [13] have explored the use of MoSi 2 for gates. The intent is to use a silicide with mid-gap @ms to symmetrize the threshold characteristics to produce maximum drivability. For 1 #m channel lengths, the drain currents of n and p channel transistors are different by a factor of 2 (mobility differences), however the currents of MoSi 2 are higher than n + poly for N M O S and p+ poly for PMOS together. See fig. 4.
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T.E. Seidel / CMOS process review
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dropping the NMOS transistor into the CMOS structure in a transparent way. The NMOS transistor is highly optimized. Body doping is relatively low, junction capacitance is small, body effect on transconductance is small and the avalanche effects are small. However, even the N-well approach does not save one from needing to further reduce the electric field near the drain of the NMOS transistor. The use of lightly-doped drains (LDD), spreads the field out and allows relatively higher voltages to be applied for a given design rule. This is shown schematically in fig. 5. At the lowest design rules - 0.3 /~m one will need LDD structures even for the PMOS transistor. The substrate for N-well technology is p - or pp+. Excellent intrinsic gettering has been obtained with pp ÷ substrate systems which is compatible with a CMOS thermal process sequence. The use of N-well technology is expected to become pervasive, with NMOS rich circuits, logic, dynamic memories, and high voltage EPROMS [1,3]. Wang et al. [15] have demonstrated a 0.5 /~m gate (MOS) in N-weU technology. They used LDD-N ÷, phosphorus-arsenic junctions with ~ , - 0.15/~m and a preamorphized boron implant sequence to obtain ~p 0.16/~m.
Applications around 0.5-1.0 ~m design rules would seem to appeal to twin-tub usage since scaling down requires small space charge widths in the source-drain region. One has to dope-up the tub regions anyway in order to avoid punch thru. Use of twin-tub implants moves the burden for doping control from the wafer manufacturer to the implant-IC manufacturer. However, if very uniform substrate doping becomes available, then the IC manufacture could be less expensive with single-well processing. Although the n + to p+ spacing is improved by using self-aligned chart stops in the twin-tub process, there is necessarily compensation of the chart stop doping at the p-tub to n-tub intersection. In this region the surface is easily inverted and gives rise to a layout loss proportional to the compensated region width. This problem naturally suggests a trench isolation solution. Trench isolation is very compatible with twin-tub technology because the problem of side wall inversion of the trench is avoided by the high doping required in the tubs for the sub-micron design rule case. Today's twin-tub technologies use implantations rather pervasively: N-tub, P-tub, Chanstops, VT adjusts, poly or polycide, p+ and n + source and drains. Applications for twin-tub utilizations could follow the guide lines mentioned above for N and P-wells, NMOS rich circuits, and DRAMs could have N-well character with p or pp+ substrates, while SRAMs could have P-well character with n or nn + substrates. There may be some reluctance to transfer older design rule devices into new substrate choices since the new engineering may cost more than the value added to the device performance [1,3]. Twin-tub technology has been implemented using a sub-micron 3D-surface orientation for the optimized PMOS mobility by Kinugawa et al. [16]. The surface hole mobility for 110 surfaces is 1.5 × the mobility for 100 surfaces. By putting the PMOS transistor on the 110 side wall, higher mobility and space saving are obtained simultaneously. See fig. 7. Threshold control is not discussed and junction leakage is reported to be only marginally worse than conventional PMOS transistors.
2.4. Twin-tub
Although twin-tub technology was introduced in 1980 by Parrillo et al. [2] with 3.0 ~m design rules, both transistors NMOS and PMOS have high body doping and therefore high Cj, body effect and susceptibility to avalanche effects. One driving force for twin-tub acceptance is complete flexibility of process attributes: both threshold voltages can be independently controlled, channel stops (high doping under the field oxide to prevent inversion) can be independently controlled, and one is free to choose either nn + , n - , p - or pp + substrate systems as dictated by issues described under N-well and P-well descriptions. See fig. 6.
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Limitations in the performance of CMOS include latchup, high junction capacitance Cj, body effect on transconductance, and n+p + spacing. By using a tub implantation of high or very high energy ions, one gets a buried maximum concentration which will lower the vertical bipolar gain of the bipolar transistor placed in that tub [12]. The lateral gain of the transistor placed in the substrate can also be reduced. Further, the high conductivity of the sub-tub region will shunt bipolar currents away from the gain connected SCR loop causing latchup. Thus retrograde well approaches can give excellent latchup protection. This is done both by the bipolar gain reduction and current shunting mechanisms. Although higher tub doping is required to obtain the latchup protection, the use of MeV implants increases the doping where it is needed and not near the surface. Thus the latchup protection is provided without impacting the surface MOS characteristics, such as C~ or the body effect. In twin-tub technology, the compensated dead layer width can be reduced since high doping can be placed at the tub intersection by the retrograde p and n implants. This can help the n+p + spacing. When retrograde doping is used as an "add on" to twin-tub technology, the term QUAD-well has been coined [17]. The retrograde approach is an outstanding technical triumph for implantation in CMOS usage. However, one faces the issues of cost and question of the reliability of operation for MeV implant equipment in a production environment. 3. Technical issues 3.1. Hot electrons
The avalanche coefficient is much greater for electrons than holes in silicon. Thus, for a given electric
field strength the multiplication of carriers is relatively easy for n ÷ drains, giving rise to electrons which transport to the gate oxide and holes which are injected into the substrate. At somewhat higher electric field strengths even the p+ drains will exhibit avalanche multiplication (e.g. for 0.3/~m design rules) [18]. The excess charge will result in drifts or instabilities in the threshold voltages and also in the transistor's transconductance. The technological solution to this problem has been through the use of lightly doped drains (LDD), where the n + junction is engineered to be graded: nn +. The electric field is then spread out into the bulk-tub and into the drain region, allowing relatively high supply voltages with lower peak electric fields. Good control of the doping profiles are needed in order to get good turn on characteristics and to limit the reduction in MOS transistor gain gm from the added series resistance of the n region. The LDD solution appears not to be completely satisfactory and complete recipes are not yet in the open literature [1]. This may be a special opportunity for excellent interfacing between implant and device technologists. 3.2. Isolation
CMOS has used, for the most part, junction isolation. This is typified by tub/substrate or tub to tub junctions in single-well and twin-tub technologies respectively. The field oxide serves to stand off voltages on signal rails. Today's advanced technology uses a recessed field oxide (to give topological patterning advantage) while employing retrograde wells to minimize the dead space in the tub to tub compensated region. Another isolation approach would employ a trench combined with twintubs. Trench isolation can be used very effectively if the trench reaches down to a heavily doped plane (which could be implanted) or to a heavily doped epi substrate [10,19]. The capability of trench technology, combined with MeV implant may obviate the need for expensive epi. This choice will be decided on yield, performance and cost as the field matures. Beyond the trench or trench refill approach, one may look to selective epi growth as another alternative. The two isolation approaches are shown in fig. 8. The trench refill makes cuts in the substrate material, providing relatively narrow regions to be refilled down with SiO2, while the selective epi growth (SEG) makes cuts in an oxide layer, leaving behind relatively narrow oxide regions-the silicon epi is then grown up on the underlying substrate. In the example shown the trench refill is done into p - bulk with an MeV p+ implant. This could provide retrograde isolation, latchup protection, limited alpha particle immunity, and partial side wall chan stopping.
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3.3. Latchup
Latchup immunity can be provided basically by bipolar gain t-spoiling or by shunting bipolar currents away from the SCR circuit or by dielectric isolation, DI [1,3]. Examples of t-spoiling include retrograde wells, Schottky source-drain contacts and gold or damage lifetime killing. The Schottky approach also gives high leakage and rules out DRAM application, but would be suitable for logic. The gold or damage lifetime killing has not found acceptance because of control problems and limited application use. Examples of approaches which limit latchup by current shunting are: retrograde doping, epi substrate (p+ or n +) doping, very high energy uniform doped plane doping and guard ring design approaches. Examples of dielectric isolation are: Trench, SEG and SOI. The Trench and SEG were described above. One example of SOI which will reduce the n+p + spacing to near absolute minimum and give latchup immunity would be where the complementary transistor is placed on the field oxide. A recessed field oxide would be most appropriate to allow good laterial solid phase epitaxy. A deposited polysilicon film can be made amorphous by implantation and seeded in the drain region of the primary transistor and solid phase epitaxy can grow laterally on the oxide. The complementary transistor is fabricated in the laterally grown solid phase epitaxy material.
4. Summary of implant usages for CMOS 4.1. Present and past use
This topic is divided in low dose and high dose applications. For low doses we have: N and P tub, N and P tub chan stops, N and P tub retrogrades and VTP and VT~ threshold adjusts.
101
Since phosphorus and other n-type dopants are segregated ahead of an oxidizing interface and since oxidation often follows implantation to play a role in subsequent masking, the N implants often are sequenced prior to P implants [2]. B o r o n - i f oxidizedwould disperse through the oxidized layer, the amount of boron kept in the silicon is then dependent on the exact oxidation conc[itions thus giving a process control problem. Both tub implants and chan stops can be done using self-aligned LOCOS type processing where one mask operation per two implant steps is utilized. Retrograde implants require thick, often deposited layers to give good stopping effects. Deposited oxides, thick photo resist and dense deposited metal layers are useful as high energy masking materials. The tub doses and chan-stop doses may be high enough to result in stacking fault nuclei if annealed directly in an oxidizing ambient. One practice is to anneal using a neutral/oxidizing sequence where the neutral first dissolves the SF nuclei and the desired oxidation is still obtained [20]. For VT adjusts, one wants low energy, close to the surface implants, annealed with very limited thermal diffusion-an opportunity for implantation plus rapid thermal processing (RTP). For high doses one has: poly silicon or gate doping, source and drain (n ÷ and p+) and the lightly doped regions (LDD) of source and drains. Doping the gates can in many cases be done with diffusion technology. Here the threat of gate oxide damage is avoided, the thermal diffusion source glass can easily be removed by etching and the process is inexpensive and suitably done has high yield. PBr3, POC13 or BBr3 sources may be used. IC manufacturers who have the vision to use the fight mix of implantation and diffusion technologies will have the lowest cost with highest yield. This issue is relevant to competitiveness, especially since implantation capital equipment costs continue to rise rapidly with additional machine sophistication. Implants are also known to channel in statistically chance aligned grains of the gates, giving rise to channeling originated source drain shorts [21]. This problem is avoided by reducing ion energy or increasing gate thickness. Source and drain implants traditionally were done because of self-aligned intent. The lateral straggle was viewed as highly advantageous compared with diffusion from a doped source. However, for the smallest design rules thermal diffusion will have physically shallower junctions than implants when done directly into the silicon [22]. Implants into silicides which are already formed, or into metals which can be reacted subsequently to form silicides will serve as a "diffusion" source from which doping impurities may diffuse into I. REVIEWS
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the silicon without channeling effec~s. This generic approach, e.g. using polysilicon as the diffusion source, has been used for some time to obtain high gain npn bipolar transistors, wherein defect free dopant is diffused into the underlying silicon. Contact resistance has been studied for WSi 2 and TiSi2 by Kobayashi et al. [23]. The profile results do not appear to reflect segregation or pileup at the WSi2-Si interface as indicated by the work of Shone et al. [1]. Diffusion from implanted silicides conceptually eliminates channeling and under processing conditions which results in interface pileup could reduce contact resistance. Implantation directly into silicon may be pursued using As or Sb for n ÷ junctions. Removal of defects can be obtained using RTP while enhancing solubility and limiting diffusion. The metastability of the dopant is an interesting feature, wherein very high temperature short time anneals can enhance solubility only to have precipitation effects occur at lower temperature [24]. Process reversal, using a high temperature spike in time following low temperature BPSG glass flow is a possibility. Implantation of B or B ~ + into bare silicon for shallow junctions depends on whether low enough energy is available or not. If BG+ is selected one needs to have an implant system which avoids charge exchange and B contamination in the BF2+. In a particular process sequence one must qualify junction characteristics for the effects of charge exchange or end of range damage. Preamorphization with BF2+ or B ÷ ions is a possibility to avoid channeling [25] but care must be taken to qualify junction leakage characteristics if end-of-range disorder is important. The extent to which multiple implants can be done with a minimum number of masking steps has been illustrated by the work of Mikoshiba et al. [26]. A CMOS process sequence has been implemented with a total of 7 mask steps, while allowing 6 implant steps. All the features for the IC are also defined by the 7 mask steps while P-well, V.r,, N ÷, V-rp, P+ and P+ well contact implants are all done after gate definition. 4.2. Future use
New applications will tend to emphasize key difficult areas where implantation is well suited specifically for the advancement of submicron technology. Such areas of focus are: contact resistance, hot electron control, latchup control, isolation [1,3], 3-D designs, gate oxide breakdown yield, uniformity and sputtering. The contact resistance needs to be improved for submicron structures, not only the interracial resistance (I2/cm 2), but the body-resistance region connecting the metal contact to silicon under the gate region. For hot electrons, profile control both laterally and vertically is
now recognized to be very important. Advances in latchup using conventional P, N, or twin-tubs will be made using retrograde implants or buried planes of doping. As advanced isolation techniques become more popular, the need to provide controlled doping on the side walls and the lower regions of active silicon (SEG and Trench) become important. For 3-D isolation, where solid phase epitaxy is utilized for lateral growth of single crystal on oxide surfaces, preamorphization may be appropriate. Gate oxide breakdown studies continue to be reported and understanding is gradually improving [27]. Clearly the problem is very complex and depends on details of the target species, layout geometry and so forth. One approach which should give control is the use of a charge monitoring device at the target. This author believes there would be an opportunity to utilize secondary electron density and trajectory for charge neutralization. The secondary electrons produced from any implant during over-scan are "time and space" correlated to the charging beam. The concentration of secondary electrons is also proportional to the charging beam current. Uniformity for very large diameter wafers is important. Wafer rotation during implantation or semicontinuous rotation is possible to improve uniformity when uniformity is limited by linear gradients. Sputtering remains a significant problem [28], and combinations of "dedicated equipment" plus implantation through thin surface filter layers remains a useful approach. However, even in this case diagnostics and solutions to high energy sputtering or high energy beam contamination may be needed.
I thank J.C. Schumacher of the Diamond Cubic Corporation for encouragement and support and M.I. Current for the invitation to do this review.
References
[1] J.Y. Chen, CMOS-The Emerging VLSI Technology, IEEE Circuits and Devices Magazine (March 1986) 16. [2] L.C. Parrillo, R.S. Payne, R.E. Davis, G.W. Reutlinger and R.L. Field, IEDM Tech. Dig. (1980) 752. [3] B. Bastami and C. Lage, CMOS Technology-A Short Course (SILI-CON, Portland, 1986). [4] J.O. Borland, Advanced Epitaxial Processing for Submicron Device Technology, HT-030 (Applied Materials, 1986). [5] 1986 Symp. on VLSI Technology, Digest of Technical Papers (IEEE Electron Devices Soc., San Diego, and Jpn. Society of Appl. Phys.). [6] E. Bassous, H.N. Yu and V. Maniscalco, J. Electrochem. Soc. 123 (1976) 1729. [7] K.Y. Chiu, R. Fang, J. Lin, J.L. Moll, C. Lage, S. Angelo
7".E. Seidel / C M O S process review
and R. Tillman, IEDM 82, section 9.3 (1982) pp. 224-227. [8] J. Hui, T.Y. Chiu and W.G. Oldham, ibidem, section 9.2 (1982) pp. 220-223. [9] T.S. Ogura, W.W. Walker, J.F. Shepard and D.L. Critchlow, IEEE Trans. Electron Devices ED-29 (1982) 590. [10] J.O. Borland, D.N. Schmidt and A.R. Stivers, Low Temperature Low Pressure Silicon Epitaxial Growth and Its Application to Advanced Dielectric Isolation Technology, presented at the 1986 Inter. Conf. on Solid State Devices & Materials (August 1986) Tokyo, Japan. [11] F.C. Shone, K.C. Saraswat and J.D. Plummer, Stanford Electronic Lab., Report ICL 17 (19 July 1984). [12]. R.D, Rung, C.J. Dell'Oca and L.G. Walker, IEEE Trans. Electron Devices ED-28 (1981) 1115. [13] T. Noguchi, Y. Asahi, M. Nakahara, K. Maeguchi and K. Kanzaki, High Speed CMOS Structure with Optimized Gate Work Function, see ref. [5]. [14] K. Yu, R. Chwang, M. Bohr, P. Warkentin, S. Stern and C.N. Berglund, IEEE J. Solid-State Circuits SC-16 (1981) 454. [15] L.K. Wang, Y. Taur, D. Moy, R.H. Dennard, K. Chiong, F. Hohn and P.J. Coane, 0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography, see ref. [51. [16] M. Kinugawa, M. Kakumu and J. Matsunaga, Submicron 3D Surface-Orientation-Optimized CMOS Technology, see
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ref. [5]. [17] J.Y. Chen, IEEE Trans. Electron Devices ED-31 (1984) 910. [18] P.K. Vasudev, private communication. [19] T. Yamaguchi, S. Morimoto, G. Kawamoto, H.K. Park and G.C. Eden, IEDM Tech. Dig. (1983) 522. [20] S. Prussin, J. Appl. Phys. 45 (1974) 1635. [21] T.E. Seidel, Appl. Phys. Lett. 36 (1980) 447. [22] T.E. Seidel, in .VLSI Technology, ed. S.M. Sze (McGraw Hill, New York, 1983) p. 261. [23] N. Kabayashi, N. Hashimoto, K. Ohyu, T. Kaga and S. lwata, Comparison of TiSi, and WSi, Silicided Shallow Junctions for Sub-Micron CMOSs, see ref. [5]. [24] T.E. Seidel, C.S. Pal, D.J. Lischner, D.M. Maher, R.V. Knoell, J.S. Williams, B.R. Penumalli and D.C. Jacobson, Proc. MRS (Nov. 1984). [25] T.M. Liu and W.G. Oldham, IEEE Electron Device Lett. EDL-4 (1983) 56. [26] H. Mikoshiba, A. Yashino and K. Hamano, A Novel CMOS Process Utilizing After-Gate-lmplantation Process, see ref. [5]. [27] Y.M. Hall et al., these Proceedings (Ion Implantation Technology, Berkeley, 1986) Nucl. Instr. and Meth. B21 (1987) 350. [28] L.A. Larson, M.I. Current and C. Healy, Semiconductor Silicon (The Electrochem. Soc., Pennington, N J, 1986) p. 667.
1. REVIEWS
Nuclear Instruments and Methods in Physics Research B21 (1987) 96-103 North-Holland, Amsterdam
CMOS PROCESS REVIEW WITH IMPLICATIONS FOR ION IMPLANTATION T.E. S E I D E L Diamond Cubic Corporation, Oceanside, CA 92054, USA
Ion implantation has been an essential technology for the development of CMOS processes. This paper reviews the origins of the various uses of implantation in CMOS, and discusses present and future applications. There are four parts: i. Design rule history, 2. Discussion of CMOS technologies, 3. Technical issues, 4. Implant usage and implications for CMOS. Key references for this paper are those of Chen [1], Parrillo et al. [2], Bastami [3], Borland [4] and the 1986 Symposium on VLSI Technology [5].
1. Design rule history Fig. 1 shows the leading edge production design rules, plotted against the year of their introduction. The "design rule" is defined as the arithmetic average for minimum feature size of: gate and source and drain region (GASAD), gate, window and contact. In 1986, the leading edge prove-in is about 1.1 ttm [1]. There has been a steady progression from 5.0 to 1.0 gm since 1975 [3], and further progress toward 0.8 and 0.5 #m is expected. Bastami expects 0.3 #m to be in production by 1995 [3]. This presumes that incremental improvement in speed and current performance can be obtained by further scaling, that the thermal limit of 4 k T - 0.1 V will not make room temperature operation poor from noise margin, and that reduced voltage operation is acceptable. Also shown in fig. 1 is the gate oxide thickness which has been scaling linearly with the feature sizes. The integrity of thin gate oxides during implant has been a yield problem for several years, and it is a critical challenge for implant applications. Also shown in fig. 1 are the various major technologies that have been introduced along with the design rule progression. At and above - 2 . 0 gm a LOCOS isolation technology can be used, where oxide step heights are partially recessed and "bird's beak" crosssectional topology gives significant lateral encroachment to the G A S A D region. For - 1 . 0 gm technology a number of innovations are used. They are: recessed FOX isolation [6-8], side-wall oxide on the GOX, direct field implants with little thermal diffusion, silicide contacts, polycide gates, lightly doped drains (LDD) [9], contact filling and retrograde wells. Many of these innovations will be discussed below in the context of implant usage. In order to obtain 0.5 #m feature sizes, it is likely that other isolation techniques will be used and further developed, such as trench isolation, selective epitaxial
growth (SEG), or some form of silicon on insulator (SOI) [10].
2. Discussion of CMOS technologies 2.1. P-weU
The earliest CMOS was implemented in P-well technology. In the early 70s, positive interface charge was a control problem and implantation was not yet fully accepted. With bipolar base diffusion furnaces in operation, and the need to dope the well surface concentration to levels that exceeded the maximum positive interface charge, it was natural to select a P-well approach, which avoided surface inversion. A standard P-well cross section is shown in fig. 2. The diffused P-well suffered from reproducibility and limited the control of the threshold voltages. Since the charge in a P-well is - 1 0 1 3 / c m 2, this is a natural application for implantation. Poly was doped by phosphorus diffusion. This was and is good practice if technically appropriate. There is no gate oxide breakdown issue, glass removal is simple since poly at the doping stage may be unpattemed. Today however one may wish to use different dopants for n and p channel transistors and this suggests implantation. In the oldest P-well processing, the source and drains were diffused from doped glass sources. In retrospect, there were no channeling effects and no gate oxide breakdown problems, however there was a problem of removing the glass after diffusion. If the glass was under etched, glass remained and gave contact problems, if over etched undercutting of the gate oxide would lead to source-gate and drain-gate leakage. Early attempts to use diffusion technology for self-aligned source and drain P-well CMOS were abandoned. Today however, side wall oxide spacer tech-
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niques are well developed. It would seem that an opportunity exists to re-explore the use of diffused boron p+ source and drain junctions. An LPCVD deposited BSG glass would provide a diffused source which has advantages: (i) has no channeling control problems, (ii) has no gate oxide breakdown problem, (iii) low capital and operational cost. However, the disadvantages are: (i) an extra glass removal step, (ii) perhaps an extra masking step, (iii) perhaps an oxinitride layer for the P-channel to avoid diffusion thru the gate oxide. Presently, low energy implantation into the sourcedrain regions where contact silicides already exist would seem to solve the implant channeling problem [11]. The P-well technology also offers opportunity to use high energy boron implants (as opposed to very high energy implants for phosphorus) to effect a retrograde P-well [12], latchup free structure. Threshold adjust implants are also done. The device characteristics of P-well technology result in the better transistor (the NMOS) having degraded performance in comparison to an N-well approach:
junction capacitance is high because of the relatively high P-well doping, the body effect is prominent i.e. transconductance is relatively poor, and hot electron effects are prominent. The NMOS transistor "defaults", it is degraded down towards the PMOS performance [1]. Today's use is mainly for SRAM devices, the NMOS and PMOS are "balanced", the NMOS has good punch thru characteristics and the NMOS has soft error immunity as it is placed in the P-well [3].
2.2. The effect of 4,.,~ offset Before discussing other "well" technologies, the impact of ~ms on the symmetry of thresholds should be briefly discussed. This issue plays an important role on the direction of technology development. Fig. 3 shows the schematic dependence of threshold voltage for NMOS and PMOS transistors as a function of body doping. The model assumes a long channel, uniform doped case. The threshold voltage is: to
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where q~ms is the metal (gate) simiconductor work function, Qi is the interface charge, ~¢ is the fermi-potential and t 0, c0,A 0 are oxide thickness, dielectric constant and area respectively and N b is the body doping. In the schematic a negative ~ms appropriate to phosphorus doped poly is used and t o of - 500 A was used. As the body doping N b is increased thresholds increase as the ~ b for both N and PMOS transistors. However, ~ms creates an offset, so for useful doping concentrations of --1016/cm 3 the VTp and VTn values are significantly I. REVIEWS
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different. V.r, for example may be +0.6 volt, while VTp is - 1 . 6 volt. Even if N b were adjusted the threshold would not reach - 0.6 V, since the dependence on Nb is weak. In the past the problem of addressing the @ms offset was to "threshold adjust" by implanting a surface layer of charge such that a voltage shift of the desired amount would be obtained: Qs -= Co AVT, where Qs is the ion implant dose. If the threshold implant is not very shallow, high subthreshold leakage degrades device performance. Approaches to obtain symmetric threshold characteristics include selection of alternate gate materials such as MoSi 2 or other metals or metal silicides. However, selective implant doping the gate poly (n-type poly for NMOS and p-type poly for PMOS) could be used. N
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One limiting problem with P-well technology at small design rules is avalanche effects in the NMOS transistor. Charge injected into the gate oxides causes gate instabilities or gate reliability problems. This is particularly true with small design rules - 1.0 #m, when trying to maintain high supply voltages, i.e. 5 V. It was recognized that the NMOS avalanche effects could be reduced by going to an N-well structure, thus reducing the electric field for the field-sensitive NMOS transistor [14].
Since the N-well structure is built on p substrate material, IC houses which already have established N M O S technology could readily transfer all process technology and simulations from NMOS to CMOS by
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dropping the NMOS transistor into the CMOS structure in a transparent way. The NMOS transistor is highly optimized. Body doping is relatively low, junction capacitance is small, body effect on transconductance is small and the avalanche effects are small. However, even the N-well approach does not save one from needing to further reduce the electric field near the drain of the NMOS transistor. The use of lightly-doped drains (LDD), spreads the field out and allows relatively higher voltages to be applied for a given design rule. This is shown schematically in fig. 5. At the lowest design rules - 0.3 /~m one will need LDD structures even for the PMOS transistor. The substrate for N-well technology is p - or pp+. Excellent intrinsic gettering has been obtained with pp ÷ substrate systems which is compatible with a CMOS thermal process sequence. The use of N-well technology is expected to become pervasive, with NMOS rich circuits, logic, dynamic memories, and high voltage EPROMS [1,3]. Wang et al. [15] have demonstrated a 0.5 /~m gate (MOS) in N-weU technology. They used LDD-N ÷, phosphorus-arsenic junctions with ~ , - 0.15/~m and a preamorphized boron implant sequence to obtain ~p 0.16/~m.
Applications around 0.5-1.0 ~m design rules would seem to appeal to twin-tub usage since scaling down requires small space charge widths in the source-drain region. One has to dope-up the tub regions anyway in order to avoid punch thru. Use of twin-tub implants moves the burden for doping control from the wafer manufacturer to the implant-IC manufacturer. However, if very uniform substrate doping becomes available, then the IC manufacture could be less expensive with single-well processing. Although the n + to p+ spacing is improved by using self-aligned chart stops in the twin-tub process, there is necessarily compensation of the chart stop doping at the p-tub to n-tub intersection. In this region the surface is easily inverted and gives rise to a layout loss proportional to the compensated region width. This problem naturally suggests a trench isolation solution. Trench isolation is very compatible with twin-tub technology because the problem of side wall inversion of the trench is avoided by the high doping required in the tubs for the sub-micron design rule case. Today's twin-tub technologies use implantations rather pervasively: N-tub, P-tub, Chanstops, VT adjusts, poly or polycide, p+ and n + source and drains. Applications for twin-tub utilizations could follow the guide lines mentioned above for N and P-wells, NMOS rich circuits, and DRAMs could have N-well character with p or pp+ substrates, while SRAMs could have P-well character with n or nn + substrates. There may be some reluctance to transfer older design rule devices into new substrate choices since the new engineering may cost more than the value added to the device performance [1,3]. Twin-tub technology has been implemented using a sub-micron 3D-surface orientation for the optimized PMOS mobility by Kinugawa et al. [16]. The surface hole mobility for 110 surfaces is 1.5 × the mobility for 100 surfaces. By putting the PMOS transistor on the 110 side wall, higher mobility and space saving are obtained simultaneously. See fig. 7. Threshold control is not discussed and junction leakage is reported to be only marginally worse than conventional PMOS transistors.
2.4. Twin-tub
Although twin-tub technology was introduced in 1980 by Parrillo et al. [2] with 3.0 ~m design rules, both transistors NMOS and PMOS have high body doping and therefore high Cj, body effect and susceptibility to avalanche effects. One driving force for twin-tub acceptance is complete flexibility of process attributes: both threshold voltages can be independently controlled, channel stops (high doping under the field oxide to prevent inversion) can be independently controlled, and one is free to choose either nn + , n - , p - or pp + substrate systems as dictated by issues described under N-well and P-well descriptions. See fig. 6.
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Limitations in the performance of CMOS include latchup, high junction capacitance Cj, body effect on transconductance, and n+p + spacing. By using a tub implantation of high or very high energy ions, one gets a buried maximum concentration which will lower the vertical bipolar gain of the bipolar transistor placed in that tub [12]. The lateral gain of the transistor placed in the substrate can also be reduced. Further, the high conductivity of the sub-tub region will shunt bipolar currents away from the gain connected SCR loop causing latchup. Thus retrograde well approaches can give excellent latchup protection. This is done both by the bipolar gain reduction and current shunting mechanisms. Although higher tub doping is required to obtain the latchup protection, the use of MeV implants increases the doping where it is needed and not near the surface. Thus the latchup protection is provided without impacting the surface MOS characteristics, such as C~ or the body effect. In twin-tub technology, the compensated dead layer width can be reduced since high doping can be placed at the tub intersection by the retrograde p and n implants. This can help the n+p + spacing. When retrograde doping is used as an "add on" to twin-tub technology, the term QUAD-well has been coined [17]. The retrograde approach is an outstanding technical triumph for implantation in CMOS usage. However, one faces the issues of cost and question of the reliability of operation for MeV implant equipment in a production environment. 3. Technical issues 3.1. Hot electrons
The avalanche coefficient is much greater for electrons than holes in silicon. Thus, for a given electric
field strength the multiplication of carriers is relatively easy for n ÷ drains, giving rise to electrons which transport to the gate oxide and holes which are injected into the substrate. At somewhat higher electric field strengths even the p+ drains will exhibit avalanche multiplication (e.g. for 0.3/~m design rules) [18]. The excess charge will result in drifts or instabilities in the threshold voltages and also in the transistor's transconductance. The technological solution to this problem has been through the use of lightly doped drains (LDD), where the n + junction is engineered to be graded: nn +. The electric field is then spread out into the bulk-tub and into the drain region, allowing relatively high supply voltages with lower peak electric fields. Good control of the doping profiles are needed in order to get good turn on characteristics and to limit the reduction in MOS transistor gain gm from the added series resistance of the n region. The LDD solution appears not to be completely satisfactory and complete recipes are not yet in the open literature [1]. This may be a special opportunity for excellent interfacing between implant and device technologists. 3.2. Isolation
CMOS has used, for the most part, junction isolation. This is typified by tub/substrate or tub to tub junctions in single-well and twin-tub technologies respectively. The field oxide serves to stand off voltages on signal rails. Today's advanced technology uses a recessed field oxide (to give topological patterning advantage) while employing retrograde wells to minimize the dead space in the tub to tub compensated region. Another isolation approach would employ a trench combined with twintubs. Trench isolation can be used very effectively if the trench reaches down to a heavily doped plane (which could be implanted) or to a heavily doped epi substrate [10,19]. The capability of trench technology, combined with MeV implant may obviate the need for expensive epi. This choice will be decided on yield, performance and cost as the field matures. Beyond the trench or trench refill approach, one may look to selective epi growth as another alternative. The two isolation approaches are shown in fig. 8. The trench refill makes cuts in the substrate material, providing relatively narrow regions to be refilled down with SiO2, while the selective epi growth (SEG) makes cuts in an oxide layer, leaving behind relatively narrow oxide regions-the silicon epi is then grown up on the underlying substrate. In the example shown the trench refill is done into p - bulk with an MeV p+ implant. This could provide retrograde isolation, latchup protection, limited alpha particle immunity, and partial side wall chan stopping.
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3.3. Latchup
Latchup immunity can be provided basically by bipolar gain t-spoiling or by shunting bipolar currents away from the SCR circuit or by dielectric isolation, DI [1,3]. Examples of t-spoiling include retrograde wells, Schottky source-drain contacts and gold or damage lifetime killing. The Schottky approach also gives high leakage and rules out DRAM application, but would be suitable for logic. The gold or damage lifetime killing has not found acceptance because of control problems and limited application use. Examples of approaches which limit latchup by current shunting are: retrograde doping, epi substrate (p+ or n +) doping, very high energy uniform doped plane doping and guard ring design approaches. Examples of dielectric isolation are: Trench, SEG and SOI. The Trench and SEG were described above. One example of SOI which will reduce the n+p + spacing to near absolute minimum and give latchup immunity would be where the complementary transistor is placed on the field oxide. A recessed field oxide would be most appropriate to allow good laterial solid phase epitaxy. A deposited polysilicon film can be made amorphous by implantation and seeded in the drain region of the primary transistor and solid phase epitaxy can grow laterally on the oxide. The complementary transistor is fabricated in the laterally grown solid phase epitaxy material.
4. Summary of implant usages for CMOS 4.1. Present and past use
This topic is divided in low dose and high dose applications. For low doses we have: N and P tub, N and P tub chan stops, N and P tub retrogrades and VTP and VT~ threshold adjusts.
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Since phosphorus and other n-type dopants are segregated ahead of an oxidizing interface and since oxidation often follows implantation to play a role in subsequent masking, the N implants often are sequenced prior to P implants [2]. B o r o n - i f oxidizedwould disperse through the oxidized layer, the amount of boron kept in the silicon is then dependent on the exact oxidation conc[itions thus giving a process control problem. Both tub implants and chan stops can be done using self-aligned LOCOS type processing where one mask operation per two implant steps is utilized. Retrograde implants require thick, often deposited layers to give good stopping effects. Deposited oxides, thick photo resist and dense deposited metal layers are useful as high energy masking materials. The tub doses and chan-stop doses may be high enough to result in stacking fault nuclei if annealed directly in an oxidizing ambient. One practice is to anneal using a neutral/oxidizing sequence where the neutral first dissolves the SF nuclei and the desired oxidation is still obtained [20]. For VT adjusts, one wants low energy, close to the surface implants, annealed with very limited thermal diffusion-an opportunity for implantation plus rapid thermal processing (RTP). For high doses one has: poly silicon or gate doping, source and drain (n ÷ and p+) and the lightly doped regions (LDD) of source and drains. Doping the gates can in many cases be done with diffusion technology. Here the threat of gate oxide damage is avoided, the thermal diffusion source glass can easily be removed by etching and the process is inexpensive and suitably done has high yield. PBr3, POC13 or BBr3 sources may be used. IC manufacturers who have the vision to use the fight mix of implantation and diffusion technologies will have the lowest cost with highest yield. This issue is relevant to competitiveness, especially since implantation capital equipment costs continue to rise rapidly with additional machine sophistication. Implants are also known to channel in statistically chance aligned grains of the gates, giving rise to channeling originated source drain shorts [21]. This problem is avoided by reducing ion energy or increasing gate thickness. Source and drain implants traditionally were done because of self-aligned intent. The lateral straggle was viewed as highly advantageous compared with diffusion from a doped source. However, for the smallest design rules thermal diffusion will have physically shallower junctions than implants when done directly into the silicon [22]. Implants into silicides which are already formed, or into metals which can be reacted subsequently to form silicides will serve as a "diffusion" source from which doping impurities may diffuse into I. REVIEWS
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the silicon without channeling effec~s. This generic approach, e.g. using polysilicon as the diffusion source, has been used for some time to obtain high gain npn bipolar transistors, wherein defect free dopant is diffused into the underlying silicon. Contact resistance has been studied for WSi 2 and TiSi2 by Kobayashi et al. [23]. The profile results do not appear to reflect segregation or pileup at the WSi2-Si interface as indicated by the work of Shone et al. [1]. Diffusion from implanted silicides conceptually eliminates channeling and under processing conditions which results in interface pileup could reduce contact resistance. Implantation directly into silicon may be pursued using As or Sb for n ÷ junctions. Removal of defects can be obtained using RTP while enhancing solubility and limiting diffusion. The metastability of the dopant is an interesting feature, wherein very high temperature short time anneals can enhance solubility only to have precipitation effects occur at lower temperature [24]. Process reversal, using a high temperature spike in time following low temperature BPSG glass flow is a possibility. Implantation of B or B ~ + into bare silicon for shallow junctions depends on whether low enough energy is available or not. If BG+ is selected one needs to have an implant system which avoids charge exchange and B contamination in the BF2+. In a particular process sequence one must qualify junction characteristics for the effects of charge exchange or end of range damage. Preamorphization with BF2+ or B ÷ ions is a possibility to avoid channeling [25] but care must be taken to qualify junction leakage characteristics if end-of-range disorder is important. The extent to which multiple implants can be done with a minimum number of masking steps has been illustrated by the work of Mikoshiba et al. [26]. A CMOS process sequence has been implemented with a total of 7 mask steps, while allowing 6 implant steps. All the features for the IC are also defined by the 7 mask steps while P-well, V.r,, N ÷, V-rp, P+ and P+ well contact implants are all done after gate definition. 4.2. Future use
New applications will tend to emphasize key difficult areas where implantation is well suited specifically for the advancement of submicron technology. Such areas of focus are: contact resistance, hot electron control, latchup control, isolation [1,3], 3-D designs, gate oxide breakdown yield, uniformity and sputtering. The contact resistance needs to be improved for submicron structures, not only the interracial resistance (I2/cm 2), but the body-resistance region connecting the metal contact to silicon under the gate region. For hot electrons, profile control both laterally and vertically is
now recognized to be very important. Advances in latchup using conventional P, N, or twin-tubs will be made using retrograde implants or buried planes of doping. As advanced isolation techniques become more popular, the need to provide controlled doping on the side walls and the lower regions of active silicon (SEG and Trench) become important. For 3-D isolation, where solid phase epitaxy is utilized for lateral growth of single crystal on oxide surfaces, preamorphization may be appropriate. Gate oxide breakdown studies continue to be reported and understanding is gradually improving [27]. Clearly the problem is very complex and depends on details of the target species, layout geometry and so forth. One approach which should give control is the use of a charge monitoring device at the target. This author believes there would be an opportunity to utilize secondary electron density and trajectory for charge neutralization. The secondary electrons produced from any implant during over-scan are "time and space" correlated to the charging beam. The concentration of secondary electrons is also proportional to the charging beam current. Uniformity for very large diameter wafers is important. Wafer rotation during implantation or semicontinuous rotation is possible to improve uniformity when uniformity is limited by linear gradients. Sputtering remains a significant problem [28], and combinations of "dedicated equipment" plus implantation through thin surface filter layers remains a useful approach. However, even in this case diagnostics and solutions to high energy sputtering or high energy beam contamination may be needed.
I thank J.C. Schumacher of the Diamond Cubic Corporation for encouragement and support and M.I. Current for the invitation to do this review.
References
[1] J.Y. Chen, CMOS-The Emerging VLSI Technology, IEEE Circuits and Devices Magazine (March 1986) 16. [2] L.C. Parrillo, R.S. Payne, R.E. Davis, G.W. Reutlinger and R.L. Field, IEDM Tech. Dig. (1980) 752. [3] B. Bastami and C. Lage, CMOS Technology-A Short Course (SILI-CON, Portland, 1986). [4] J.O. Borland, Advanced Epitaxial Processing for Submicron Device Technology, HT-030 (Applied Materials, 1986). [5] 1986 Symp. on VLSI Technology, Digest of Technical Papers (IEEE Electron Devices Soc., San Diego, and Jpn. Society of Appl. Phys.). [6] E. Bassous, H.N. Yu and V. Maniscalco, J. Electrochem. Soc. 123 (1976) 1729. [7] K.Y. Chiu, R. Fang, J. Lin, J.L. Moll, C. Lage, S. Angelo
7".E. Seidel / C M O S process review
and R. Tillman, IEDM 82, section 9.3 (1982) pp. 224-227. [8] J. Hui, T.Y. Chiu and W.G. Oldham, ibidem, section 9.2 (1982) pp. 220-223. [9] T.S. Ogura, W.W. Walker, J.F. Shepard and D.L. Critchlow, IEEE Trans. Electron Devices ED-29 (1982) 590. [10] J.O. Borland, D.N. Schmidt and A.R. Stivers, Low Temperature Low Pressure Silicon Epitaxial Growth and Its Application to Advanced Dielectric Isolation Technology, presented at the 1986 Inter. Conf. on Solid State Devices & Materials (August 1986) Tokyo, Japan. [11] F.C. Shone, K.C. Saraswat and J.D. Plummer, Stanford Electronic Lab., Report ICL 17 (19 July 1984). [12]. R.D, Rung, C.J. Dell'Oca and L.G. Walker, IEEE Trans. Electron Devices ED-28 (1981) 1115. [13] T. Noguchi, Y. Asahi, M. Nakahara, K. Maeguchi and K. Kanzaki, High Speed CMOS Structure with Optimized Gate Work Function, see ref. [5]. [14] K. Yu, R. Chwang, M. Bohr, P. Warkentin, S. Stern and C.N. Berglund, IEEE J. Solid-State Circuits SC-16 (1981) 454. [15] L.K. Wang, Y. Taur, D. Moy, R.H. Dennard, K. Chiong, F. Hohn and P.J. Coane, 0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography, see ref. [51. [16] M. Kinugawa, M. Kakumu and J. Matsunaga, Submicron 3D Surface-Orientation-Optimized CMOS Technology, see
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ref. [5]. [17] J.Y. Chen, IEEE Trans. Electron Devices ED-31 (1984) 910. [18] P.K. Vasudev, private communication. [19] T. Yamaguchi, S. Morimoto, G. Kawamoto, H.K. Park and G.C. Eden, IEDM Tech. Dig. (1983) 522. [20] S. Prussin, J. Appl. Phys. 45 (1974) 1635. [21] T.E. Seidel, Appl. Phys. Lett. 36 (1980) 447. [22] T.E. Seidel, in .VLSI Technology, ed. S.M. Sze (McGraw Hill, New York, 1983) p. 261. [23] N. Kabayashi, N. Hashimoto, K. Ohyu, T. Kaga and S. lwata, Comparison of TiSi, and WSi, Silicided Shallow Junctions for Sub-Micron CMOSs, see ref. [5]. [24] T.E. Seidel, C.S. Pal, D.J. Lischner, D.M. Maher, R.V. Knoell, J.S. Williams, B.R. Penumalli and D.C. Jacobson, Proc. MRS (Nov. 1984). [25] T.M. Liu and W.G. Oldham, IEEE Electron Device Lett. EDL-4 (1983) 56. [26] H. Mikoshiba, A. Yashino and K. Hamano, A Novel CMOS Process Utilizing After-Gate-lmplantation Process, see ref. [5]. [27] Y.M. Hall et al., these Proceedings (Ion Implantation Technology, Berkeley, 1986) Nucl. Instr. and Meth. B21 (1987) 350. [28] L.A. Larson, M.I. Current and C. Healy, Semiconductor Silicon (The Electrochem. Soc., Pennington, N J, 1986) p. 667.
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