Application of ion implantation in submicron CMOS processes

9

Nuclear Instruments and Methods in Physics Research B55 (1991) 9-16 North-Holland

Application

of ion implantation

K.H. Kiisters, H.M. logoff Siemens AG, Otto-Hahn-Ring

in subticron

CMOS processes *

and H. Cerva

6, 8000 Mikehen

83, Germany

Ion implantation is an essential technology for the development of submicron CMOS processes. The most important applications of ion implantation in a CMOS process are: (1) well formation, (2) threshold voltage control of MOS active and parasitic transistors, (3) drain engineering of transistor, (4) fo~ation of n+, p+ areas, (5) breakup of native oxides by ion mixing and (6) doping of 3-dimensional structures lie DRAM cells. Recent developments in these topics, v&ich are reviewed in this paper, include optimization work based on conventional implantation technology as well as new implantation techniques like MeV implantation, parallel-scan implantation and large-tilt-angle implantation.

1. Introduction Ion implantation is used for most doping steps in VLSI. The scaling of CMOS devices into the deep submicron range sets new challenges for the optimization of implantation technology. The design rules of 16 Mbit DRAMs, which are now in pilot production, have moved down to 0.5-0.6 urn. All impurity doping steps (see fig. 1) have to be optimized to improve device performance, particularly isolation and transistor performance. The development of 3-dimensional DRAM cells requires the implantation doping of 3-dimensional structures. This paper reviews the most important applications of ion implantation in modern CMOS processes and the present work on process optimization concerning impurity doping and new implantation techniques in CMOS processes. Furthermore, defect problems in CMOS processes due to implantation damage are discussed.

controlled leakage (punchthrou~} both in active and isolation devices. Also vertical puncht~ough between devices in a well with opposite doping than the substrate and the substrate has to be avoided. In DRAMS with depletion-type trench capacitors, especially high p-well doping levels are necessary to suppress punchthrough between adjacent trenches [l] and to reduce the soft error rate due to alpha particles [Z]. The latch-up problem inherent in CMOS technology has to

90

91

92

93

94

I Design Rule IRml

0,s

0.3

Technolsgy: fwnceming Implantation) l

Wellfarmatian~. Conventional Retrograde-wells

I‘) __________

LCCCS (high E channel stopper shallow -_--a

Trenrh Isolation (tilt angle

I2,

2. Well formation -_____ drain engineering

In CMOS processes adjustment of bulk doping is usually performed by the formation of n- and p-wells. When designing the well process, several device issues have to be taken into account. Surface concentration has to be high enough that sufficient isolation for active and passive devices can be maintained. Since this is not always the case, additional shallow implantations such as channel implants for active devices and field implants for isolation areas may be necessary. Bulk concentration needs to be at a level to inhibit non-surface-

* Invited paper,

LDD Fully overlapped

LD

(tilt

angle I 2,

3D transisor -----_-_--_-_--_+

Fig. 1. Technology trends in ion implantation.

0168-583X/91/$03.50 0 1991 - Elsevier Science Publishers B.V. (worth-Holland)

1. OVERVIEWS

10

K.H. Kiisters et al. / Jon implantation in submicron CMOS processes

Fig. 2. Simulated

2D doping

profile of deep n-well, and counter-doped

be minimized by designing wells with low sheet resistances and minimum /? for the parasitic bipolar transistors. P- and n-wells can be fabricated in a fairly straightforward fashion using two masking steps and low implantation energies. To achieve the required well depths, drive-in steps are performed at high temperature (11501190 * C). Several hours are needed for DRAMS with trench capacitors because the doping concentration at the trench bottom in 4 urn depth has to be more than 1016 cmp3. In order to reduce the mask count, self-adjusting technologies have been suggested [3] employing a local oxidation process. An even simpler approach is an unmasked p-well impl~tation followed by the implantation of the n-well in masked areas, in which the n-doping counterdopes the p-well, creating a net donor concentration between 5 X 101” and 10” cm-j [4]. 2D simulation of the doping profile reveals the advantages of this well concept (fig. 2). Because the n-well is sup~imposed on a highly doped p-well background, well pn junctions are fairly abrupt both in the lateral and in the vertical direction. The dimension of regions with low net doping (less than 1016 cmp3 net concentration) is considerably smaller than in conventionally

n-well.

doped wells (0.6 urn vs 2 urn). ‘This permits tighter spacing because no isolation design rnles for n+-pc area is wasted with lowly doped well boundaries. The dependence of isolation properties of the n-well on separation between well-edge and p+ junction are shown in fig. 3. The counterdoped n-well even beats a very shallow n-well which was driven in with ~nimum thermal budget. Well parameters are listed in table 1. Hightemperature drive-in steps can be avoided, if higher implantation energies are used. MeV implantation has left the development phase and is now entering production [5-S]. Besides low-temperature processing, an additionial advantage consists of being able to make a retrograde doping profile, in which bulk concentration is much higher than surface concentration. Using this technology, highly doped layers can be made underneath field oxide for improved isolation and be made underneath active devices for reduced susceptibility to latch-up [S]. But also conventional or counterdoped well technologies can produce good results with respect to latch-up 141. Fig. 4 shows latch-up data for substrate-triggering of p-doped wafers (refer to refs. [g-11] for description of characterization method). This trigger mechanism is dominated by the shunt resistance of the p-substrate and the p-well. Using thin epi can improve latch-up trigger currents by several orders of magnitude. 16 Mbit DRAMS with deep p-well have a performance equivalent to 8 to 14 pm epi-substrate. Trigger currents for well triggering are shown in fig. 5. This trigger mechanism is dominated by the shunt

Table 1 Well parameters

Fig. 3. Lateral isolation of n-well. Threshold voltages of FOXtransistor for V,, = 0.25 V and V,, =lO V at 1 PA/km.

Well depth [pm] ~tdiffus~on from masks edge [pm] Vert. d, ~1x10~ [am] Lat. d, -z 1 x lOI [pm]

Deep n-well

Shallow n-well

Counterdoped n-well

4.0

1.5

3

3.5 2.0 1.4

2.0 0.9 0.8

0.5 0.6 0.5

K.H. Ktiters ltrigger

et al. / Ion implantation

in submicron CMOS processes

(A/urn) -0”

1”

B”’ ROE-05

Lit. retrograde

t

l.OE-04

deep N-well

N-well

I Lit. Bum epi y” Lit. 14um epi 0

l.OE-05

n

n .a Lit. bulk

-a

D

l.OE-06’ 0

1

2

3

4

n+ to p+ separation

Fig. 4. Latch-up:

resistance ventional

6

of the n-well.

Well

trigger

I

I

7

3

1

2

currents

3

4

5

n+ to p+ separation

between

Fig. 5. Latch-up:

6

7

6

(pm)

weII triggering. Comparison data and ref. [PI.

between own

for con-

are are not much below those of

retrograde

0

(vrn)

substrate triggering. Comparison own data and ref. [8].

deep n-wells

MeV-implanted

5

n-wells down to 4 Pm nf-p+

spacing. Figs. 4 and 5 compare own data with results taken from the literature [8]. Is is evident that carefully tuned conventional well technologies can be stretched to realize n+-p+ spacings of less than 4 pm, which is sufficient for 0.5 pm CMOS processes. For spacings less than 2 pm, however, thin (2 l.trn) epi-substrate and retrograde wells will be required.

3. Threshold voltage control, MOS active and parasitic transistors Conventional poly-buffered LOCOS isolation can still be used up to the 16 Mbit DRAM integration level [12,13]. Maintaining oxide thicknesses of more than 200 nm becomes difficult with processes where isolation widths of less than 0.7 pm are required. Satisfactory electrical results are shown in fig. 6 demonstrating that

neither turn-on of the parasitic field-effect transistor nor punchthrough between adjacent source/ drain areas occurs down to 0.7 pm separations. Due to the different segregation behavior of boron and phosphorus during oxidation, boron concentration underneath the field oxide is very low whereas phosphorus piles up on the silicon side of the interface. For this reason channel-stop implantation is usually not required for PMOS isolation areas. To achieve satisfactory isolation in NMOS areas, additional channel-stop implants are required. If this implantation is carried out before LOCOS growth, lateral outdiffusion will increase the doping concentration in narrow active areas causing higher threshold voltages. This narrow width effect can be eliminated by performing the channel-stop implantation after the LOCOS growth at higher energies (180 keV). Boron atoms at this energy penetrate 400 to 600 nm field oxide. Isolation properties of both doping techniques are compared in fig. 6. The narrow-width effect (fig. 7) V!aunch (VI

f4

at IpA/um

12

2 0 0

0.2

0.4

0.6

0.8

1

FOX Length

Fig. 6. Threshold voltage (a) and punchthrough (b) of parasitic FOX-transistor.

1.2 1.4 (urn)

1.6

1.8

2

Isolation can be maintained down to 0.7 pm. I. OVERVIEWS

12

K.H. Kiisters et al. / Ion implantation

t (V) +

“M,

0

1.5

1

0.5

Width

2

3

2.5

Iurn)

Fig. 7. Comparision of NMOSFET narrow-width effect for two channel-stop implantation techniques: w implantation before LOCOS growth, * implantation after LOCOS growth. L gate = 0.8 pm, V,, = 3.5 V and V,, = - 1.5 V.

disappears

almost

completely

and

transistors

with

ac-

Even smaller LOCOS isolation can be made when the pad oxide is scaled down further. A value of 0.5 urn can be acheived when a 5 nm pad oxide under a 50 nm poly-Si film is used [13]. For increased integration densities like 64 Mbit DRAM, shallow trench isolation can be introduced. Isolation properties have to be adjusted by tiltangle implant of trench sidewalls [15,16]. tive

area

width

of 0.25

pm

can

be realized

The performance of submicron transistors depends on the impurity profile in the vicinity of the drain regions. LDD transistors reduce the peak electric field in the channel and thus reduce hot electron degradation of NMOS transistors. Gate control over n--LDD re-

drawing

of (a) LDD sistor.

gions is crucial for reliability improvement. Therefore the shadowing of the LDD implantation at the gate edge, which gives rise to asymmetric transistors with nonoverlap between gate and source/drain, has to be avoided by rotating the wafers at the LDD implantation [17]. Optimization of deep submicron (L, = 0.25 pg) transistor reliability has led to fully overlapped LDD structures (FOLD) (fig. 8) [l&19]: The LDD implant is performed at tilt angles up to 60 O. In addition to reliability gains, current drive capability is increased due to the higher conductivity of the fully overlapped n- region. This structure is also suitable to suppress gate-induced drain leakage [20] which sets constraints on deep submicron transistors with ultrathin (< 10 nm) gate oxides. Fully overlapped LDD structures can also be achieved with conventional implanters (inverse T-gate process) without large-tilt-angle end stations; however, this is achieved at the cost of enhanced process complexity [21,22].

[14].

4. Drain engineering of transistors

Fig. 8. Schematic

in submicron CMOS processes

and (b) FOLD

tran-

5. n+-, p-areas junction formation A scaled CMOS technology requires shallow source/ drain junctions. Junction depth for 0.5 pm CMOS technology is approaching 100 nm or less to prevent punchthrough and short-channel effects. Shallow implanted profiles can easily be achieved for As-doped n+ layers. However, shallow B-doped p+ profiles can only be realized if the channeling of B+ ions is prevented. Complete elimination of channeling is possible by preamorphization using a Ge or Si implant prior to B+ or BF,+ implantation [23,24]. Also preamorphization by implantation of F [25] or Sb [26] has been reported. The integration of shallow implanted layers in a CMOS process requires careful work on the control of implantation damage [27]. Defects near the shallow source/ drain junctions are detrimental to device performance. The thermal budget for defect anneal has to be kept minimal because of dopant redistribution. Therefore, control of implantation damage is an important concern of process flow and optimization of implantation parameters. Process options for shallow pt layers without defects include the following. _ Use of rather thin preamorphized layers. The annealing time to remove damage is decreasing as the proximity to the surface increases: the shallower the damage, the lower the annealing temperature can be. The use of an amorphized layer as thin as 40 nm is combined with low-energy BFC (fig. 9) [24] or verylow-energy B implantation [2X] _ Outdiffusion from TiSi and CoSi using RTA annealing, which has been intensively investigated [29-331. Different approaches using ion implantation before or after silicide formation are reported. Process prob-

K.H. Kiisters et al. / Ion implantation

lems arise from low dopant concentration at the silicide/Si interface, which have been observed, e.g., for B and the TiSi,/Si interface [30]. B tends to precipitate at the TiSi,/SiO, interfaces and to form metal/dopant compounds with Ti. Outdiffusion of B into Si is rather poor (fig. 10). The lack of pileup of boron at the TiSiJSi interface makes ohmic contact formation difficult. Process optimization for higher surface dopant concentration at the TiSi,/Si interface therefore requires high implant doses, an implantation range as close as possible to the interface, and short-time drive in RTA. Results for the outdiffusion of dopants from CoSi, indicate that CoSi, is favourable compared to TiSi. Shallow junctions with high B concentration at the CoSiJSi interface were reported [32]. Formation of detrimental defects is not only critical for p+ layers, but also for nt layers. Here, defects at mask edges are found after the crystallization of an amorphous layer [34,35]. These defects occur during a typical CMOS process. The high-dose source/drain implantation is performed self-aligned to the gate. The gate/LDD spacer acts as an implantation mask. At the mask edge the amorphous/crystalline interface is curved; solid-phase epitaxial regrowth (fig. 11) proceeds now into both vertical and lateral directions, simultaneously. Partial crystallization of the amorphous layer reveals a notch on the amorphous/crystalline (a/c) interface, which is shown to be due to the different epitaxial regrowth rates on the various lattice planes. On further annealing, defects are generated when the crystallization fronts on both sides of the notch join. These defects are inevitable if an amorphous zone has sharply curved a/c interfaces. During further processing these defects are in a stress field. Fig. 12 shows a dislocation nucleated at the mask edge defect below a stress-inducing thick

a

1022,

,

, EF2

,

,

15keV,2x1015cm-2

I

in submicron

CMOS processes

0.0

0.1

13

0.2

0.3pm0.4

0.5

( 6

Depth ---+ Fig. 10. B doping profiles after outdiffusion from TiSi,, taken from ref. [30] (B in mono-%).

data

nitride layer; here a strong leakage current can be observed. Process options to avoid these defects at mask edges, which occur only in As-implanted source/drain regions of N channel transistors, are: use of less steep implantation sidewalls to achieve a smoothly rounded a/c interface; however, this may conflict with the trend of increasing integration density; use of only n- doping in stress-sensitive regions; diffusion of dopants from doped silicide on Si into Si substrate, to avoid any implantation damage in the substrate.

6. Ion mixing Ion mixing techniques are used for silicide formation and for poly-Si/Si contacts. The effect of an interface native oxide can largely be suppressed by implanting

1

b F

E s

pre-amorphizalion

Depth

(rim)

Depth

(nm)

Fig. 9. Doping profiles of BF,+-implanted layers with different thicknesses of the preamorphized layer. Data taken from ref. [24]. (a) As-implanted B profiles for preamorphized and crystal samples. The arrows indicate the a/c interface positions. (b) Annealed B profiles for preamorphized samples formed by Si+ and Get implantations, I. OVEiCVIEWS

14

Fig. 11. Defect formation

K. H. Kiisters et al. / Ion implantation

in submicron CMOS processes

during crystallizationof an amorphousAs-implantation layer near a mask edge. (a) As-implanted, (b)-(d) regrowthafter: (b) 500 o C, 30 ruin, (c) 500 o C, 190 ruin, (d) 900 ’ C, 60 min.

ions through the deposited-met~/poly-Si layer into the interface 1371. The ion beam mixing breaks up the oxide at the interface. For silicide processes it has been observed that interface mixing (e.g., by Si+ implantation or implantation of dopants) enhances the Ti-Si or Co-Si nucleation rate and results in a smooth silicide surface [38]. Furthermore, resistivity uniformity is enhanced. EIowever, junction problems have been reported, e.g., because of mixing of Co into the substrate and loss of dopants during silicide formation. Ion mixing also serves to reduce the contact resistance of poly-Si/Si contacts [39]. Low specific contact resistivities in the 20 Stpm* range are found if the energy is high enough that As+ ions reach the contact interface. The native oxide is broken up and poly-Si regrowth on Si substrate is epitaxial during subsequent annealing. Also Sif ions can be used to break the native oxide and achieve low values of contact resistance after low-energy As + ion implantation. Using Si implantation, the degradation of the contact doping profile can be avoided. Wowever, ion mixing of contact areas leads to an amorphous zone in the Si substrate, which may

have sharply curved a/c interfaces below the mask edges. During regrowth of the amorphous zones the defect formation at contact borders again becomes an important concern for process optimization (see section 5).

7. Trench capacitor sidewall doping As the level of integration increases, devices have to be formed below the Si surface or above it. DRAM cells of beyond 1 Mbit integration density (see ref. [40]) are based on S-dimensional cell structures such as stacked capacitors and trench capacitors. Fig. 13 shows a cross section of a 16-Mbit-DRAM trench cell. The doping of a trench capacitor requires implantation of ions into vertical sidewalls of trenches, whose aspect ratio may be as high as 10. The angle of incidence of the ion on the trenches has to be strictly controlled, therefore implanters with parallel beam scan have to be used [41-431. To avoid shadowing effects, rotational implantation is necessary. A major concern about trench sidewall doping is con-

K.H. Kiisters et al. / Ion implantation

in submicron CMOS processes

15

trollability and uniformity. The ion dose delivered to trench sidewall/ trench bottom depends, e.g., on the implantation angle and energy, which determine the reflection on ions from the sidewalls, and on the trench geometry. The experimental determination of implantation profiles is cumbersome and time-consuming. Computer simulation is used to obtain suitable implantation conditions [4447]. In simulation studies, the 3-dimensional Monte Carlo technique is used to simulate the trajectories of particles and the final doping profile. To achieve uniform trench doping, optimization of the ion incidence angle is necessary. The optimized ion incidence angle is given by the condition that the ion beam, coming from the mask edge (upper trench edge) is

Fig. 13. Cross section of 16 Mbit DRAM trench cell.

injected into the opposite bottom comer of the trench ]441.

8. Summary The application of ion implantation in advanced CMOS processes has been discussed. Recent developments include optimization work based on conventional implantation techniques as well as the application of advanced techniques like - MeV implants (retrograde well), _ tilt-angle implantation with parallel beam scan (3-dimensional structures, FOLD transistor). For all implantation applications in VLSI, defect-related problems will need more attention to enable the production of chips with increased packing density at high yield: _ implantation damage has to be characterized, process flow has to be optimized to avoid implantation damage or remove damage with low thermal budget; _ contamination levels have to be reduced: ultraclean techniques [47] will be introduced in VLSI; ~ charging of wafers through implantation, which may cause gate damage, has to be avoided.

Acknowledgement Fig. 12. (a) Nucleation of a Hu loop at a residual implantation defect induced by the stress of a thick nitride film. (b) Thin nitride film; (c) no nitride film.

The authors are grateful to W. Miiller for continuous support and encouragement, and to R. Kakoschke and A. Strohbach for helpful discussions. I. OVERVIEWS

16

K. I% Kiisters et al. / Ion implantation

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