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Compact carry-save multiplier architecture and its applications
442
Engineering Information Abstracts (Part I)
FDAF which improves the performance of the conventional FDAF for system identification with the presence of additive noise and colored signal input. In English ŽAuthor abstract . 3 Refs. EI Order Number: 98054179487 Keywords: Digital filters; Adaptive filtering; Frequency domain analysis; Parallel processing systems; Spurious signal noise; Mathematical models Title: REAL-TIME PROCESSING OF SPEECH SIGNALS USING NETWORKED COMPUTERS Author(s): Pendse, Ravi; Yip, Andrew W.; Hoyer, Elmer A. Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p 802-805 CODEN: MSCSDL Publication Year: 1997 Abstract: In this paper, parallel processing of speech analysis techniques using networked computers is considered. A unique multiprocessor structure and algorithms have been developed. Results are presented demonstrating that networked computers afford the user the power equivalent to that of parallel processor systems and that processing of speech signals using these algorithms can be accomplished in real-time. In English ŽAuthor abstract . 14 Refs. EI Order Number: 98054179482 Keywords: Speech analysis; Real time systems; Local area networks; Parallel processing systems; Algorithms; Microprocessor chips Title: MULTIPROCESSOR 3D SOUND SYSTEM Author(s): El-Sharkawy, Mohamed; Guillen, Newton; Eshmawy, Waleed; Langhorst, Brad; Gundrum, Harry; Judd, Darrel; Auerbach, Richard Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p 798-801 CODEN: MSCSDL Publication Year: 1997 Abstract: A developed system that allows greater freedom in the placement of the speakers without degrading the degree of freedom in the listener’s position is presented. The implementation of a real-time multiprocessor 3-D sound system based on Analog Devices ADSP-2181 processors is discussed. A Windows based program is used to control the real-time system using the personal computer’s serial and parallel ports. In English 9 Refs. EI Order Number: 98054179481 Keywords: Sounding apparatus; Multiprocessing systems; Digital signal processing; Microprocessor chips; Personal computers; Echo suppression; Real time systems; Crosstalk Title: COMPACT CARRY-SAVE MULTIPLIER ARCHITECTURE AND ITS APPLICATIONS Author(s): Raghunath, Raghu K.J.; Farrokh, Hashem; Naganathan, Nagi; Rambaud, Marta; Mondal, Kalyan; Masci, Frank; Hollopeter, Mark Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p
794-797 CODEN: MSCSDL Publication Year: 1997 Abstract: Carry-save arithmetic based architectures are becoming popular in VLSI designs. However, few designs are available for 2’s complement carry-save multipliers. The carry-save outputs from conventional 2’s complement multipliers are not in legitimate carry-save form. This leads to errors if carry-save manipulations, such as, saturations, sign-extension etc are used. In this paper, a pure carry-save multiplier design is presented. The architecture is compact and regular leading to ease in VLSI implementation. This architecture is extended to design a carry-save multiplierraccumulator. By manipulating the partial product additions a row of adders are saved. Since multipliers form the basic building blocks of any signal processing ASIC design, this leads to large savings in chip area and power dissipation. Application of this design to equalizers and other signal processing blocks is also presented. In English ŽAuthor abstract . 17 Refs. EI Order Number: 98054179480 Keywords: Multiplying circuits; VLSI circuits; Integrated circuit layout; Application specific integrated circuits; Equalizers; Computer architecture; Adders Title: BIASED TWO’S COMPLEMENT REPRESENTATION FOR LOW-POWER DSP SYSTEMS Author(s): Khoo, Kei-Yong; Chen, Chao-Liang; Willson, Alan N. Jr. Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p 786-789 CODEN: MSCSDL Publication Year: 1997 Abstract: This paper shows that the switching activity of the sign-extended bits in a two’s complement number in a DSP system can be reduced by the application of a bias to the system’s input. The technique is easy to implement and requires only one to two additional adders. Experimental results show a 20% and 5% reduction in bit-switching activities for a typical voice grade signal and an FIR filter processing the signal, respectively. In English ŽAuthor abstract . 7 Refs. EI Order Number: 98054179478 Keywords: Digital signal processing; Number theory; Adders; Digital filters; Switching functions Title: FAST VLSI ARCHITECTURE FOR RANK ORDER BASED FILTERING USING A BIT-SERIAL WINDOW PARTITIONING TECHNIQUE Author(s): Savin, C.E.; Ahmad, M.O.; Swamy, M.N.S. Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p 671-674 CODEN: MSCSDL Publication Year: 1997 Abstract: Based on a recently proposed algorithm for stack filtering, the bit-serial window partitioning ŽBSWP. algorithm, a new architecture suitable for the VLSI implementation of very fast rank order based filters for signal and image process-
Engineering Information Abstracts (Part I)
FDAF which improves the performance of the conventional FDAF for system identification with the presence of additive noise and colored signal input. In English ŽAuthor abstract . 3 Refs. EI Order Number: 98054179487 Keywords: Digital filters; Adaptive filtering; Frequency domain analysis; Parallel processing systems; Spurious signal noise; Mathematical models Title: REAL-TIME PROCESSING OF SPEECH SIGNALS USING NETWORKED COMPUTERS Author(s): Pendse, Ravi; Yip, Andrew W.; Hoyer, Elmer A. Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p 802-805 CODEN: MSCSDL Publication Year: 1997 Abstract: In this paper, parallel processing of speech analysis techniques using networked computers is considered. A unique multiprocessor structure and algorithms have been developed. Results are presented demonstrating that networked computers afford the user the power equivalent to that of parallel processor systems and that processing of speech signals using these algorithms can be accomplished in real-time. In English ŽAuthor abstract . 14 Refs. EI Order Number: 98054179482 Keywords: Speech analysis; Real time systems; Local area networks; Parallel processing systems; Algorithms; Microprocessor chips Title: MULTIPROCESSOR 3D SOUND SYSTEM Author(s): El-Sharkawy, Mohamed; Guillen, Newton; Eshmawy, Waleed; Langhorst, Brad; Gundrum, Harry; Judd, Darrel; Auerbach, Richard Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p 798-801 CODEN: MSCSDL Publication Year: 1997 Abstract: A developed system that allows greater freedom in the placement of the speakers without degrading the degree of freedom in the listener’s position is presented. The implementation of a real-time multiprocessor 3-D sound system based on Analog Devices ADSP-2181 processors is discussed. A Windows based program is used to control the real-time system using the personal computer’s serial and parallel ports. In English 9 Refs. EI Order Number: 98054179481 Keywords: Sounding apparatus; Multiprocessing systems; Digital signal processing; Microprocessor chips; Personal computers; Echo suppression; Real time systems; Crosstalk Title: COMPACT CARRY-SAVE MULTIPLIER ARCHITECTURE AND ITS APPLICATIONS Author(s): Raghunath, Raghu K.J.; Farrokh, Hashem; Naganathan, Nagi; Rambaud, Marta; Mondal, Kalyan; Masci, Frank; Hollopeter, Mark Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p
794-797 CODEN: MSCSDL Publication Year: 1997 Abstract: Carry-save arithmetic based architectures are becoming popular in VLSI designs. However, few designs are available for 2’s complement carry-save multipliers. The carry-save outputs from conventional 2’s complement multipliers are not in legitimate carry-save form. This leads to errors if carry-save manipulations, such as, saturations, sign-extension etc are used. In this paper, a pure carry-save multiplier design is presented. The architecture is compact and regular leading to ease in VLSI implementation. This architecture is extended to design a carry-save multiplierraccumulator. By manipulating the partial product additions a row of adders are saved. Since multipliers form the basic building blocks of any signal processing ASIC design, this leads to large savings in chip area and power dissipation. Application of this design to equalizers and other signal processing blocks is also presented. In English ŽAuthor abstract . 17 Refs. EI Order Number: 98054179480 Keywords: Multiplying circuits; VLSI circuits; Integrated circuit layout; Application specific integrated circuits; Equalizers; Computer architecture; Adders Title: BIASED TWO’S COMPLEMENT REPRESENTATION FOR LOW-POWER DSP SYSTEMS Author(s): Khoo, Kei-Yong; Chen, Chao-Liang; Willson, Alan N. Jr. Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p 786-789 CODEN: MSCSDL Publication Year: 1997 Abstract: This paper shows that the switching activity of the sign-extended bits in a two’s complement number in a DSP system can be reduced by the application of a bias to the system’s input. The technique is easy to implement and requires only one to two additional adders. Experimental results show a 20% and 5% reduction in bit-switching activities for a typical voice grade signal and an FIR filter processing the signal, respectively. In English ŽAuthor abstract . 7 Refs. EI Order Number: 98054179478 Keywords: Digital signal processing; Number theory; Adders; Digital filters; Switching functions Title: FAST VLSI ARCHITECTURE FOR RANK ORDER BASED FILTERING USING A BIT-SERIAL WINDOW PARTITIONING TECHNIQUE Author(s): Savin, C.E.; Ahmad, M.O.; Swamy, M.N.S. Source: Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 2 Žof 2. Aug 3-6 1997 v 2 Sacramento, CA, USA. Sponsored by: IEEE Piscataway NJ USA. p 671-674 CODEN: MSCSDL Publication Year: 1997 Abstract: Based on a recently proposed algorithm for stack filtering, the bit-serial window partitioning ŽBSWP. algorithm, a new architecture suitable for the VLSI implementation of very fast rank order based filters for signal and image process-