Novel CFOA based capacitance multiplier and its application

Int. J. Electron. Commun. (AEÜ) 107 (2019) 192–198

Contents lists available at ScienceDirect

International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue

Short communication

Novel CFOA based capacitance multiplier and its application Rakesh Verma, Neeta Pandey ⇑, Rajeshwari Pandey Department of Electronics and Communication Engineering, Delhi Technological University, Bawana Road, Delhi 110042, India

a r t i c l e

i n f o

Article history: Received 12 January 2019 Accepted 8 May 2019

Keywords: CFOA Capacitance multiplier Resonance Multiplication factor

a b s t r a c t This communication presents a novel CFOA based capacitance multiplier. The proposed circuit employs two CFOAs, two resistors and a single capacitor. To achieve higher multiplication factors, the larger component spread is needed in existing CFOA based capacitance multiplier circuits. The proposal addresses this and attains multiplication at lower component spread. The mathematical analysis for modelling the effects of non-ideality shows the deviations from ideal behavior which may be compensated by placing an additional resistor. The functionality is tested using SPICE simulations and experimentation under different conditions. An application namely parallel RLC resonator is included to show the usefulness. Ó 2019 Elsevier GmbH. All rights reserved.

1. Introduction Large valued capacitors are imperative for implementing zeromaking capacitor in loop filter in monolithic phase locked loop (PLL) [1] and applications pertaining to low frequency signal processing such as sample and holds, switched-capacitor, continuous-time filters [2] and implantable biomedical systems [3]. The on-chip realization of such capacitors is not practical [1,2] due to significant area overhead. In order to realize large capacitors, the concept of capacitance multiplier may be used where active blocks are arranged in a configuration providing a multiplication factor for a small on-chip capacitance [3]. In the last few decades a variety of grounded/floating capacitance multiplier circuits [4–43] have been presented using active blocks like operational amplifiers (Op-amps) [4,5], current follower transconductance amplifiers (CFTAs) [6], voltage differencing buffered amplifiers (VDBAs) [7–9], current backward transconductance amplifiers (CBTAs) [10], operational transconductance amplifiers (OTAs) [11–13], OTAs with op-amp [14], current feedback operational amplifiers (CFOAs) [15–20], tunable four terminal floating nullors (TFTFNs) [21] and second-generation current conveyors (CCIIs)/current-controlled CCIIs [22–35]/generalization of current conveyors (CCs) namely dual-X CCII (DXCCII) [36], CC transconductance amplifier (CCTA) [37], differential voltage CCTAs (DVCCTAs) [38,39], differential voltage CCs (DVCCs) [27,40,41], current controlled CC transconductance amplifier (CCCCTAs) [42], current controlled differential difference CCs (CCDDCCs) [43], voltage differencing CCs (VDCCs) [44], fully differential (FD) voltage ⇑ Corresponding author. E-mail address: [email protected] (N. Pandey). https://doi.org/10.1016/j.aeue.2019.05.010 1434-8411/Ó 2019 Elsevier GmbH. All rights reserved.

and current gained (VCG)-CCIIs [45], and current differencing transconductance amplifier (CDTA) [46]. It may be noted that though numerous capacitance multipliers exist but very few are based on commercially available active blocks namely Op-amp [4,5,14], OTA [11–14], AD 844 (CFOA) [15–20,32] and CDTA [46]. This contribution aims at proposing a CFOA based capacitance multiplier circuit. The paper is organized as follows: A brief review of available CFOA multipliers is placed in Section 2. The proposed capacitance multiplier circuit is put forward in Section 3. To examine operation of the proposed circuit, SPICE simulations are carried out under different test cases and the corresponding results are included in Section 3. This section also includes experimental results. An application of proposed multiplier circuit namely reconfiguring parallel RLC resonance circuit is placed in Section 4. The functionality of the application is verified through SPICE simulation which clearly demonstrates the scaling behavior of reconfigured resonator on the basis of numerous case studies. Section 5 is the conclusion part. 2. Brief literature review on CFOA based capacitance multipliers The study of CFOA based capacitance multiplier (C-multiplier) [15–20,32] shows that the multiplication factor (K) of capacitance (C) can be expressed in the form of (i) 1 + P [16,32], (ii) 1-P [32] and (iii) 1/(1 + P) [16,32] where P represents resistor ratio. The structures of type (ii) may be used to realize a C-multiplier presenting a negative capacitance value if P is greater than unity and a positive value for P less than unity. The capacitance multiplier circuit may be obtained by adaptation of CFOA based gyrator [47–49]/generalized impedance converter [50]. Other characteristics are summarized below:

193

R. Verma et al. / Int. J. Electron. Commun. (AEÜ) 107 (2019) 192–198

– [16,18] provide lossy capacitance whereas lossless is obtained in [15,17–20,32] – [15,18,20,32] realize grounded capacitance while floating C realization are found in [16,17,19] – [16,32] can emulate both positive and negative C-multiplier while positive C occurs in [15,32] and negative C in [17–20,32] – The multiplication factor of C-multipliers of type (iii) and type (ii) with P > 1 is less than unity. So, the effective value of capacitor decreases which may be used multiplication factor multiplication factor multiplication factor capacitor which is not available otherwise. – Larger component spread (resistance ratio) is needed to achieve higher multiplication factor [15–20,32,47–50]. It is clear from above discussion that available CFOA based topologies require larger component spread for higher multiplication factor. An alternative approach is presented in this paper wherein multiplication factor depends on ratio of resistance and difference between the resistor values. Therefore, closer are the resistor values, higher will be the multiplication factor.

3. Proposed CFOA based capacitance multiplier circuit This section presents a new type of C-multiplier circuit with multiplication factor of K = 1/(1
P) and designate this as type (iv). This type of circuit can provide very high multiplication factor by selecting P close to unity. The closer is P to unity, higher would be the multiplication factor resulting in smaller component spread. The CFOA symbol and port relationships are described first and followed by proposed circuit schematic and related discussion. 3.1. The CFOA

3.2. Proposed circuit The schematic of proposed C-multiplier circuit is shown in Fig. 2. It uses two CFOAs, two resistors and a capacitor (for noncompensating circuit). The proposed circuit uses floating capacitor which may be realized using Metal-insulator-metal (MIM) or metal-oxide-metal (MOM) double poly (poly1-poly2) capacitor processes [51]. Considering port relation of (1), the input impedance of the proposed circuit is computed as

Z in ðsÞ ¼

1 1 1
R2 =R1 ¼ ¼ sC eff sðKC Þ sC

ð3Þ

where K ¼ 1=ð1
R2 =R1 Þ It is clear from (3) that the smaller is the component spread larger will be the multiplication factor (K) e. g. R2 = 0.9 R1 gives K = 10. R2 =R1 The sensitivity of the (K) with respect to R2 =R1 is SKR2 =R1 ¼ 1
R . 2 =R1

Therefore, the advantage comes at the cost of higher sensitivity of K. To analyze the proposed circuit’s behavior in presence of CFOA non-idealities shown in Fig. 1(b), the input impedance is recomputed as

Z in ðsÞjn ¼

1 sC þ GY1 þ sC Y1 þ ðG

ð4Þ where GY1 ; C Y1 ; GZ1 ; C Z1 ; RX1 ; and GZ2 ; C Z2 ; RX2 are parasitics of CFOA1; and CFOA2 respectively. Considering RX2 GZ1  1 operating frequency x<
 min RY1 ðC1 þCÞ ; RZ21C ; RX21C , (3) reduces to Z2

Y1

Z1

1 ða2 bcÞsC

The symbol of CFOA shown in Fig. 1(a) has port relationship given by (1).

Z in ðsÞjn 

IY ¼ 0; V X ¼ V Y ; IZ ¼ IX ; V O ¼ V Z

which gives multiplication factor as

ð1Þ

Fig. 1(b) shows equivalent circuit with CFOA non-idealities. The (RY, CY) and (RZ, CZ) correspond to parasitic resistor and capacitor at Y and Z terminals while RX represent parasitic resistor at X terminal. There are two voltage buffers between Y and X-terminals; and O and Z-terminals; and one current follower between Z and X-terminals where a represents current transfer gain; and b, c correspond to voltage transfer gains due to tracking errors of CFOA. This restructured port relationship of (1) as

IY ¼ 0; V X ¼ bV Y ; IZ ¼ aIX ; V O ¼ cV Z

ð2Þ

ða2 bcÞsC

2 2 þGZ2 þsC Z2 ÞðR1 þRX1 Þð1þRX2 GZ1 þsRX2 C Z1 Þ
a c

sC þ ðG

ð5Þ

2 2 þGZ2 ÞðR1 þRX1 Þ
a c

Kn ¼ 1 þ

a2 bc

ð6Þ

ðG2 þ GZ2 ÞðR1 þ RX1 Þ
a2 c

It may be observed from (6) that multiplication factor (K n Þ drastically decreases for a; b; c < 1. To compensate this, a grounded 0

resistor R at X-terminal of CFOA1 may be placed (as shown in Fig. 2) which modifies (4) to

1

0

Z in ðsÞjn ¼

sC þ GY1 þ sC Y1 þ

Ideally these values are GY1 ¼ GZ1 ¼ GZ2 ¼ RX1 ¼ RX2 ¼ C Y1 ¼ C Z1 ¼ C Z2 ¼ 0 and a ¼ b ¼ c ¼ 1

Fig. 1. (a) CFOA symbol and (b) its equivalent circuit with parasitic.

ða2 bcÞsC




RX1 ðG2 þGZ2 þsC Z2 Þð1þRX2 GZ1 þsRX2 C Z1 Þ
a2 c

0 R 0 R1 þR

 ð7Þ

194

R. Verma et al. / Int. J. Electron. Commun. (AEÜ) 107 (2019) 192–198

The relation between R1 and R’ is obtained by comparing (8) and (9) as 0

R ¼

P R1 1
P

ð10Þ

where

  RX1 ðG2 þ GZ2 Þð1 þ RX2 GZ1 Þ R1 P¼b
þ 1 a2 bc R2

ð11Þ

The behavior of capacitance multiplier circuit is examined under non-compensating, compensating and ideal conditions and simulation results are demonstrated in Fig. 3. The responses are plotted for factor K = 100 where R1 = 20.02 kO, R2 = 20 kO, 0

R = 32.16 O, by assuming non-ideal characteristics occurred due to a; b; c = 0.99 and RX1 ¼ RX2 = 50 O, RY1 ¼ RY2 = 2 MO, RZ1 ¼ RZ2 = 3 MO, C Y1 ¼ C Y2 = 2 pF, C Z1 ¼ C Z2 = 4.5 pF. Fig. 2. Proposed CFOA based capacitance multiplier circuit.

Considering R G  1, operating frequency x<
 X2 Z1 min RZ21C ; RX21C ; and neglecting parasitic effect at Y-terminal, Z2

Z1

(7) reduces to

1 ða2 bcÞsC

0

Z in ðsÞjn 

sC þ




RX1 ðG2 þGZ2 Þð1þRX2 GZ1 Þ
a2 c

0

ð8Þ



R 0 R1 þR

3.3. Functional verification The functionality of the proposed capacitance multiplier is examined using CFOA model [52] using the following simulations conditions: (i) K is fixed and varying C; (ii) C is fixed and varying K; and (iii) K and C are fixed and varying temperature.

Since ideally it is expressed by (9)

Z in ðsÞ ¼

1 sC þ G2 RsC1
1

ð9Þ

which are designated as case 1, case 2 and case 3 respectively; and detailed simulation settings are placed in Table 1. Simulated and theoretical frequency responses are plotted in Fig. 4(a) and

Fig. 3. Magnitude responses of proposed non-compensating and compensating circuits with ideal case.

Table 1 Detailed simulation settings and summary of observations. Case

Components tuning C (nF)

1

2

0.1 10 100 1

3

1

Realized Ceff (F)

K tuning

Temperature (°C)

K

R1 (kO)

R2 (kO)

R0 (kO)

100

20.202

20

4.4

27

50 100 200 5

20.408 20.202 20.1 25

20 20 20 20

9.1 4.4 2.23 (not required)

27


55 27 125

10n 1m 10m 50n 100n 200n 5n

Frequency response Magnitude response within 7% error

Phase response within 60 phase error

upto 390 kHz upto 43.6 kHz upto 25.1 kHz upto 141 kHz upto 144.5 kHz upto 190 kHz 5.75 Hz–512.8 kHz upto 281 kHz upto 331 kHz

upto 67.6 kHz upto 20.5 kHz upto 2.89 kHz upto 75.8 kHz upto 55 kHz upto 40.7 kHz 10 Hz–794 kHz upto 316.23 kHz upto 416.8 kHz

R. Verma et al. / Int. J. Electron. Commun. (AEÜ) 107 (2019) 192–198

195

Fig. 4. Simulation (solid lines) and ideal (dashed lines) magnitude (in black) and phase (in green) responses of the proposed Fig. 2 circuit for (a) fixed K = 100 and different C = 100 nF, 10 nF, 0.1 nF (b) fixed C = 1 nF, and different K = 50, 100, 200. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

(b) respectively for cases 1 and 2 at room temperature. The effective value of capacitance and frequency range is also listed in Table 1. Fig. 5 shows the simulation and theoretical frequency responses by varying temperature.

The functionality of the proposed circuit is examined through experimentation. The proposed circuit is breadboarded for K = 5 and 21 with (R1 = 25 kX, R2 = 20 kX) and (R1 = 21 kX, R2 = 20 kX) respectively. Power supply of ±10 V is considered and a sinusoid

Fig. 5. Impedance magnitude and phase responses of the proposed Fig. 2 circuit at different temperature.

196

R. Verma et al. / Int. J. Electron. Commun. (AEÜ) 107 (2019) 192–198

Fig. 6. Experimental results of Fig. 2 for K = 5 and 21.

having Vpeak-peak of 2 V is applied to examine the performance of the proposal. The simulated, theoretical and experimental magnitude response is depicted in Fig. 6 for C = 1 nF. The frequency ranges of multiplier circuit for K = 5 and 21 are (0.02–2.8) kHz and (9.1–10.9) kHz respectively within 10% deviations. A deviation of up to 40% is observed for K = 21 for frequencies up to 20 kHz. The designer needs to take care of limited range for higher capacitance value i.e. designer has to preadjust the value of resistor once the frequency/frequency range of operation is fixed. It is emphasized here that high multiplication factor requires passive components with great precision. Therefore it is difficult to achieve very high multiplication factor. In integrated circuit realization, such precision may be achieved by using electronically tunable resistor.

The impedance function of the reconfigured parallel RLC circuit is given as

Z in ¼

1 1 ¼ Y in R1 þ sL1 þ sC eff eff

ð13Þ

eff

and its performance parameters resonant frequency (x0 ), quality-factor (Q) and peak impedance at resonant frequency (Z in jx0 ) are evaluated as

x0 ¼

qffiffiffiffiffiffiffiffiffiffi 1 Leff C eff

Q ¼ Reff :

qffiffiffiffiffiffi

ð14Þ

C eff Leff

Z in jx0 ¼ Reff 0

Assuming K1 and K2 as multiplication factors for C eff and C eff i.e.

4. Application

0

The proposed C multiplier circuit (Fig. 2) may be add extra degree of freedom for scaling the circuit behavior. In this section, the proposed circuit is employed for reconfiguration of a parallel RLC resonator (Fig. 7) for simulating grounded parallel RL combination using active CFOA element [53]. The values of components Reff and Leff are given in (12) while C eff is obtained from (2) 0

Reff ¼

0

R1 R2

0

0

0

R1 þ R2

0

0

; Leff ¼ C eff R1 R2

ð12Þ

0

C eff ¼ K 1 C, and C eff ¼ K 2 C , the performance parameters of (14) can be rearranged as

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 1 0 0 0 : K 2 C R1 R2 K 1 C pffiffiffiffiffiffiffi ffi 0 0 qffiffiffiffiffiffiffiffi R R Q ¼ 0 1 0 2 : K 1 C0

x0 ¼

R1 þR2

Z in jx0 ¼

K2 C

0 0 R1 R2 0 0 R1 þR2

Fig. 7. (a) Reconfiguration of parallel RLC resonance circuit (b) CFOA based active simulation of parallel RL circuit.

ð15Þ

197

R. Verma et al. / Int. J. Electron. Commun. (AEÜ) 107 (2019) 192–198 Table 2 Performance case study of the reconfigured parallel RLC resonator. Case

Case Test no.

Reff

C eff

0

1

2

3

S1 S2 S3 S4 S5 S6 S7 S8 S9

0

Leff 0

R1 ¼ R2 (kO)

Reff (kO)

K1

C (nF)

C eff (nF)

K2

C (nF)

Leff (H)

0.5 1 2 0.5

0.25 0.5 1 0.25

100

1

100

100

1

1

0.25

200 100 50 100 200 400

200 100 50 200 100 50

1

0.5

200 100 50 50 100 200

0.025 0.1 0.4 0.05 0.025 0.0125 0.1 0.05 0.025

2

2

x0 (krad/s)

Q

Z in jx0 (kO)

20 10 5 10 20 40 10

0.5

0.25 0.5 1 0.25

0.5

0.25 0.5 1

0.25

Fig. 8. Simulation outputs for input impedance of reconfigured parallel RLC (Fig. 7) for (a) Case1, (b) Case 2, (c) Case 3.

The performance parameters of the reconfigured resonator can be tuned by controlling the effective values of components (C eff , Leff , Reff ) of the reconfigured resonator. Following test cases are selected: 0

0

Case 1: Tuning R1 and R2 while keeping K 1 and K 2 constant Case 2: Tuning K 1 and K 2 while maintaining K 1 ¼ K 2 Case 3: Tuning K 1 and K 2 while retaining their product (K 1 :K 2 ) constant Case 1 affects the performance parameters x0 and Z in jx0 and is thus useful when these parameters need be changed for the fixed value of Q-factor. Case 2 is useful for changing x0 while retaining the Q-factor and Z in jx0 . Case 3 is appropriate for varying Q-factor and keeping x0 and Z in jx0 constant. Simulations for all the three cases are carried out with test conditions listed in Table 2 and the input impedance under the test conditions are plotted in Fig. 8. The performance parameters are also listed in Table 2. Thus its performance parameters can be independently controlled by following observations obtained from above simulations:

– Case1: different desirable impedance peaks (=0.25 k, 0.5 k, 1 k) and fixed Q (=0.5) at different x0 (=20 krad/s, 10 krad/s, 5 krad/s) – Case2: x0 tuning (=10 krad/s, 20 krad/s, 40 krad/s) with constant impedance peaks (=0.25 k) and Q (=0.5) – Case3: Q tuning (=0.25, 0.5, 1) with constant impedance peaks (=0.25 k) and x0 (=10 krad/s). 5. Conclusion A CFOA based capacitance multiplier is presented in this paper which uses two CFOAs, two resistors and a single capacitor. It requires lower component spread in order to achieve larger multiplication factor. Effects of non-idealities are addressed and compensation method is also suggested. The operation of proposed circuit is verified through SPICE simulations under variety of test cases and usefulness is illustrated through parallel RLC resonator. Declaration of Competing Interest The authors declared that there is no conflict of interest.

198

R. Verma et al. / Int. J. Electron. Commun. (AEÜ) 107 (2019) 192–198

References [1] Choi J, Park J, Kim W, Lim K, Laskar J. High multiplication factor capacitor multiplier for an on-chip PLL loop filter. Electron Lett 2009;45(5):239–40. [2] Aparicio R, Hajimiri A. Capacity limits and matching properties of integrated capacitors. IEEE J Solid-State Circ 2002;37(3):384–93. [3] Al-Absi MA, Al-Suhaibani ES, Abuelma’atti MT. A new compact CMOS Cmultiplier. Analog Integr Circ Sign Process 2017;90(3):653–8. [4] Marcellis AD, Ferri G, Stornelli V. NIC-based capacitance multipliers for lowfrequency integrated active filter applications. In: IEEE research in microelectronics and electronics conference 2007, 2007 July 2–5, Bordeaux. p. 225–8. [5] Tang Y, Ismail M, Bibyk S. Adaptive Miller capacitor multiplier for compact onchip PLL filter. Electron Lett 2003;39(1):43–5. [6] Li YA. A series of new circuits based on CFTAs. AEU - Int J Electron Commun 2012;66:587–92. [7] Mongkolwai P, Tangsrirat W. Generalized impedance function simulator using voltage differencing buffered amplifiers (VDBAs). Proceedings of the international multiconference of engineers and computer scientists 2016, 2016 March 16–18, Hong Kong, 2016. p. 609–12. [8] Unhavanich S, Onjan O, Tangsrirat W. Tunable capacitance multiplier with a single voltage differencing buffered amplifier. In: Proceedings of the international multiconference of engineers and computer scientists 2016, 2016 March 16–18, Hong Kong. p. 568–71. [9] Pimpol J, Channumsin O, Tangsrirat W. Floating capacitance multiplier circuit using full-balanced voltage differencing buffered amplifiers (FB-VDBAs). In: Proceedings of the international multiconference of engineers and computer scientists 2016, 2016 March 16–18, Hong Kong. p. 564–7. [10] Ayten UE, Sagbas M, Herencsar N, Koton J. Novel floating general element simulators using CBTA. Radioengineering 2012;21(1):11–9. [11] Jaikla W, Siripruchyanan M. An electronically controllable capacitance multiplier with temperature compensation. In: IEEE international symposium on communications and information technologies 2006, Bangkok. p. 356–9. [12] Khan IA, Ahmed MT. OTA-based integrable voltage/current-controlled ideal Cmultiplier. Electron Lett 1986;22(7):365–6. [13] Sotner R, Jerabek J, Petrzela J, Domansky O, Tsirimokou G, Psychalinos C. Synthesis and design of constant phase elements based on the multiplication of electronically controllable bilinear immittances in practice. AEU Int J Electron Commun 2017;78:98–113. https://doi.org/10.1016/j. aeue.2017.05.013. [14] Ahmed MT, Khan IA, Minhaj N. Novel electronically tunable C-multipliers. Electron Lett 1995;31(1):9–11. [15] Yuce E, Minaei S. A modified CFOA and its applications to simulated inductors, capacitance multipliers, and analog filters. IEEE Trans Circ Syst I 2008;55 (1):266–75. [16] Abuelma’atti MT, Dhar SK, Khalifa ZJ. New two-CFOA-based floating immittance simulators. Analog Integr Circ Sig Process 2017;91(3):479–89. https://doi.org/10.1007/s10470-017-0956-9. [17] Abuelma’atti MT, Dhar SK. New CFOA-based floating lossless negative immittance function emulators. In: TENCON 2015 - IEEE region 10 conference 2015, Macao. p. 1–4. [18] Abuelma’atti MT. New grounded immittance function simulators using single current feedback operational amplifier. Analog Integr Circ Sig Process 2012;71 (1):95–100. https://doi.org/10.1007/s10470-011-9742-2. [19] Abuelma’atti MT, Dhar SK. CFOA-based floating negative inductance, positive frequency dependent resistance and resistance-controlled capacitance and resistance emulator. In: IEEE international conference on electronics, information, and communications (ICEIC) 2016, Da Nang. p. 1–3. [20] Lahiri A, Gupta M. Realizations of grounded negative capacitance using CFOAs. Circuits Syst Sig Process 2011;30(1):143–55. https://doi.org/10.1007/s00034010-9215-3. [21] Jaikla W, Lahiri A, Siripruchyanun M. Capacitance multipliers using tunable four terminal floating nullors. In: IEEE international conference on electrical engineering/electronics computer telecommunications and information technology 2010; 2010 May 19–21, Chiang Mai, Thailand. p. 42–5. [22] Lahiri A. DO-CCII based generalised impedance convertor simulates floating inductance, capacitance multiplier and FDNR. Aust J Electr Electron Eng 2010;7 (1):15–20. [23] Minaei S, Yuce E, Cicekoglu O. A versatile active circuit for realising floating inductance, capacitance, FDNR and admittance converter. Analog Integr Circ Sig Process 2006;47:199–202. [24] Abuelma’atti MT, Tasadduq NA. Electronically tunable capacitance multiplier and frequency-dependent negative-resistance simulator using the currentcontrolled current conveyor. Microelectr J 1999;30:869–73. [25] Alpaslan H, Yuce E. Bandwidth expansion methods of inductance simulator circuits and voltage-mode biquads. J Circ Syst Comput 2011;20(3):557–72.

[26] Yuce E. On the realization of the floating simulators using only grounded passive components. Analog Integr Circ Sig Process 2006;49:161–6. [27] Siripruchyanan M, Jaikla W. Floating capacitance multiplier using DVCC and CCCIIs. In: IEEE international symposium on communications and information technologies 2007, Sydney. p. 218–21. [28] Premont C, Grisel R, Abouchi N, Chante JP. A current conveyor based capacitive multiplier. In: IEEE proceedings of 40th midwest symposium on circuits and systems 1997. p. 146–7. [29] Cataldo GD, Ferri G, Pennisi S. Active capacitance multipliers using current conveyors. In: Proceedings of the 1998 IEEE international symposium on circuits and systems, ISCAS ’98. p. 343–6. [30] Ferri G, Pennisi S. A 1.5-V current-mode capacitance multiplier. In: IEEE proceedings of the tenth international conference on microelectronics 1998, Monastir. p. 9–12. [31] Saad RA, Soliman AM. On the systematic synthesis of CCII-based floating simulators. Int J Circ Theory Appl 2010;38:935–67. [32] Khan AA, Bimal S, Dey KK, Roy SS. Current conveyor based R- and C- multiplier circuits. AEU Int J Electron Commun 2002;56:312–6. [33] Yuce E, Minaei S, Cicekoglu O. Resistorless floating immittance function simulators employing current controlled conveyors and a grounded capacitor. Electr Eng 2006;88:519–25. [34] Yuce E. Floating inductance, FDNR and capacitance simulation circuit employing only grounded passive elements. Int J Electron 2006;93:679–88. [35] Yesil A, Yuce E, Minaei S. Grounded capacitance multipliers based on active elements. AEU Int J Electron Commun 2017;79:243–9. https://doi.org/ 10.1016/j.aeue.2017.06.006. [36] Myderrizi I, Zeki A. Electronically tunable DXCCII-based grounded capacitance multiplier. AEU Int J Electron Commun 2014;68:899–906. [37] Jantakun A. A simple grounded FDNR and capacitance simulator based-on CCTA. AEU Int J Electron Commun 2015;69(6):950–7. https://doi.org/10.1016/ j.aeue.2015.03.002. [38] Tangsrirat W. Floating simulator with a single DVCCTA. Ind J Eng Mater Sci 2013;2013:79–86. http://nopr.niscair.res.in/handle/123456789/17099. [39] Jantakun A, Pisutthipong N, Siripruchyanun M. Single element based-novel temperature insensitive/electronically controllable floating capacitance multiplier and its application. In: International conference on electrical engineering/electronics, computer, telecommunications and information technology (ECTI-CON 2010), Chaing Mai. p. 37–41. [40] Alpaslan H. DVCC-based floating capacitance multiplier design. Turkish J Electr Eng Comput Sci 2017;25:1334–45. [41] Yuce E. A novel floating simulation topology composed of only grounded passive components. Int J Electron 2010;97:249–62. [42] Silapan P, Tanaphatsiri C, Siripruchyanun M. Current controlled CCTA basednovel grounded capacitance multiplier with temperature compensation. In: APCCAS 2008 IEEE Asia Pacific conference on circuits and systems 2008, Macao. p. 1490–3. [43] Prommee P, Somdunyakanok M. CMOS-based current-controlled DDCC and its applications to capacitance multiplier and universal filter. AEU Int J Electron Commun 2011;65:1–8. [44] Kartci A, Ayten UE, Herencsar N, Sotner R, Jerabek J, Vrba K. Application possibilities of VDCC in general floating element simulator circuit. In: European conference on circuit theory and design 2015, 2015 Aug 24–26, Trondheim, Norway. p. 1–4. [45] Marcellis AD, Ferri G, Guerrini NC, Scotti G, Stornelli V, Trifiletti A. A novel lowvoltage low-power fully differential voltage and current gained CCII for floating impedance simulations. Microelectron J 2009;40(1):20–5. https://doi. org/10.1016/j.mejo.2008.08.014. [46] Biolek D, Vavra J, Keskin AU. CDTA-based capacitance multipliers. Circ Syst Sig Process 2019;38(4):1466–81. https://doi.org/10.1007/s00034-018-0929-y. [47] Fabre A. Gyrator implementation from commercially available operational transimpedance operational amplifiers. Electron Lett 1992;28:263–4. [48] Senani R. Realization of a class of analog signal processing/signal generation circuits: novel configurations using current feedback op-amps. Frequenz 1998;52(9–10):196–206. [49] Senani R, Bhaskar DR, Singh AK, Singh VK. Current feedback operational amplifiers and their applications. New York: Springer Science + Business Media; 2013. p. 54–6. [50] Psychalinos C, Pal K, Vlassis S. A floating generalized impedance converter with current feedback operational amplifiers. AEU Int J Electron Commun 2008;62:81–5. [51] Komanapalli G, Pandey R, Pandey N. New sinusoidal oscillator configurations using operational transresistance amplifier. Int J Circ Theor Appl 2019:1–20. [52] Madian AH, Mahmoud SA, Soliman AM. New 1.5-V CMOS current feedback operational amplifier. In: 13th IEEE international conference on electronics, circuits and systems 2006; 2006 Dec 10–13. p. 600–3. [53] Soliman AM. Applications of the current feedback operational amplifiers. Analog Integr Circ Sig Process 1996;11(3):265–302.