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A new CFOA based grounded capacitance multiplier
Journal Pre-proofs Regular paper A New CFOA Based Grounded Capacitance Multiplier Mehmet Dogan, Erkan Yuce PII: DOI: Reference:
S1434-8411(19)32389-1 https://doi.org/10.1016/j.aeue.2019.153034 AEUE 153034
To appear in:
International Journal of Electronics and Communications
Received Date: Revised Date: Accepted Date:
22 September 2019 11 December 2019 11 December 2019
Please cite this article as: M. Dogan, E. Yuce, A New CFOA Based Grounded Capacitance Multiplier, International Journal of Electronics and Communications (2019), doi: https://doi.org/10.1016/j.aeue. 2019.153034
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
© 2019 Published by Elsevier GmbH.
The second revised version of AEUE_2019_2308
A New CFOA Based Grounded Capacitance Multiplier Mehmet Dogan Pamukkale University, Department of Electrical and Electronics Engineering, 20160, Denizli, Turkey E-mail: [email protected]
Erkan Yuce* Pamukkale University, Department of Electrical and Electronics Engineering, 20160, Denizli, Turkey E-mail: [email protected]
*corresponding author Abstract: A new CFOA based grounded capacitance multiplier is proposed in this study. The proposed grounded capacitance multiplier that does not need any passive component matching conditions employs two CFOAs, a grounded capacitor and a couple of resistors. A number of frequency and time domain analyses for the proposed grounded capacitance multiplier are performed through the SPICE simulation program. During the simulations, ± 9 V supply voltages and a commercially available AD844 model are used. In addition to these, an experiment in time domain is made to validate the performance.
Keywords: CFOA; AD844; grounded capacitance multiplier. 1. Introduction The capacitance multipliers are needed for the integrated circuit (IC) process because large-valued capacitors occupy large areas on the chip. The purpose of the capacitance multipliers [1]-[17] is to obtain a large-valued equivalent capacitor from a small-valued capacitor. Until now, the capacitance multipliers have
been realized with various kinds of active elements for example OTAs [1]-[7], CCIIs [8]-[10], CFOAs [1], [11]-[15], DXCCII [16], etc. The capacitance multipliers proposed in [1]-[7] include OTA(s) which have restrictions at the high frequencies [18]. The capacitance multiplier developed in [1] possesses one grounded capacitor attached to series to X terminal of the CFOA. Therefore, it has limited high frequency performances [19]. The circuit of [5] also uses an operational amplifier that has slew-rate limitations. The capacitance multipliers presented in [8]-[10], [15] are realized with three AD844s [20]. Moreover, the capacitance multipliers reported in [2]-[4], [6], [7], [11], [12], [16], [17] employ a floating capacitor that is not suitable IC fabrication. The capacitance multiplier proposed in [13] includes a grounded resistor attached to series to the Z terminal. For this reason, its high frequency performance is poor [19]. The capacitance multiplier presented in [14] includes a grounded capacitor attached to series to X terminal. On the other hand, CFOA based circuits find wide application areas such as first-order all-pass filters [20], immittance function simulators [22], second-order filters [23][25], oscillators [25]-[27], etc. In this paper, a new grounded capacitance multiplier is proposed. The proposed circuit includes two CFOAs, one grounded capacitor and a couple of resistors. Any passive component matching constraints are not required for the proposed capacitance multiplier. Many frequency and time domain analyses for the proposed grounded capacitance multiplier are carried out through the SPICE program. During the simulations, ± 9 V supply voltages are chosen where AD844 model [18] is used. Moreover, an experiment in time domain is made in which ± 9 V supply voltages are chosen. The proposed grounded capacitance multiplier is illustrated in Section 2. In Sections 3 and 4, a number of simulation results and an experimental study for the proposed topology are respectively shown. A conclusion for the proposed circuit is finally given in Section 5.
2. The Proposed Grounded Capacitance Multiplier The CFOA can be explained in matrix equation (1). Moreover, its symbol is denoted in Fig. 1 while the CFOA with its parasitic impedances is depicted in Fig. 2.
VX I sC Y Y IZ 0 VW 0
RX
0 0 sCZ 1/ RZ
0
0
2
0 VY 0 I X 0 VZ RW IW
(1)
where the values of β, α and η are ideally one [28]. Furthermore, they are non-ideal gains. RX, RZ and RW are parasitic resistors while CZ and CY are parasitic capacitors. Ideally, RX, RW, CZ and CY are equal to zero while RZ is equal to infinity.
IX
VX
X
IY
VY
IW
CFOA W Z Y
VW
IZ
VZ Fig. 1. The circuit symbol of the CFOA.
CY
VY
Y
IY
CFOA VX
RX
IX
Z X
W
RW
IW
VW
RZ
IZ
CZ
VZ Fig. 2. The CFOA with its parasitic impedances. Without considering any non-idealities, the input impedance of the proposed capacitance multiplier in Fig. 3 is evaluated as Zin (s)
Vin 1 1 Iin sC 2R2 sCeq R1
(2)
Here, Ceq = 2CR2/R1. If non-ideal gains are taken into account, the input impedance of the proposed capacitance multiplier is computed as
3
R1
Vin
X
Z CFOA W (1) Y
Iin
Zin
R2
Y Z W CFOA (2) X
C
Fig. 3. The proposed grounded capacitance multiplier.
Zin (s)
1 1 (1 1 )sCR2 (1 1 )(11 2 ) 1 sCeq Req 12 11R1 111R1
(3)
In equation (3) given above, Ceq = (1+α1)CR2/(α1α2β1η1R1) and Req = α1β1η1R1/((1+α1)(β1η1 - β2)). From equation (3), quality factor (Q) of the proposed capacitance multiplier is found as Q Ceq Req
(4)
where ω = 2×π×f is an angular frequency. The proposed capacitance multiplier can be operated as a lossless capacitance multiplier (Q≥10) in the following frequency range:
f
10 1 2 Ceq Req
(5)
If only parasitic resistors of the X and W terminals of the CFOAs are considered, the input impedance of the proposed capacitance multiplier is calculated as Zin (s)
R 1 1 X1 Req 2 R2 RX 2 RW 1 2 sCeq sC R1 RX 1
(6)
where Ceq = 2C(R2+RX2+RW1)/(R1-RX1) and Req = RX1/2. As stated in [29], R1 must be chosen greater than RX1 for stable impedance. From equation (6), Q of the proposed capacitance multiplier is found as follows: Q
1 1 Ceq Req Ceq Req
4
(7)
The proposed capacitance multiplier can be operated as a lossless capacitance multiplier (Q≥10) in the following frequency range: f
1 1 10 2 Ceq Req
(8)
If only parasitic impedances of the Z and Y terminals of the CFOAs are considered, the input impedance of the proposed capacitance multiplier is evaluated as Zin (s)
R1RZ1RZ 2 as2 bs c
(9)
Here, a (C CY1 CY 2 CZ 2 )CZ1R1R2 RZ1RZ 2 b CZ1R1RZ1 (R2 RZ 2 ) (C CY1 CY 2 CZ 2 )R2 RZ 2 (R1 2RZ1 )
c R2 (R1 2RZ1 ) R1RZ 2
(10.a) (10.b) (10.c)
In equations (10), b and c must be greater than zero for stable impedance [29]. On the other hand, from equation (3), the passive and active sensitivities with respect to Ceq and Req are computed as follows: C
C
C
SC eq SR1eq SR2eq 1 C
S1eq C
1 1 1
C
C
S2eq S1eq S1eq 1 C
C
R
R
R
R
S 2eq S2eq SC eq S R2eq S 2eq S2eq 0 R
SR1eq 1, SR1eq R
R
R
1 1 1
S1eq S2eq S1eq
2 11 2
3. Simulation Results The proposed capacitance multiplier depicted in Fig. 3 is simulated through the SPICE program in which AD844 model [30] is utilized. Supply voltages are selected as ±9 V. Furthermore, R1= 1 kΩ, R2= 5 kΩ and C= 100 pF are selected as passive components resulting in Ceq= 1 nF (values of some parasitic impedances of the AD844 are RX ≅ 50 , RZ ≅ 3 M and CZ ≅ 5.5 pF). At 100 kHz, two separate sinusoidal input currents with peak-to-peak value of 1 mA are applied. Thus, ideal and simulation output voltages are shown in Fig. 4. An AC analysis for the proposed grounded capacitance multiplier is shown in Fig. 5. It is observed from Fig. 5 that the proposed capacitance multiplier has limitations at low and high frequencies due to parasitic impedances and non-ideal gains. After one hundred runnings, a Monte Carlo (MC) analysis is 5
achieved for the proposed capacitance multiplier where the values of all the passive components are uniformly changed by 5 %. Also, the result of the MC analysis is demonstrated in Fig. 6. Two resistors R1= 1 kΩ and R2= 5 kΩ are selected as constant values besides C= 100 pF, C= 75 pF, C= 50 pF and C= 25 pF are chosen as variable values. Therefore, Ceq are respectively found as 1 nF, 750 pF, 500 pF and 250 pF. AC analyses of the proposed circuit for different values of the capacitor are shown in Fig. 7. R1= 1 kΩ and C= 100 pF are selected as constant values besides R2= 10 kΩ, R2= 7.5 kΩ, R2= 5 kΩ and R2= 2.5 kΩ are chosen as variable values. Hence, Ceq are respectively obtained as 2 nF, 1.5 nF, 1 nF and 500 pF. AC analyses of the proposed capacitance multiplier for different values of R2 are demonstrated in Fig. 8. A comparison with AC analyses of this work and the capacitance multipliers in references [13] and [14] are denoted in Fig. 9 where Ceq is chosen as 1 nF. The power dissipation of each of the proposed capacitance multiplier and one in [14] is found as 233 mW while power consumption of the capacitance multiplier developed in [13] is found as 235 mW via the SPICE program. In addition, the capacitance multipliers in [13] and [14] like the proposed one are composed of two CFOAs, two resistors and a grounded capacitor.
Fig. 4. A time domain analysis for the proposed grounded capacitance multiplier.
6
Fig. 5. An AC analysis for the proposed grounded capacitance multiplier.
Fig. 6. A Monte Carlo analysis for the proposed grounded capacitance multiplier.
Fig. 7. AC analyses for the proposed grounded capacitance multiplier for different values of the capacitor. 7
Fig. 8. AC analyses for the proposed grounded capacitance multiplier for different values of the resistor R2.
Fig. 9. A comparison with AC analyses of this work and the circuits in references [13] and [14].
As stated by an anonymous reviewer, it is observed from the proposed capacitance multiplier given in Fig. 3 that if the capacitor, C has 0 V, the voltages at the Y terminals of both CFOAs will be 0 V. In addition, the voltages at the X terminals of both CFOAs are 0 V. However, the applied input current passes through the X and Z terminals of both CFOAs due to parasitic impedances of both CFOAs. As a result, input impedance of the proposed capacitance multiplier does not give any stability problems.
8
4. Experimental Study An experiment is made for the proposed capacitance multiplier with three AD844s (one AD844 is used to obtain a current source), three resistors (one resistor (R = 1 kΩ) attached to X terminal of the AD844 is used to obtain a current source) and one capacitor. Passive elements R1= 1 kΩ, R2= 4.7 kΩ, C= 100 pF resulting in Ceq= 940 pF and supply voltages are chosen as ± 9 V in the experiment. A sinusoidal input current with peak-to-peak of 720 µA (applied input voltage is about peak-to-peak 720 mV) at 20 kHz is applied to input of the proposed grounded capacitance multiplier. Consequently, the sinusoidal input voltage and the corresponding sinusoidal output voltage with peak-to-peak of 4.6 V at 20 kHz are indicated in Fig. 10. The experimental result shows that the proposed grounded capacitance multiplier works well.
Fig. 10. The experimental result.
5. Conclusion A new grounded capacitance multiplier that is proposed in this paper contains two CFOAs, two resistors and one grounded capacitor. It does not need any passive component matching constraints. A non-ideality analysis is also given. An experiment and many simulations demonstrate that the proposed capacitance multiplier works well. There is an insignificant difference among ideal, experimental and simulation results because AD844s are not ideal active devices.
References [1] M. A. Al-Absi, and M. T. Abuelma’atti, “A novel tunable grounded positive and negative impedance multiplier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 6, pp. 924-927, 2019.
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[2] I. Padilla-Cantoya, and P. M. Furth, “Enhanced grounded capacitor multiplier and its floating implementation for analog filters,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 10, pp. 962-966, 2015. [3] E. Alaybeyoglu, “Implementation of capacitor multiplier with cell-based variable transconductance amplifier,” IET Circuits, Devices & Systems, vol. 13, no. 3, pp. 267-272, 2018. [4] I. A. Khan, and M. T. Ahmed, “OTA-based integrable voltage/current-controlled ideal C-multiplier,” Electronics letters, vol. 22, no. 7, pp. 365-366, 1986. [5] M. T. Ahmed, I. A. Khan, and N. Minhaj, “Novel electronically tunable C-multipliers,” Electronics Letters, vol. 31, no. 1, pp. 9-11, 1995. [6] E. Alaybeyoglu, and H. Kuntman, “Capacitor multiplier with high multiplication factor for integrated low pass filter of biomedical applications using DTMOS technique,” AEU-International Journal of Electronics and Communications, vol. 107, pp. 291-297, 2019. [7] D. Biolek, J. Vavra, and A. U. Keskin, “CDTA-based capacitance multipliers,” Circuits, Systems, and Signal Processing, vol. 38, no. 4, pp. 1466-1481, 2019. [8] A. S. Sedra, and K. Smith, “A second-generation current conveyor and its applications,” IEEE Transactions on circuit theory, vol. 17, no. 1, pp. 132-134, 1970. [9] A. Yesil, E. Yuce, and S. Minaei, “Grounded capacitance multipliers based on active elements,” AEU-International Journal of Electronics and Communications, vol. 79, pp. 243-249, 2017. [10] O. Cicekoglu, “New current conveyor based active-gyrator implementation,” Microelectronics Journal, vol. 29, no. 8, pp. 525-528, 1998. [11] A. A. Khan, S. Bimal, K. K. Dey, and S. S. Roy, “Current conveyor based R- and C- multiplier circuits,” AEUInternational Journal of Electronics and Communications, vol. 56, no. 5, pp. 312-316, 2002. [12] R. Verma, N. Pandey, and R. Pandey, “Novel CFOA based capacitance multiplier and its application,” AEUInternational Journal of Electronics and Communications, vol. 107, pp. 192-198, 2019. [13] A. Toker, O. Cicekoglu, and H. Kuntman, “New active gyrator circuit suitable for frequency-dependent negative resistor implementation,” Microelectronics Journal, vol. 30, no. 1, pp. 59-62, 1999. [14] A. Fabre, “Gyrator implementation from commercially available transimpedance operational amplifiers,” Electronics Letters, vol. 28, no. 3, pp. 263-264, 1992. [15] E. Yuce, and S. Minaei, “A modified CFOA and its applications to simulated inductors, capacitance multipliers, and analog filters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 1, pp. 266-275, 2008. [16] I. Myderrizi, and A. Zeki, “Electronically tunable DXCCII-based grounded capacitance multiplier,” AEUInternational Journal of Electronics and Communications, vol. 68, no. 9, pp. 899-906, 2014. [17] M. A. Al-Absi, E. S. Al-Suhaibani, and M. T. Abuelma’atti, “A new compact CMOS C-multiplier,” Analog Integrated Circuits and Signal Processing, vol. 90, no. 3, pp. 653-658, 2017.
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[18] A. Fabre, O. Saaid, F. Wiest, and C. Boucheron, “High frequency applications based on a new current controlled conveyor,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 43, no. 2, pp. 82-91, 1996. [19] E. Yuce, and S. Minaei, “Universal current‐mode filters and parasitic impedance effects on the filter performances,” International Journal of Circuit Theory and Applications, vol. 36, no. 2, pp. 161-171, 2008. [20] AD844 60MHz Monolithic Op amp, http://www.analog.com/ static/ imported-files/data_ sheets / AD844.pdf. [21] E. Yuce, R. Verma, N., Pandey, and S. Minaei, “New CFOA-based first-order all-pass filters and their applications,” International Journal of Electronics and Communications (AEU), vol. 103, pp. 57-63, 2019. [22] M. Dogan, and E. Yuce, “Supplementary single active device based grounded immittance function simulators,” International Journal of Electronics and Communications (AEU), vol. 94, pp. 311-321, 2018. [23] S. Topaloglu, M. Sagbas, and F. Anday, “Three-input single-output second-order filters using current-feedback amplifiers,” International Journal of Electronics and Communications (AEU), vol. 66, pp. 683-686, 2012. [24] R. K. Sharma, and R. Senani, “Multifunction CM/VM biquads realized with a single CFOA and grounded capacitors,” International Journal of Electronics and Communications (AEU), vol. 57, pp. 301-308, 2003. [25] W. Tangsrirat, and W. Surakampontorn, “Single-resistance-controlled quadrature oscillator and universal biquad filter using CFOAs,” International Journal of Electronics and Communications (AEU), vol. 63, pp. 1080-1086, 2009. [26] S. S. Gupta, D. R. Bhaskar, and R. Senani, “New voltage controlled oscillators using CFOAs,” International Journal of Electronics and Communications (AEU), vol. 63, pp. 209-217, 2009. [27] A. Lahiri, W. Jaikla, and M. Siripruchyanun, “Explicit-current-output second-order sinusoidal oscillators using two CFOAs and grounded capacitors,” International Journal of Electronics and Communications (AEU), vol. 65, pp. 669-672, 2011. [28] M. Dogan, and E. Yuce, “CFOA based a new grounded inductor simulator and its applications,” Microelectronics Journal, vol. 90, pp. 297-305, 2019. [29] E. Yuce, and O. Cicekoglu, “The effects of non-idealities and current limitations on the simulated inductances employing current conveyors,” Analog Integrated Circuits and Signal Processing, vol. 46, no. 2, pp. 103-110, 2006. [30] http://www.spicemodel.com/models/ad/AD844.htm.
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Authors’ name
Affiliation
Mehmet Dogan Pamukkale University Erkan Yuce Pamukkale University
12
S1434-8411(19)32389-1 https://doi.org/10.1016/j.aeue.2019.153034 AEUE 153034
To appear in:
International Journal of Electronics and Communications
Received Date: Revised Date: Accepted Date:
22 September 2019 11 December 2019 11 December 2019
Please cite this article as: M. Dogan, E. Yuce, A New CFOA Based Grounded Capacitance Multiplier, International Journal of Electronics and Communications (2019), doi: https://doi.org/10.1016/j.aeue. 2019.153034
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
© 2019 Published by Elsevier GmbH.
The second revised version of AEUE_2019_2308
A New CFOA Based Grounded Capacitance Multiplier Mehmet Dogan Pamukkale University, Department of Electrical and Electronics Engineering, 20160, Denizli, Turkey E-mail: [email protected]
Erkan Yuce* Pamukkale University, Department of Electrical and Electronics Engineering, 20160, Denizli, Turkey E-mail: [email protected]
*corresponding author Abstract: A new CFOA based grounded capacitance multiplier is proposed in this study. The proposed grounded capacitance multiplier that does not need any passive component matching conditions employs two CFOAs, a grounded capacitor and a couple of resistors. A number of frequency and time domain analyses for the proposed grounded capacitance multiplier are performed through the SPICE simulation program. During the simulations, ± 9 V supply voltages and a commercially available AD844 model are used. In addition to these, an experiment in time domain is made to validate the performance.
Keywords: CFOA; AD844; grounded capacitance multiplier. 1. Introduction The capacitance multipliers are needed for the integrated circuit (IC) process because large-valued capacitors occupy large areas on the chip. The purpose of the capacitance multipliers [1]-[17] is to obtain a large-valued equivalent capacitor from a small-valued capacitor. Until now, the capacitance multipliers have
been realized with various kinds of active elements for example OTAs [1]-[7], CCIIs [8]-[10], CFOAs [1], [11]-[15], DXCCII [16], etc. The capacitance multipliers proposed in [1]-[7] include OTA(s) which have restrictions at the high frequencies [18]. The capacitance multiplier developed in [1] possesses one grounded capacitor attached to series to X terminal of the CFOA. Therefore, it has limited high frequency performances [19]. The circuit of [5] also uses an operational amplifier that has slew-rate limitations. The capacitance multipliers presented in [8]-[10], [15] are realized with three AD844s [20]. Moreover, the capacitance multipliers reported in [2]-[4], [6], [7], [11], [12], [16], [17] employ a floating capacitor that is not suitable IC fabrication. The capacitance multiplier proposed in [13] includes a grounded resistor attached to series to the Z terminal. For this reason, its high frequency performance is poor [19]. The capacitance multiplier presented in [14] includes a grounded capacitor attached to series to X terminal. On the other hand, CFOA based circuits find wide application areas such as first-order all-pass filters [20], immittance function simulators [22], second-order filters [23][25], oscillators [25]-[27], etc. In this paper, a new grounded capacitance multiplier is proposed. The proposed circuit includes two CFOAs, one grounded capacitor and a couple of resistors. Any passive component matching constraints are not required for the proposed capacitance multiplier. Many frequency and time domain analyses for the proposed grounded capacitance multiplier are carried out through the SPICE program. During the simulations, ± 9 V supply voltages are chosen where AD844 model [18] is used. Moreover, an experiment in time domain is made in which ± 9 V supply voltages are chosen. The proposed grounded capacitance multiplier is illustrated in Section 2. In Sections 3 and 4, a number of simulation results and an experimental study for the proposed topology are respectively shown. A conclusion for the proposed circuit is finally given in Section 5.
2. The Proposed Grounded Capacitance Multiplier The CFOA can be explained in matrix equation (1). Moreover, its symbol is denoted in Fig. 1 while the CFOA with its parasitic impedances is depicted in Fig. 2.
VX I sC Y Y IZ 0 VW 0
RX
0 0 sCZ 1/ RZ
0
0
2
0 VY 0 I X 0 VZ RW IW
(1)
where the values of β, α and η are ideally one [28]. Furthermore, they are non-ideal gains. RX, RZ and RW are parasitic resistors while CZ and CY are parasitic capacitors. Ideally, RX, RW, CZ and CY are equal to zero while RZ is equal to infinity.
IX
VX
X
IY
VY
IW
CFOA W Z Y
VW
IZ
VZ Fig. 1. The circuit symbol of the CFOA.
CY
VY
Y
IY
CFOA VX
RX
IX
Z X
W
RW
IW
VW
RZ
IZ
CZ
VZ Fig. 2. The CFOA with its parasitic impedances. Without considering any non-idealities, the input impedance of the proposed capacitance multiplier in Fig. 3 is evaluated as Zin (s)
Vin 1 1 Iin sC 2R2 sCeq R1
(2)
Here, Ceq = 2CR2/R1. If non-ideal gains are taken into account, the input impedance of the proposed capacitance multiplier is computed as
3
R1
Vin
X
Z CFOA W (1) Y
Iin
Zin
R2
Y Z W CFOA (2) X
C
Fig. 3. The proposed grounded capacitance multiplier.
Zin (s)
1 1 (1 1 )sCR2 (1 1 )(11 2 ) 1 sCeq Req 12 11R1 111R1
(3)
In equation (3) given above, Ceq = (1+α1)CR2/(α1α2β1η1R1) and Req = α1β1η1R1/((1+α1)(β1η1 - β2)). From equation (3), quality factor (Q) of the proposed capacitance multiplier is found as Q Ceq Req
(4)
where ω = 2×π×f is an angular frequency. The proposed capacitance multiplier can be operated as a lossless capacitance multiplier (Q≥10) in the following frequency range:
f
10 1 2 Ceq Req
(5)
If only parasitic resistors of the X and W terminals of the CFOAs are considered, the input impedance of the proposed capacitance multiplier is calculated as Zin (s)
R 1 1 X1 Req 2 R2 RX 2 RW 1 2 sCeq sC R1 RX 1
(6)
where Ceq = 2C(R2+RX2+RW1)/(R1-RX1) and Req = RX1/2. As stated in [29], R1 must be chosen greater than RX1 for stable impedance. From equation (6), Q of the proposed capacitance multiplier is found as follows: Q
1 1 Ceq Req Ceq Req
4
(7)
The proposed capacitance multiplier can be operated as a lossless capacitance multiplier (Q≥10) in the following frequency range: f
1 1 10 2 Ceq Req
(8)
If only parasitic impedances of the Z and Y terminals of the CFOAs are considered, the input impedance of the proposed capacitance multiplier is evaluated as Zin (s)
R1RZ1RZ 2 as2 bs c
(9)
Here, a (C CY1 CY 2 CZ 2 )CZ1R1R2 RZ1RZ 2 b CZ1R1RZ1 (R2 RZ 2 ) (C CY1 CY 2 CZ 2 )R2 RZ 2 (R1 2RZ1 )
c R2 (R1 2RZ1 ) R1RZ 2
(10.a) (10.b) (10.c)
In equations (10), b and c must be greater than zero for stable impedance [29]. On the other hand, from equation (3), the passive and active sensitivities with respect to Ceq and Req are computed as follows: C
C
C
SC eq SR1eq SR2eq 1 C
S1eq C
1 1 1
C
C
S2eq S1eq S1eq 1 C
C
R
R
R
R
S 2eq S2eq SC eq S R2eq S 2eq S2eq 0 R
SR1eq 1, SR1eq R
R
R
1 1 1
S1eq S2eq S1eq
2 11 2
3. Simulation Results The proposed capacitance multiplier depicted in Fig. 3 is simulated through the SPICE program in which AD844 model [30] is utilized. Supply voltages are selected as ±9 V. Furthermore, R1= 1 kΩ, R2= 5 kΩ and C= 100 pF are selected as passive components resulting in Ceq= 1 nF (values of some parasitic impedances of the AD844 are RX ≅ 50 , RZ ≅ 3 M and CZ ≅ 5.5 pF). At 100 kHz, two separate sinusoidal input currents with peak-to-peak value of 1 mA are applied. Thus, ideal and simulation output voltages are shown in Fig. 4. An AC analysis for the proposed grounded capacitance multiplier is shown in Fig. 5. It is observed from Fig. 5 that the proposed capacitance multiplier has limitations at low and high frequencies due to parasitic impedances and non-ideal gains. After one hundred runnings, a Monte Carlo (MC) analysis is 5
achieved for the proposed capacitance multiplier where the values of all the passive components are uniformly changed by 5 %. Also, the result of the MC analysis is demonstrated in Fig. 6. Two resistors R1= 1 kΩ and R2= 5 kΩ are selected as constant values besides C= 100 pF, C= 75 pF, C= 50 pF and C= 25 pF are chosen as variable values. Therefore, Ceq are respectively found as 1 nF, 750 pF, 500 pF and 250 pF. AC analyses of the proposed circuit for different values of the capacitor are shown in Fig. 7. R1= 1 kΩ and C= 100 pF are selected as constant values besides R2= 10 kΩ, R2= 7.5 kΩ, R2= 5 kΩ and R2= 2.5 kΩ are chosen as variable values. Hence, Ceq are respectively obtained as 2 nF, 1.5 nF, 1 nF and 500 pF. AC analyses of the proposed capacitance multiplier for different values of R2 are demonstrated in Fig. 8. A comparison with AC analyses of this work and the capacitance multipliers in references [13] and [14] are denoted in Fig. 9 where Ceq is chosen as 1 nF. The power dissipation of each of the proposed capacitance multiplier and one in [14] is found as 233 mW while power consumption of the capacitance multiplier developed in [13] is found as 235 mW via the SPICE program. In addition, the capacitance multipliers in [13] and [14] like the proposed one are composed of two CFOAs, two resistors and a grounded capacitor.
Fig. 4. A time domain analysis for the proposed grounded capacitance multiplier.
6
Fig. 5. An AC analysis for the proposed grounded capacitance multiplier.
Fig. 6. A Monte Carlo analysis for the proposed grounded capacitance multiplier.
Fig. 7. AC analyses for the proposed grounded capacitance multiplier for different values of the capacitor. 7
Fig. 8. AC analyses for the proposed grounded capacitance multiplier for different values of the resistor R2.
Fig. 9. A comparison with AC analyses of this work and the circuits in references [13] and [14].
As stated by an anonymous reviewer, it is observed from the proposed capacitance multiplier given in Fig. 3 that if the capacitor, C has 0 V, the voltages at the Y terminals of both CFOAs will be 0 V. In addition, the voltages at the X terminals of both CFOAs are 0 V. However, the applied input current passes through the X and Z terminals of both CFOAs due to parasitic impedances of both CFOAs. As a result, input impedance of the proposed capacitance multiplier does not give any stability problems.
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4. Experimental Study An experiment is made for the proposed capacitance multiplier with three AD844s (one AD844 is used to obtain a current source), three resistors (one resistor (R = 1 kΩ) attached to X terminal of the AD844 is used to obtain a current source) and one capacitor. Passive elements R1= 1 kΩ, R2= 4.7 kΩ, C= 100 pF resulting in Ceq= 940 pF and supply voltages are chosen as ± 9 V in the experiment. A sinusoidal input current with peak-to-peak of 720 µA (applied input voltage is about peak-to-peak 720 mV) at 20 kHz is applied to input of the proposed grounded capacitance multiplier. Consequently, the sinusoidal input voltage and the corresponding sinusoidal output voltage with peak-to-peak of 4.6 V at 20 kHz are indicated in Fig. 10. The experimental result shows that the proposed grounded capacitance multiplier works well.
Fig. 10. The experimental result.
5. Conclusion A new grounded capacitance multiplier that is proposed in this paper contains two CFOAs, two resistors and one grounded capacitor. It does not need any passive component matching constraints. A non-ideality analysis is also given. An experiment and many simulations demonstrate that the proposed capacitance multiplier works well. There is an insignificant difference among ideal, experimental and simulation results because AD844s are not ideal active devices.
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Mehmet Dogan Pamukkale University Erkan Yuce Pamukkale University
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