Comparative evaluation of optical waveguides as alternative interconnections for high performance packaging

World Abstracts on Microelectronics and Reliability This paper will highlight the usefulness of the designing test patterns on this excess material, namely test coupons, in terms of how these can be used to monitor all of the manufacturing and assembly process steps. It will also show how these coupons can be used to make the board easier to assemble and how they may actually lead to an improvement in the quality of the assembly and an increase in production yields. Suggestions will be made as to the types of test pattern that can be used, as well as how these patterns can be utilised as process control checkers. Since the test coupons are incorporated in the board design, a quality check of 100% of the boards that are being processed is possible. This would highlight any board-toboard variation if it were present. It would also allow for destructive testing to be carried out, without damaging any of the working product. The applications of these patterns are wide ranging. They can be used to check bare board quality--etch definition, layer registration, plating quality, solder mask definition etc. They can also be used to monitor the assembly processes for SMT and conventional PTH assembly types--cut and clinch quality, paste printing quality, insertion accuracy, reflow/ flow soldering quality and assembly cleanliness, among others. Many of these applications are examined in this paper. Electrical design technology for low dielectric constant multilayer ceramic snbstrate. AKIHIROSASAKIand Yuzo SmMADA. IEEE Trans. Compan. Hybrids mfg Technol. 15, 56 (1992). High-speed electrical equipment systems, like large scale computers, demand new packaging style technology to meet high propagation speed, high wiring density, and high frequency pulse requirements for a multichip substrate. A very important property of substrate materials for microelectronic packaging with high propagation speed is an appropriate dielectric constant. The VLSI demand will require even higher transmission speed on the substrate, and the use of an even lower dielectric constant material system. From the viewpoint of substrate propagation delays, the key factor for reducing signal propagation delays is hollow structure design between ground plane and signal plane, as well as the low dielectric constant material around signal lines. The reason is that space between signal lines and the ground plane is able to reduce a practical propagation delay constant. Another important factor for transmission properties is the ground plane design. The reason is that pulse transmission properties are greatly influenced by configuration ground plane and wiring plane that is used, such as: ground mesh size and ground plane open area. Therefore, test samples regarding a new kind of packaging were made for estimation and basic properties which were measured. From this estimation, characteristics for a new kind of packaging substrate are summarized. (1) Low propagation delay time (3.9ns m -I) can be realized by using a hollow strip line structure ceramic substrate with a 4.4. material dielectric constant. (2) Electric design, which can control characteristic impedance and crosstalk coupling noise, is realized for the hollow strip line structure. (3) Electric design, which can control propagation delay time, is realized. (4) Ground plane design, which can stabilize characteristic impedance, is realized. As a result, this new structure substrate, with low dielectric constant, has sufficient possibility to be applied to high-speed VLSI packages in the future. New packaging of a chip on a board by a unique printing method. ATSUSHI OKUNO et al. IEEE Trans. Compon. Hybrids mfg Technol.15, 73 (1992). Transfer molding is a typical method for packaging integrated circuits (ICs). However, transfer molding is very difficult to do at heights of less than 1 ram, and has a limited surface mounting area.

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Recent research of high density surface mounting for thinner and lighter weight packaging has progressed for both IC cards and liquid crystal displays (LCDs). In surface mounting, all plural large scale integration (LSI) circuits are attached to the substrate, then connected with wire bonding and encapsulated with an epoxy resin. As already reported, encapsulation is performed by dropping a liquid epoxy resin on an IC through a dispensing apparatus. However, the dispensing method has many problems, such as the height variations of the coating, difficulties of uniform spreading on large size ICs, and one-by-one encapsulation. This paper describes a unique printing method we developed to solve such problems. Through this method it is possible to achieve a height less than 1 mm and a uniform thickness on an integrated system. On reaching these parameters, the surface mount ICs replace molded packaged devices that are manufactured using expensive equipment and molding dies. Also, our method requires only a small amount of epoxy resin and is, therefore, more economical than the conventional transfer molding process. We developed a one component epoxy resin--NPR- 150-suitable for printing. To date, deformations of gold wire have not been observed and the reliability test results are equal to the conventional transfer molding packaging's results. We expect that this method will be applied to meet industry demands for light weight and small size products including IC cards, lap-top computers, video-cameras and LCDs for colour televisions. Modeling of multilevel structures: a general method for analyzing stress evolution daring processing. ARTURO O. CI~.rENT~ and IQBALA. SHAREEF. IEEE Trans. Semicond. mfg 5, 128 (1992). This paper presents a general modeling technique for following the evolution of the stress field during the manufacturing of multilevel structures. This technique combines the finite element method with a modeling strategy that uses artificial nodes to simulate material interfaces. It can be applied to both linear and nonlinear structures. The main advantage of this approach is that it allows one to account for all topological and geometric changes during the manufacturing process, as well as the residual stresses introduced at each stage. Its implementation is very straightforward since it is compatible with current finite element technology and most commercial codes. The usefulness of this technique is illustrated with an example concerning an encapsulated copper line. Comparative evaluation of optical waveguides as alternative interconnections for high performance packaging. S. E. SCHACHAMet al. IEEE Trans. Compan. Hybriak mfg Technol. 15, 63 (1992). The well-known advantages of optical interconnections include high carrier frequency, low attenuation, high noise immunity, and, in ideal guides, low cross talk. In this paper, a detailed comparison between optical and electrical interconnections is presented, with the emphasis on advantages and drawbacks of optical link utilization. The impact of attenuation, dispersive degradation, and fan out on signal integrity is discussed. Reflections from discontinuities are taken into account in the section on fan out, but the issue of reflection is omitted in the remainder of the paper, not because it is unimportant, but because these reflections do not give either system an advantage. If anything, reflections are more troublesome in optical waveguide circuits than in electrical circuits. Bends in optical waveguides cannot exceed the limitations imposed by the index difference which precludes the extent of abrupt bends that mimic corners or vias in electrical interconnections. According to our results, there is no obvious advantage of using optical interconnections for the distribution of digital signals containing significant frequency components in excess of 10 GHz, unless substantial distances are involved, for

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which low dispersion optical waveguides could provide a solution. The actual electrical digital signal speeds for which suitable interconnections can be provided still depend as much on the skill of the designer as on the availability of materials or processes. Therefore, in high-speed digital systems, a detailed study has to be performed on the entire system before a decision is made as to which interconnection scheme is superior for a given application. Moreover, the reduction of the number of lines and ports by multiplexing and demultiplexing is limited by the electronics, for both electrical and optical approaches. Retention of waveform amplitude and integrity and tolerance of cross talk eventually become the key parameters that force the transition to the optical channel at ultra-high digital speeds. Approaching tens of picosecond rise time, dispersion and attenuation of electrical signals is detrimental, while optical waveforms are basically unaffected in low dispersion waveguides, making the transition to optical interconnections essential. The implementation of a polyimide optical waveguide in the MCNC package is discussed.

Polyamic alkyi esters: versatile polyimide precursors for improved dielectric coatings. WILLI VOLKSEN,Do Y. YOON and JAMESL. HENDRICK. IEEE Trans. Compon. Hybrids mfg Technol.15, 107 (1992). The derivatization of the pendant acid moieties along the poly(amic acid) backbone in the form of alkyl ester groups provides a unique solution to the hydrolytic instability associated with the traditional polymide precursors and offers additional benefits in the form of increased synthetic flexibility as well as a more desirable imidization behaviour. These improvements are a direct result of eliminating the "monomer-polymer" equilibrium associated with poly(amic acids). In the absence of hydrolytic instability, it is now possible to utilize an aqueous work-up of the polyimide precursor. This presents an attractive synthetic pathway for well-defined, amineterminated oligomers, which can then be formulated to yield low molecular weight, chain-extendable polyimide precursors. Furthermore, the higher imidization temperatures offered by the "amic alkyl ester" chemistry allows for more efficient chain extension prior to imidization. In the case of segmented copolyimides, the same features permit the extraction of the material with a suitable solvent to remove any homopolymer contamination as well as the development of a well-defined morphology. Alternatively, the lack of monomer randomization reactions offers the possibility to prepare polyimide blends, a very attractive and economical means of polymer modification. Packaging of GaAs signal processors on multichip modules. BARRY K, GILBERT and GEORGE W. PAN. IEEE Trans. Compon. Hybrids mfg Technol. 15, 15 (1992), Deposited multichip modules (MCM-Ds) are in their infancy for use with conventional CMOS-based digital computing systems operating at 100 MHz clock rates, and even more immature from the perspective of high clock rate silicon ECL and GaAs-based processors operating at hundreds of megahertz or low gigahertz clock rates. In this paper, we discuss the extensions to the MCM-D fabrication technology, and to the design and layout of these structures, which will have to be made to accommodate high clock rate ECL and GaAs digital integrated circuits. Techniques for attachment of the high clock rate chips to the MCM-Ds will be discussed including wire bond, tape automated bond (TAB), flip-chip solder attachment, and flip adhesives; the trade-offs between these different approaches will be noted. Electrical issues which must be addressed include minimizing signal amplitude losses in the small cross section interconnects typical of MCM-Ds, minimization of interline cross talk through proper layout and design rules, provision of integral thin film termination resistors of excellent electrical quality, and the provision of integral decoupling capacitors to suppress inductively generated noise on the power and ground planes.

The problem of launching fast rise time, wide bandwidth signals onto and retrieving such signals from the MCM-Ds will be noted. The thermal problems associated with the packing of 10-50 high power dissipation chips onto such small structures will be discussed, along with methods of removing such high levels of heat by changes in materials incorporated into the stacked structures. Finally, several MCM-D design and fabrication projects under way at the Mayo Foundation in collaboration with corporate partners which attempt to address and solve some of the problems cited above will be described, along with some of the initial results of these studies.

Microcarrier for LSI chip used in the HITAC M-880 processor group. TAKASmINOUEet al, IEEE Trans. Compon. Hybrids rnfg Technol.15, 7 (1992). The compact chip carrier named MCC has been developed for high density chip level packaging. The MCC realizes the possible smallest hermetic chip package by introducing full surface flip-chip interconnections, thin film process technology, built-in termination resistors, and a thermal expansion matched ceramic substrate. This paper reports on the structure of the MCC and particularly on the film process technology for its fabrication. Analogue and mixed-signal IC design. ROB MASSARA and KEVIN STEPTOE. IEEE Rev. 75 (February 1992). Implementing analogue functions on ICs is getting easier, creating a booming market for analogue ASICs. Resistance computations for multilayer packaging structures by applying the boundary element method. RuEY-B~I Wu. IEEE Trans. Compon. Hybrids mfg Technol. 15, 87 (1992). A boundary element formulation together with the moment method analysis is proposed to find the equivalent multiport d.c. resistances for packaging structures consisting of uniform conducting plates with arbitrarily shaped boundaries. Incorporated with a new equiangie division scheme and exact integration formulas, this approach is very efficient in the usage of computer storage and computation time such that many practical structures can be dealt with even by a small personal computer. The method is employed to investigate the effect on the equivalent resistances due to the presence of the interior apertures and the exterior boundary. Also presented are the resistance modeling technique for the multilayer packaging structures, and a novel cut and fill technique to estimate the resistances of complicated structures. Advanced ultrapure wafer systems with low dissolved oxygen for native oxide free wafer processing. YASUVUKIYAGI et al. IEEE Trans. Semicond. mfg 5, 121 (1992). In the manufacture of submicron or deep submicron ULSIs, it is important to completely suppress native oxide growth on the silicon wafer surface. Especially, in order to suppress the native oxide growth in a wet process, dissolved oxygen must be removed from the ultrapure water uced for the final rinsing of the wafer. Two independent systtms for the supply of ultrapure water, augmented with new techniques to remove dissolved oxygen, have been ins ailed in the mini-superclean room at Tohoku University. Both systems use two-stage dissolved oxygen removing methods. System 1 uses vacuum degassing through membrane and catalytic resin-based reduction, while System 2 uses vacuum degassing through membrane and nitrogen gas bubbling. Both systems can supply ultrapure water of 10 ppb or less in dissolved oxygen concentration. The concentrations of other impurities such as TOC, silica and total residue are also 1 ppb or less. Particle deposition and removal in wet cleaning, processes for ULSI manufacturing. MITSUSm ITANO et aL IEEE Trans. Semicond. mfg 5, 114 (1992). Particle deposition on