- Email: [email protected]
Comparison of different on-chip ESD protection structures in a 0.35 μm CMOS technology
Microelectron. Reliab., Vol. 37, No. 10/1 I, pp. 1537-1540, 1997 © 1997 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026-2714/97 $17.00 + 0.00
Pergamon
Pll: S 0 0 2 6 - 2 7 1 4 ( 9 7 ) 0 0 1 0 3 - 0
COMPARISON OF DIFFERENT ON-CHIP ESD PROTECTION STRUCTURES IN A 0.35 lxm CMOS TECHNOLOGY C.RICH--IER (I), NaMAENE (2), G.MABBOUX (I), R.BELLENS (2) (I) SGS-THOMSON, 850 rue J.Monnet, BPI6, 38921 Crolles cedex, France (2) Alcatel Telecom, l Francis Wellesplein, 2018 Antwerpen, Belgium.
Abstract: In nowadays submicron technologies, Electrostatic Discharges (ESD) are one of the major threat for the reliability of ICs. The aim of this paper is to demonstrate that a very good ESD protection level can be achieved provided we can insure a uniform triggering of multifmger NMOS protection devices. This can be done by a gate coupling to the drain, either by a capacitance or by a zener diode. Human Body Model (I-IBM) and Charged Device Model (CDM) test results, as well as Transmission Line Measurement (TLM) and light emission results suppon this finding. © 1997 Elsevier Science Ltd INTRODUCTION Electrostatic Discharges (ESD) are one of the bigger concerns for the reliability of I t s in nowadays submicron technologies. The reduction in dimensions, as well as process options are well known to be detrimental to the ESD robustness [ 1]. Thus, the ESD protection of ICs is becoming a real challenge as we are scaling down towards deep-submicron technologies. Basically two approaches can be found to protect I/O buffers. One is to make the output transistor self-protecting: a special ESD implant [2] as well as silicide blocking are then required, adding an extra cost to the process. The other one is to add an extra protection device to the I/O pad, such as diodes, NPN devices (Field devices or NMOS) or thyristors [1].We choose to use this second solution. This paper presents a comparison between various ESD damps. Human Body Model (I-IBM) and Charged Device Model (CDM) behavior of these clamps, as well as dynamic I(V) characteristics measured by the transmission line pulsing technique (TLP) have been investigated. TEST STRUCTURES The test structures used throughout this study have been fabricated with a general purpose, live metal levels, silicided diffusion 0.35 lira LDD CMOS process. Several protection devices have been considered. The first one is a Field oxide gateless MOSFET (FIVIOS) with a minimum 0.7 ltm channel length while the second one is a Grounded gate thin oxide, N-channel MOSFET (GGNMOS). For this latter device, a NLDD blocking mask was used, so that GGNMOS with and without LDD were available. Two different implementations of a gate coupled NMOS have been evaluated. Both versions have a resistor between the NMOS gate and the grounded substrate, while the coupling of the NMOS gate to the drain is performed in two different ways: the 1537
1538
C. Richier et al.
first protection uses the capacitive coupling of the p+ to nwell junction diode (CCNMOS), while the second clamp takes advantage of the early breakdown of a zener diode (ZCNMOS). No additional process step is needed for this umer as it makes use of the NLDD doping, standard in this process. HBM AND TLP RESULTS
Experimental procedure The elementary devices have been stressed according to norm MIL STD 883C 3015.7, by using a manual IMCS700 t e a r . Prior and after any stress, the leakage current of the devices pads was measured with an HP4145B semiconductor parameter analyzer. As a failure criterion, an increase of the leakage current above 100 nA at 3.6 V (supply voltage +10%) was considered. The ESD failure voltage will be called Vesd in the following pages. Results on elementary devices
Field MOS and GGNMOS. A nearly linear width dependency was observed for Vesd on single fingers FMOS and GGNMOS devices. If we express Vesd per device active width, we obtain 22V / lun for No LDD GGNMOS, 20 V / lun for LDD GGNMOS, and 15 V / for FMOS. For two source fingers devices, there is a large spread in the HBM results, due to triggering problem: only one finger may be triggered into snapback, leading to a degradation of the ESD robusmess by a factor 2 (see Figure 1). TLP measurements [5] (see Figure 2) explained these I-IBM results. The triggering voltage (VT1) of the devices (cf table 1) is too high and the resistance in snapback region is not high enough to insure that if one finger is triggered into snapback, the voltage drop across this finger reaches VT1 again before it is damaged Capacitively coupled NMOS structure. The junction diode triggered NMOS structures (CCNMOS) showed an improvement on ESD performance compared to a similar GGNMOS, but the spreading is still too large. The design needs to be further optimized for a larger feedthrough capacitance ratio, resulting in a longer lime period during which the gate is puiledup [6]. Zener triggered NMOS c/amp. This third protection structure is found to be the optimal one. Both TLP and HBM test results show that the ESD performance of the zener triggered NMOS scales with the total width and has a HBM performance of 22 V/3un, as shown on figure 1. TLP measurements show that the gate coupling results in a lower triggering voltage Vtl of the nlm bipolar of the NMOS clamp transistor, compared to the GGNMOS case as described in literature [6].When the voltage on the pad reaches the zener breakdown voltage, then the NMOS gate is transiently pulled up during the stress and the MOS action results in a higher substrate current compared to the Grounded gate case. This facilitates the bipolar turn-on, and results in a more uniform triggering of multifinger NMOS transistors. Comparison TLP&HBM Results. The tablel hereafter summarizes the TLP and HBM data obtained on different clamps. It2 values between 9-10.5 mA / ~ have been measured. It has to be noted that TLP I(V) curves do not show a real second snapback to low voltage as often reported in the literature [2,6,7]. The TLP curves in reference 8 also show a rather weak second snapback, more in line with our measurements. This ~non catastrophic drop to a lower voltage~ may be explained by a localized failure, while the current is supported by the whole structure. A catastrophic drop would occur for total destruction of the devices (nearly for a shortcircui0. In literature, a contradiction has been reported between references [2][7][8], which show a good correlation between HBM and TLP and reference 9 which shows a potential discrepancy due to the rise time of the HBM signal. In our case, a good correlation was obtained as the HBM
1539
On-chip ESD Protection structures
~
~ II
~
~
y
L6 ~
~ ' ~
~.. 3.5
Singlefinger
De/~ble~ngen
7
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/
/
I
2.5
6
M
w:2.,75,
°~
~ 1,5
W=175 ~m
~~j"
3 2 I
- -
0
50
I00
150
2
250 3 (urn)
Activewidth
350
400
0.i 0
"
1 o
-- W=I00 ~m
2
4
6 $ 10 V device (V)
W=50 tun 12
14
Figures 1 &2: I k p m d e m y of minimum HBM Vead (kV) veal'us W for GGNMOS, ZCNMOS. T I P measurements for No-LDD GGNMOS (Lffi0.35lun, DSffi3 pro) without any tri~ problems in this particularcase.
Proteoions "No-LDD GGNMOS (50/0.35) No-LDD GGNMOS (100/0.35) No-LDD GGNMOS (175/0.35) No-LDD GGNMOS (2"175/0.35) LDD GGNMOS(175/0.7) CCNMOS (2"125/0.4) ZCNMOS(2*125 tun/0.4) ZCNMOS(2*150 ran/0.4) FMOS (175/0.7)
Vtl C¢')
Vsb(V)
It2 (A)
Vesd (kV)
9 9 9 9 9.7 7.8-8.7 7.1-7.7 7.2-7.4 10.7-10.9
4.8-5 4.8-5 4.8-5 4.8-5 5.9-6.1 5-5.2 5-5.1 5-5.2 5.9-6.3
0.525 1.013 1.62 3.25 1.51 2.5-3 2.7-2.9 2.78 1.18
1.5 2.5 4 4 or 7 3.5 3 or 5.5 5.5 6 2.5
CDM RESULTS The samples werepackaged in DIL28 and a failure criterion of 1 [email protected] V was chosen. Except for the $~gzzal]estdim~kqiOll$(W< 175 I~m for GGNMOS), all the tested samples exceed the pet-formance of the tester (4+ 1500V). Various I/O cells have been tested, with either a GGNMOS or a dynamically triggered NMOS (CCNMOS or ZCNMOS, with 200 urn minimum width) as Pad/ Vss protection and ZCNMOS as Vdd/Vss clamp. No CDM failure up to 1500V has been detected on these I/Os. Nevertheless we have to take care that these resultscarmot be generalized directly for ASIC VLSI designs, due to core circuitry sensitivity and parasitic effects of the inter-
(L,C,R). LIGHT EMISSION Light emission was performed on failed sampl~ in order to identify failure sites. The emission site oblained confirms I-IBM results. When trigsering problems occur, only one finger is damaged (see Hg3). With uaiform uiggering, bath angen am damaged. Figme 4 shews a 2"175 tun No-LDD GGNMOS without any triggering problems in this pa~cular case.
16
1540
C. Richier et al.
Figures 3 & 4:Light emission for 2"175 Ixrn wide FMOS (Only the bottom finger shows emission spots) and for 2"175 lain wide No LDD GGNMOS without triggering problem in this case.(Both fingers show emission spots) CONCLUSIONS In this paper we investigated the Human Body and Charged Device behavior of a FMOS, GGNMOS with/without LDD, and dynamically triggered NMOS in a 0.35 lain p-substrate CMOS process. We reported very good HBM results of 22 V / Ixm width and CDM performances beyond the tester limit for the dynamically coupled and No-LDD GGNMOS (W>175 lain). The gate coupling improves the width scaling for HBM performance compared to GGNMOS. The transmission line pulsing technique was used on some samples, and confirms the ESD HBM results. The triggering voltage of the protection can be drastically decreased from 9 V for a GGNMOS transistor down to 7.1-7.7 V for a zener triggered clamp, leading to a better triggering of multifinger structures. A good correlation was obtained between the TLP current leading to a degradation of the devices (It2 value) and the HBM results. It2 values between 9-10.5 mA/Ixm width were obtained. Emission light measurements confirm the previous results: only one finger is damaged when triggering problem occurs. Finally, gate coupled devices were used as I/O pad protections and very good ESD protection level were obtained for HBM as well as for CDM tests.J10] ACKNOWLEDGMENTS The authors would like to thank Mr. C.Leroux and Mr. P.Salome from LETI, B.Keppens and K.H. Bock from IMEC (within IWT frame) for their support in TLP and fruitful discussion. REFERENCES 1. C.Duvvury, A.Amerasekera, Semiconductor Science Technology, vol 11 (1996), pp 833- 850. 2. C.Diaz, T.Kopley, P.Marcoux, IRPS95, pp 276-283. 3. R. Rountree, IEEE on Electron Devices, vol ED-32, no 5, May 85. 4. K.Ve~aege and al, ESREF95. 5. T.Maloney, N.Khurana, EOS/ESD Symposium 1985, p 49 6. C.Duvvury, C.Diaz, IRPS92, pp 141-150. 7. T.Polgreen, A.Chatterjee, <<,EOS/ESD Symposium 1989, lap 167-174. 8. C.Jiang, E.Nowak, M. Manley, IRPS 96, pp233-236. 9. C.Musshoff and al, Proceedings of ESREF 96 (1996), pp 1743- 1746. 10. C.Richier, N.Maene,G.Mabboux, R.Bellens, to be published in EOS/ESD Symposium 1997.
Pergamon
Pll: S 0 0 2 6 - 2 7 1 4 ( 9 7 ) 0 0 1 0 3 - 0
COMPARISON OF DIFFERENT ON-CHIP ESD PROTECTION STRUCTURES IN A 0.35 lxm CMOS TECHNOLOGY C.RICH--IER (I), NaMAENE (2), G.MABBOUX (I), R.BELLENS (2) (I) SGS-THOMSON, 850 rue J.Monnet, BPI6, 38921 Crolles cedex, France (2) Alcatel Telecom, l Francis Wellesplein, 2018 Antwerpen, Belgium.
Abstract: In nowadays submicron technologies, Electrostatic Discharges (ESD) are one of the major threat for the reliability of ICs. The aim of this paper is to demonstrate that a very good ESD protection level can be achieved provided we can insure a uniform triggering of multifmger NMOS protection devices. This can be done by a gate coupling to the drain, either by a capacitance or by a zener diode. Human Body Model (I-IBM) and Charged Device Model (CDM) test results, as well as Transmission Line Measurement (TLM) and light emission results suppon this finding. © 1997 Elsevier Science Ltd INTRODUCTION Electrostatic Discharges (ESD) are one of the bigger concerns for the reliability of I t s in nowadays submicron technologies. The reduction in dimensions, as well as process options are well known to be detrimental to the ESD robustness [ 1]. Thus, the ESD protection of ICs is becoming a real challenge as we are scaling down towards deep-submicron technologies. Basically two approaches can be found to protect I/O buffers. One is to make the output transistor self-protecting: a special ESD implant [2] as well as silicide blocking are then required, adding an extra cost to the process. The other one is to add an extra protection device to the I/O pad, such as diodes, NPN devices (Field devices or NMOS) or thyristors [1].We choose to use this second solution. This paper presents a comparison between various ESD damps. Human Body Model (I-IBM) and Charged Device Model (CDM) behavior of these clamps, as well as dynamic I(V) characteristics measured by the transmission line pulsing technique (TLP) have been investigated. TEST STRUCTURES The test structures used throughout this study have been fabricated with a general purpose, live metal levels, silicided diffusion 0.35 lira LDD CMOS process. Several protection devices have been considered. The first one is a Field oxide gateless MOSFET (FIVIOS) with a minimum 0.7 ltm channel length while the second one is a Grounded gate thin oxide, N-channel MOSFET (GGNMOS). For this latter device, a NLDD blocking mask was used, so that GGNMOS with and without LDD were available. Two different implementations of a gate coupled NMOS have been evaluated. Both versions have a resistor between the NMOS gate and the grounded substrate, while the coupling of the NMOS gate to the drain is performed in two different ways: the 1537
1538
C. Richier et al.
first protection uses the capacitive coupling of the p+ to nwell junction diode (CCNMOS), while the second clamp takes advantage of the early breakdown of a zener diode (ZCNMOS). No additional process step is needed for this umer as it makes use of the NLDD doping, standard in this process. HBM AND TLP RESULTS
Experimental procedure The elementary devices have been stressed according to norm MIL STD 883C 3015.7, by using a manual IMCS700 t e a r . Prior and after any stress, the leakage current of the devices pads was measured with an HP4145B semiconductor parameter analyzer. As a failure criterion, an increase of the leakage current above 100 nA at 3.6 V (supply voltage +10%) was considered. The ESD failure voltage will be called Vesd in the following pages. Results on elementary devices
Field MOS and GGNMOS. A nearly linear width dependency was observed for Vesd on single fingers FMOS and GGNMOS devices. If we express Vesd per device active width, we obtain 22V / lun for No LDD GGNMOS, 20 V / lun for LDD GGNMOS, and 15 V / for FMOS. For two source fingers devices, there is a large spread in the HBM results, due to triggering problem: only one finger may be triggered into snapback, leading to a degradation of the ESD robusmess by a factor 2 (see Figure 1). TLP measurements [5] (see Figure 2) explained these I-IBM results. The triggering voltage (VT1) of the devices (cf table 1) is too high and the resistance in snapback region is not high enough to insure that if one finger is triggered into snapback, the voltage drop across this finger reaches VT1 again before it is damaged Capacitively coupled NMOS structure. The junction diode triggered NMOS structures (CCNMOS) showed an improvement on ESD performance compared to a similar GGNMOS, but the spreading is still too large. The design needs to be further optimized for a larger feedthrough capacitance ratio, resulting in a longer lime period during which the gate is puiledup [6]. Zener triggered NMOS c/amp. This third protection structure is found to be the optimal one. Both TLP and HBM test results show that the ESD performance of the zener triggered NMOS scales with the total width and has a HBM performance of 22 V/3un, as shown on figure 1. TLP measurements show that the gate coupling results in a lower triggering voltage Vtl of the nlm bipolar of the NMOS clamp transistor, compared to the GGNMOS case as described in literature [6].When the voltage on the pad reaches the zener breakdown voltage, then the NMOS gate is transiently pulled up during the stress and the MOS action results in a higher substrate current compared to the Grounded gate case. This facilitates the bipolar turn-on, and results in a more uniform triggering of multifinger NMOS transistors. Comparison TLP&HBM Results. The tablel hereafter summarizes the TLP and HBM data obtained on different clamps. It2 values between 9-10.5 mA / ~ have been measured. It has to be noted that TLP I(V) curves do not show a real second snapback to low voltage as often reported in the literature [2,6,7]. The TLP curves in reference 8 also show a rather weak second snapback, more in line with our measurements. This ~non catastrophic drop to a lower voltage~ may be explained by a localized failure, while the current is supported by the whole structure. A catastrophic drop would occur for total destruction of the devices (nearly for a shortcircui0. In literature, a contradiction has been reported between references [2][7][8], which show a good correlation between HBM and TLP and reference 9 which shows a potential discrepancy due to the rise time of the HBM signal. In our case, a good correlation was obtained as the HBM
1539
On-chip ESD Protection structures
~
~ II
~
~
y
L6 ~
~ ' ~
~.. 3.5
Singlefinger
De/~ble~ngen
7
/
/w
/
/
I
2.5
6
M
w:2.,75,
°~
~ 1,5
W=175 ~m
~~j"
3 2 I
- -
0
50
I00
150
2
250 3 (urn)
Activewidth
350
400
0.i 0
"
1 o
-- W=I00 ~m
2
4
6 $ 10 V device (V)
W=50 tun 12
14
Figures 1 &2: I k p m d e m y of minimum HBM Vead (kV) veal'us W for GGNMOS, ZCNMOS. T I P measurements for No-LDD GGNMOS (Lffi0.35lun, DSffi3 pro) without any tri~ problems in this particularcase.
Proteoions "No-LDD GGNMOS (50/0.35) No-LDD GGNMOS (100/0.35) No-LDD GGNMOS (175/0.35) No-LDD GGNMOS (2"175/0.35) LDD GGNMOS(175/0.7) CCNMOS (2"125/0.4) ZCNMOS(2*125 tun/0.4) ZCNMOS(2*150 ran/0.4) FMOS (175/0.7)
Vtl C¢')
Vsb(V)
It2 (A)
Vesd (kV)
9 9 9 9 9.7 7.8-8.7 7.1-7.7 7.2-7.4 10.7-10.9
4.8-5 4.8-5 4.8-5 4.8-5 5.9-6.1 5-5.2 5-5.1 5-5.2 5.9-6.3
0.525 1.013 1.62 3.25 1.51 2.5-3 2.7-2.9 2.78 1.18
1.5 2.5 4 4 or 7 3.5 3 or 5.5 5.5 6 2.5
CDM RESULTS The samples werepackaged in DIL28 and a failure criterion of 1 [email protected] V was chosen. Except for the $~gzzal]estdim~kqiOll$(W< 175 I~m for GGNMOS), all the tested samples exceed the pet-formance of the tester (4+ 1500V). Various I/O cells have been tested, with either a GGNMOS or a dynamically triggered NMOS (CCNMOS or ZCNMOS, with 200 urn minimum width) as Pad/ Vss protection and ZCNMOS as Vdd/Vss clamp. No CDM failure up to 1500V has been detected on these I/Os. Nevertheless we have to take care that these resultscarmot be generalized directly for ASIC VLSI designs, due to core circuitry sensitivity and parasitic effects of the inter-
(L,C,R). LIGHT EMISSION Light emission was performed on failed sampl~ in order to identify failure sites. The emission site oblained confirms I-IBM results. When trigsering problems occur, only one finger is damaged (see Hg3). With uaiform uiggering, bath angen am damaged. Figme 4 shews a 2"175 tun No-LDD GGNMOS without any triggering problems in this pa~cular case.
16
1540
C. Richier et al.
Figures 3 & 4:Light emission for 2"175 Ixrn wide FMOS (Only the bottom finger shows emission spots) and for 2"175 lain wide No LDD GGNMOS without triggering problem in this case.(Both fingers show emission spots) CONCLUSIONS In this paper we investigated the Human Body and Charged Device behavior of a FMOS, GGNMOS with/without LDD, and dynamically triggered NMOS in a 0.35 lain p-substrate CMOS process. We reported very good HBM results of 22 V / Ixm width and CDM performances beyond the tester limit for the dynamically coupled and No-LDD GGNMOS (W>175 lain). The gate coupling improves the width scaling for HBM performance compared to GGNMOS. The transmission line pulsing technique was used on some samples, and confirms the ESD HBM results. The triggering voltage of the protection can be drastically decreased from 9 V for a GGNMOS transistor down to 7.1-7.7 V for a zener triggered clamp, leading to a better triggering of multifinger structures. A good correlation was obtained between the TLP current leading to a degradation of the devices (It2 value) and the HBM results. It2 values between 9-10.5 mA/Ixm width were obtained. Emission light measurements confirm the previous results: only one finger is damaged when triggering problem occurs. Finally, gate coupled devices were used as I/O pad protections and very good ESD protection level were obtained for HBM as well as for CDM tests.J10] ACKNOWLEDGMENTS The authors would like to thank Mr. C.Leroux and Mr. P.Salome from LETI, B.Keppens and K.H. Bock from IMEC (within IWT frame) for their support in TLP and fruitful discussion. REFERENCES 1. C.Duvvury, A.Amerasekera, Semiconductor Science Technology, vol 11 (1996), pp 833- 850. 2. C.Diaz, T.Kopley, P.Marcoux, IRPS95, pp 276-283. 3. R. Rountree, IEEE on Electron Devices, vol ED-32, no 5, May 85. 4. K.Ve~aege and al, ESREF95. 5. T.Maloney, N.Khurana, EOS/ESD Symposium 1985, p 49 6. C.Duvvury, C.Diaz, IRPS92, pp 141-150. 7. T.Polgreen, A.Chatterjee, <<,EOS/ESD Symposium 1989, lap 167-174. 8. C.Jiang, E.Nowak, M. Manley, IRPS 96, pp233-236. 9. C.Musshoff and al, Proceedings of ESREF 96 (1996), pp 1743- 1746. 10. C.Richier, N.Maene,G.Mabboux, R.Bellens, to be published in EOS/ESD Symposium 1997.