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Holding voltage investigation of advanced SCR-based protection structures for CMOS technology
Microelectronics Reliability 47 (2007) 1444–1449 www.elsevier.com/locate/microrel
Holding voltage investigation of advanced SCR-based protection structures for CMOS technology A. Tazzoli
a,*
, F.A. Marino a, M. Cordoni b, A. Benvenuti b, P. Colombo b, E. Zanoni a, G. Meneghesso a a
DEI, University of Padova, Via Gradenigo 6/B, 35131 Padova, Italy b STMicroelectronics, Agrate Brianza (Mi), Italy Received 6 July 2007 Available online 4 September 2007
Abstract A new silicon-controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially destroy the loop feedback gain of the two main npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage during the ESD event. A strong dependence of the holding voltage with the ESD pulse width has also been observed, caused by self-heating effects. 2D-device simulations (DESSIS Synopsys) have been performed obtaining results that perfectly fit the measurements over a wide temperature range (25 °C 125 °C). Using device simulation results, the factors that influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, are explained. A guideline to change the SCR holding voltage, related to the SCR design layout without any change to process parameters, is also proposed. Ó 2007 Elsevier Ltd. All rights reserved.
1. Introduction The main target when developing protection structures against electrostatic discharge (ESD) is to generate a low impedance path between the pins interested by the ESD event, in order to dissipate all the discharge and, at the same time, keeping the voltage drop within the safe operating area (SOA) of the circuit to be protected. Many ESD protection structures exist, each of which presents advantages and disadvantages. Diodes (i) are the simplest ESD protection devices, however, their low forward turn-on voltage makes them not suitable for many applications unless used in a diode chain format. The bipolar junction transistor (BJT) (ii) is the basis for most active ESD protection structures, including MOS and SCR types. BJT-based ESD protection structure are fairly effective as
*
Corresponding author. Tel.: +39 049 8277653; fax: +39 049 8277699. E-mail address: [email protected] (A. Tazzoli).
0026-2714/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.07.078
ESD protection devices because of the large current gain. The gate-grounded nMOS (ggNMOS) (iii) is the most commonly used ESD protection structure in CMOS IC design. However, due to the low efficiency of the intrinsic parasitic BJT, ggNMOS-based ESD protection structures utilize a relatively large silicon area. Hence, significant parasitic effects are present, which makes ggNMOS devices the non-optimum solution for high ESD robustness, high frequency, large pin count, and area-sensitive IC chips [1]. The silicon-controlled rectifier low voltage triggered (SCR-LVT) (iv) is one of the most efficient ESD protection structure. Thanks to the low holding voltage, leading to a low power dissipation during the ESD event, SCRs exhibit a great robustness per unit area. Despite these positive aspects, SCR-based protection structures must be carefully designed, in order to avoid self-triggering, that can cause latch-up conditions during the normal operation [2,3]. With respect to traditional SCRs, where the holding voltage is determined by the intrinsic feedback of two BJTs, we have developed and characterized a new
A. Tazzoli et al. / Microelectronics Reliability 47 (2007) 1444–1449
1E-12 9
Ileak [A] 1E-6
1E-9
1E-3
1E+0
8 7 6 Id [A]
SCR-LVT structure, where the holding voltage is adjustable provided that some layout parameters are changed. This flexibility allows to adapt the same protection device to many different technologies in an easy way. During our test we have observed a strong dependence of the holding voltage with the ESD pulse width, due to the self-heating effect. This effect, in particular, lead the holding voltage to lower from 8 V (with a 100 ns pulse width), down to 4 V (with a 1 ms pulse width). In order to fully understand the behavior of these new protection structure, we have performed an extensive process and 2D-device simulations campaign. Simulations results perfectly fit with measurements, from room temperature up to 125 °C. Furthermore, simulations have allowed to understand the factors that mainly influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs.
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5 4 3 IV 100ns TLP 2
Ileak
1 0 0
10
20 Vd [V]
30
40
Fig. 1. I–V curve of a SCR-HV exhibiting a high robustness of around 8 A.
2. Device structure In this work, new SCR-LVTs to be adopted as protection structure against ESD events, have been developed and characterized. We have studied two type of SCR-LVT devices, SCRLVT-HV and SCR-LVT-LV, respectively for 3.3 and 1.8 voltage classes. The devices have been designed with a very similar layout, a width of 183 lm, but differing doping profiles. The technology node that we have used to test this new SCR structures has been a 0.18 lm CMOS process. Developed devices have exhibited a great ESD robustness (around 8 A), and an holding voltage (VH) suitable with the nominal supply voltage (3.3 V). These structures could be used to protect input pad, where oxide breakdown is higher than SCRs trigger voltage, or even standard IOs, adopting the general techniques to reduce further the trigger voltage or to make less efficient the buffer parasitic bipolar.
In order to test the dependence of the trigger voltage with the pulse width, we have used a solid state pulser Hp8114A, useful to test the device behavior at lower current regime than TLP systems. In Fig. 2 the I–V curves measured changing the pulse width from 100 ns up to 1 ms is reported. The lowering of the holding voltage on increasing of the pulse width is clearly visible. Analyzing the measured voltage waveforms during the TLP event (see Fig. 3), it is possible to notice the decaying behavior of the holding voltage as function of the time. This behavior, as previously stated, is more evident in HV devices than in LV ones, as shown in the I–V curves of Fig. 4, where VH changes only from 4.1 V down to 3.2 V. A very important feature of SCR-LVT-HV devices is that they present an holding voltage of around 7.5 V (4 V for the SCR-LVT-LV), against the typical VH of around 2 V exhibited by classical SCRs. This is a very positive feature, because it could allow to use this protection structures
3. Electrical characterization 0.5
1ms
0.45
1us
0.4
100ns IV - SCRHV
0.35 0.3 Id [A]
We have used a 100 ns transmission line pulser (TLP) system, based on the transmission domain reflectometer philosophy [2], in order to characterize the ESD robustness of tested SCR-based protection structures. TLP is a widely used testing method, which allows not only a device standard characterization, but also a detailed investigation of the device in the ESD regime, thanks to the ability of generating high voltage and/or high current levels, rectangular shaped pulses, with very fast rise time (below 1 ns). The typical I–V curve (open diamonds) and leakage current measurements (gray boxes) of tested SCR devices are reported in Fig. 1. This device has exhibited a great robustness of around 8 A (that can be correlated to around 12 kV of the Human Body Model testing), and has failed with a sudden change of the leakage current from around 1 nA to the set current compliance level (2 lA).
0.25 0.2 0.15 0.1 0.05 0 0
1
2
3
4
5
6
7 8 9 10 11 12 13 14 15 Vd [V]
Fig. 2. I–V TLP curve of a SCR-HV. The holding voltage is heavily dependent on the pulse width.
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A. Tazzoli et al. / Microelectronics Reliability 47 (2007) 1444–1449 18 16
9 T = 25 °C
100ns
Trigger
8
1us 14
Vhold @ 1us
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Vhold @ 1ms
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7
Vhold @ 100ns
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Vd [V]
T = 75 °C
1ms
12
T = 50 °C
25 C
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6
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T = 100 °C
75 C
T = 125 °C
5 100 C 125 C 4 3
2
2 10E-9 100E-9 1E-6
0 10E-9
1E-6
100E-6
Fig. 3. Holding voltage dependence upon the pulse width.
10E-3 100E-3
Pulse Width [s]
10E-3
Time [s]
10E-6 100E-6 1E-3
Fig. 5. Measurement of the holding voltage dependence on the pulse width at increasing temperature.
9
0.5 IV - SCRLV
0.45
7 Holding Voltage [V]
1us
0.4
100ns
0.35
1ms
0.3 Id [A]
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90 100 110 120 130
Temperature [°C]
0
1
2
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5
6
7
8
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Fig. 6. Measurement of the holding voltage dependence on the ambient temperature at different pulse widths.
Fig. 4. I–V characteristic of a SCR-LV. These devices are less influenced by the pulse width used for testing.
4. Simulation activity in circuit with high supply voltage, avoiding critical latchup condition during the normal operation. In order to investigate, if the relatively high holding voltage value is temperature dependent, we have repeated TLP measurements at different temperatures, starting from 25 °C to 125 °C, using a temperature controlled climatic chamber. In Figs. 5 and 6 we report the holding voltage extraction during these tests. As it can be seen in the Figs. 5 and 6, with the increase of the temperature, the holding voltage decreases. This dependence of the holding voltage with the temperature supports the hypothesis that the dependence of the holding voltage on the pulse width is due to some thermal effect.
In order to study the physical behavior of these SCR structures, we have made simulations with Synopsys TCAD tools [4,5]. In Fig. 7 we report the analyzed structure obtained by process simulation (DIOS Synopsys) [4]. Superimposed to the process simulation result, and sketched in Fig. 8a, the equivalent electrical circuit is shown. As depicted, unlike the traditional SCR (made only by PNP1 and NPN2), other two parasitic BJTs (PNP3 and PNP4) are present. In order to better analyze the effect of the two new BJTs included in the SCR loop, we have analyzed by 2D-device simulations the standard SCR-LVT structure (i.e. without the two transistors, PNP3 and PNP4). This standard
A. Tazzoli et al. / Microelectronics Reliability 47 (2007) 1444–1449
Fig. 7. Structure of the new SCR-LVT-HV tested, obtained by process simulation.
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Simulated currents at each terminal (as function of the applied voltage) of the SCR-schematic without PNP3 and PNP4 (see Fig. 8b) are reported in Fig. 10. As it can be seen, when the voltage across the SCR reaches around 9 V, after the device snapback (i.e. in the negative resistance region), PNP1 turns on, and the current starts to flow also into the PEmit terminal. Considering the structure of the new SCR studied in this work (see the schematic in Fig. 8a), the simulated currents at each terminals as function of the device voltage drop are reported in Fig. 11. In this case, when PNP1 turns on, also PNP3 and PNP4 do the same. Therefore the only difference with the previous case is that also PNP3 and PNP4 contribute to sustain I(PEmitt), interacting with the main feedback of PNP1 and NPN2. This then causes the holding voltage to increase to a value of around 7 V. The base-emitter voltages of PNP3 and PNP4 of the complete SCR-LVT, after that the holding point has been reached, are respectively VBE3 = 6 V and VBE4 = 1 V, while the base-collector voltages are VBC3 = 1.5 V and VBC4 = 2 V (see Fig. 12). This confirms that all the parasitic BJTs are properly turned on, in agreement with the
Fig. 8. Equivalent circuits of the studied SCR-LVT-HV, respectively, with (a) and without (b) the parasitic BJTs PNP3 and PNP4.
structure has been obtained simply removing the p-substrate (see Fig. 8b for the schematic). In Fig. 9 we report the comparison of the simulated I–V curves of SCRs with and without PNP3 and PNP4. The dark curve, the I–V behavior of the SCR developed in this work exhibits an holding voltage of about 7 V. On the contrary, the light curve shows the behavior of the SCR without PNP3 and PNP4 (i.e. with the removed substrate). In this case, the simulated holding voltage is around 2 V.
Fig. 9. Comparison between the I–V characteristics of the complete SCR LVT-HV and without the two parasitic BJTs.
Fig. 10. Simulated current of various terminals of the SCR-HV without PNP3 and PNP4. The instant in which PNP1 turns on is highlighted.
Fig. 11. Simulated current of various terminals of the complete SCR LVT-HV. PNP1, PNP3 and PNP4 turn-on are highlighted.
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A. Tazzoli et al. / Microelectronics Reliability 47 (2007) 1444–1449
Fig. 12. Simulated voltage at various node of the complete SCR-HV. Fig. 15. Comparison between the simulated I–V characteristics of the complete SCR-HV varying the resistors at the NEmitt electrode.
Fig. 13. Distribution of the hole current density in the holding phase.
simulated distribution of the hole current density, shown in Fig. 13. All previous analyses have been carried out at 300 K. We have also simulated the SCRs behavior at different temperatures. In good agreement with the measurements, as the temperature increases the holding voltage decreases (see Fig. 14). This phenomenon is a direct consequence of the temperature dependence of the BJT currents. In fact, keeping constant the base-to-emitter voltage, and increasing the temperature of a BJT, the base current increases, leading the collector current to do the same, and this effect is more evident in BJTs with larger gain (and greater base-emitter voltage) [6]. This temperature dependence has a direct consequence on the SCR behavior. In fact, as the temperature increases, PNP1 works better than the other two parasitic BJTs, causing the decrease of the holding voltage of the SCR.
Fig. 14. Comparison between the simulated I–V characteristics of the complete SCR-LVT-HV at different environment temperature.
When the holding voltage reaches around 2 V (at a temperature of 175 °C), the decreasing trend saturates to the lower limit exhibited by the tested structure, about 2.4 V. This represents the situation where the effects of PNP3 and PNP4 are completely overcome by the effect of PNP1. Summarizing, the efficiency of the parasitic BJTs is determined by the gain of PNP3 and PNP4, and the base-emitter voltages. For this reason, a simple way to control the holding voltage could be the sizing of the series resistance of the various electrodes. In order to better investigate the SCR behavior, we have made many simulations with different electrodes resistances combinations. Finally, we have found that the terminals that meaningfully impact on the holding voltage are PEmitt and mainly NEmitt. In fact, the PEmitt terminal regulates the turn-on current and the base-emitter voltage of PNP1, while NEmitt influences the VBE of NPN2. Thank to these results, an easy way to control the holding voltage could be the proper sizing of the series resistance of the NEmitt terminal, as depicted by the simulation results reported in Fig. 15. 5. Conclusion In this work, new silicon-controlled rectifiers low voltage triggered have been developed and characterized. We have studied two type of SCR-LVT devices, differing from the doping profiles (named SCR-LVT-HV and SCR-LVTLV), but with the same layout. These devices could be effectively adopted as protection structures against electrostatic discharge events, thanks a great robustness, characterized by TLP measurements, of around 8 A. The important feature of tested devices is the high value of the holding voltage. This feature has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCRLVT structure. In this way, two parasitic transistors are inserted into the typical SCR structure, influencing the loop feedback gain of the two main npn and pnp BJTs.
A. Tazzoli et al. / Microelectronics Reliability 47 (2007) 1444–1449
This leads to an increase of the sustaining (holding) voltage during the ESD event. We have noticed that this effect is more evident in HV devices than in LV ones, because of different doping profiles, that bring to different gain of the two parasitic bipolar transistors constituting the SCR structure. We have also observed a strong dependence of the holding voltage with the ESD pulse width due to the self-heating effects. In particular, we have observed that the holding voltage can decrease of around 4 V, lowering from 8 V with a 100 ns pulse width, down to 4 V with a 1 ms pulse width. Device simulation results perfectly fit with measurements, at room temperature as well as up to 125 °C. Furthermore, simulations have allowed to understand the factors influencing the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, providing guidelines to proper SCR design. In fact, we have demonstrated that the holding voltage value can be controlled by the layout design properly sizing the series resistance of the SCR electrodes.
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Acknowledgement The authors would like to thank Karl Su¨ss for providing a PM8 probe station in order to build the TLP-TDR on wafer system. References [1] Wang AZH. On-chip ESD protection for integrated circuits. An IC design perspective. 2nd ed. Kluwer Academic Publisher; 2002. [2] Amerasekera A, Duvvury C. ESD in silicon integrated circuits. 2nd ed. John WILEY and Sons; 2002. [3] Concannon A, Vashchenko VA, Beek MT, Hopper P. A device level negative feedback in the emitter line of SCR structures as a method to realize latch-up free ESD protection. In: Proceeding of international reliability and physics symposium, IRPS 2003; p. 105–11. [4] Synopsys, TCAD tools, http://www.synopsys.com/. [5] Esmark K, Gossner H, Standler W. Advanced simulation methods for ESD protection development. 2nd ed. John WILEY and Sons; 2002. [6] Sze SM, Ng Kwok K. Physics of semiconductor devices. 3rd ed. John WILEY and Sons; 2007.
Holding voltage investigation of advanced SCR-based protection structures for CMOS technology A. Tazzoli
a,*
, F.A. Marino a, M. Cordoni b, A. Benvenuti b, P. Colombo b, E. Zanoni a, G. Meneghesso a a
DEI, University of Padova, Via Gradenigo 6/B, 35131 Padova, Italy b STMicroelectronics, Agrate Brianza (Mi), Italy Received 6 July 2007 Available online 4 September 2007
Abstract A new silicon-controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially destroy the loop feedback gain of the two main npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage during the ESD event. A strong dependence of the holding voltage with the ESD pulse width has also been observed, caused by self-heating effects. 2D-device simulations (DESSIS Synopsys) have been performed obtaining results that perfectly fit the measurements over a wide temperature range (25 °C 125 °C). Using device simulation results, the factors that influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, are explained. A guideline to change the SCR holding voltage, related to the SCR design layout without any change to process parameters, is also proposed. Ó 2007 Elsevier Ltd. All rights reserved.
1. Introduction The main target when developing protection structures against electrostatic discharge (ESD) is to generate a low impedance path between the pins interested by the ESD event, in order to dissipate all the discharge and, at the same time, keeping the voltage drop within the safe operating area (SOA) of the circuit to be protected. Many ESD protection structures exist, each of which presents advantages and disadvantages. Diodes (i) are the simplest ESD protection devices, however, their low forward turn-on voltage makes them not suitable for many applications unless used in a diode chain format. The bipolar junction transistor (BJT) (ii) is the basis for most active ESD protection structures, including MOS and SCR types. BJT-based ESD protection structure are fairly effective as
*
Corresponding author. Tel.: +39 049 8277653; fax: +39 049 8277699. E-mail address: [email protected] (A. Tazzoli).
0026-2714/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.07.078
ESD protection devices because of the large current gain. The gate-grounded nMOS (ggNMOS) (iii) is the most commonly used ESD protection structure in CMOS IC design. However, due to the low efficiency of the intrinsic parasitic BJT, ggNMOS-based ESD protection structures utilize a relatively large silicon area. Hence, significant parasitic effects are present, which makes ggNMOS devices the non-optimum solution for high ESD robustness, high frequency, large pin count, and area-sensitive IC chips [1]. The silicon-controlled rectifier low voltage triggered (SCR-LVT) (iv) is one of the most efficient ESD protection structure. Thanks to the low holding voltage, leading to a low power dissipation during the ESD event, SCRs exhibit a great robustness per unit area. Despite these positive aspects, SCR-based protection structures must be carefully designed, in order to avoid self-triggering, that can cause latch-up conditions during the normal operation [2,3]. With respect to traditional SCRs, where the holding voltage is determined by the intrinsic feedback of two BJTs, we have developed and characterized a new
A. Tazzoli et al. / Microelectronics Reliability 47 (2007) 1444–1449
1E-12 9
Ileak [A] 1E-6
1E-9
1E-3
1E+0
8 7 6 Id [A]
SCR-LVT structure, where the holding voltage is adjustable provided that some layout parameters are changed. This flexibility allows to adapt the same protection device to many different technologies in an easy way. During our test we have observed a strong dependence of the holding voltage with the ESD pulse width, due to the self-heating effect. This effect, in particular, lead the holding voltage to lower from 8 V (with a 100 ns pulse width), down to 4 V (with a 1 ms pulse width). In order to fully understand the behavior of these new protection structure, we have performed an extensive process and 2D-device simulations campaign. Simulations results perfectly fit with measurements, from room temperature up to 125 °C. Furthermore, simulations have allowed to understand the factors that mainly influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs.
1445
5 4 3 IV 100ns TLP 2
Ileak
1 0 0
10
20 Vd [V]
30
40
Fig. 1. I–V curve of a SCR-HV exhibiting a high robustness of around 8 A.
2. Device structure In this work, new SCR-LVTs to be adopted as protection structure against ESD events, have been developed and characterized. We have studied two type of SCR-LVT devices, SCRLVT-HV and SCR-LVT-LV, respectively for 3.3 and 1.8 voltage classes. The devices have been designed with a very similar layout, a width of 183 lm, but differing doping profiles. The technology node that we have used to test this new SCR structures has been a 0.18 lm CMOS process. Developed devices have exhibited a great ESD robustness (around 8 A), and an holding voltage (VH) suitable with the nominal supply voltage (3.3 V). These structures could be used to protect input pad, where oxide breakdown is higher than SCRs trigger voltage, or even standard IOs, adopting the general techniques to reduce further the trigger voltage or to make less efficient the buffer parasitic bipolar.
In order to test the dependence of the trigger voltage with the pulse width, we have used a solid state pulser Hp8114A, useful to test the device behavior at lower current regime than TLP systems. In Fig. 2 the I–V curves measured changing the pulse width from 100 ns up to 1 ms is reported. The lowering of the holding voltage on increasing of the pulse width is clearly visible. Analyzing the measured voltage waveforms during the TLP event (see Fig. 3), it is possible to notice the decaying behavior of the holding voltage as function of the time. This behavior, as previously stated, is more evident in HV devices than in LV ones, as shown in the I–V curves of Fig. 4, where VH changes only from 4.1 V down to 3.2 V. A very important feature of SCR-LVT-HV devices is that they present an holding voltage of around 7.5 V (4 V for the SCR-LVT-LV), against the typical VH of around 2 V exhibited by classical SCRs. This is a very positive feature, because it could allow to use this protection structures
3. Electrical characterization 0.5
1ms
0.45
1us
0.4
100ns IV - SCRHV
0.35 0.3 Id [A]
We have used a 100 ns transmission line pulser (TLP) system, based on the transmission domain reflectometer philosophy [2], in order to characterize the ESD robustness of tested SCR-based protection structures. TLP is a widely used testing method, which allows not only a device standard characterization, but also a detailed investigation of the device in the ESD regime, thanks to the ability of generating high voltage and/or high current levels, rectangular shaped pulses, with very fast rise time (below 1 ns). The typical I–V curve (open diamonds) and leakage current measurements (gray boxes) of tested SCR devices are reported in Fig. 1. This device has exhibited a great robustness of around 8 A (that can be correlated to around 12 kV of the Human Body Model testing), and has failed with a sudden change of the leakage current from around 1 nA to the set current compliance level (2 lA).
0.25 0.2 0.15 0.1 0.05 0 0
1
2
3
4
5
6
7 8 9 10 11 12 13 14 15 Vd [V]
Fig. 2. I–V TLP curve of a SCR-HV. The holding voltage is heavily dependent on the pulse width.
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A. Tazzoli et al. / Microelectronics Reliability 47 (2007) 1444–1449 18 16
9 T = 25 °C
100ns
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8
1us 14
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Vhold @ 100ns
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Vd [V]
T = 75 °C
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25 C
4
6
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T = 100 °C
75 C
T = 125 °C
5 100 C 125 C 4 3
2
2 10E-9 100E-9 1E-6
0 10E-9
1E-6
100E-6
Fig. 3. Holding voltage dependence upon the pulse width.
10E-3 100E-3
Pulse Width [s]
10E-3
Time [s]
10E-6 100E-6 1E-3
Fig. 5. Measurement of the holding voltage dependence on the pulse width at increasing temperature.
9
0.5 IV - SCRLV
0.45
7 Holding Voltage [V]
1us
0.4
100ns
0.35
1ms
0.3 Id [A]
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90 100 110 120 130
Temperature [°C]
0
1
2
3
4
5
6
7
8
9
10 11 12
Vd [V]
Fig. 6. Measurement of the holding voltage dependence on the ambient temperature at different pulse widths.
Fig. 4. I–V characteristic of a SCR-LV. These devices are less influenced by the pulse width used for testing.
4. Simulation activity in circuit with high supply voltage, avoiding critical latchup condition during the normal operation. In order to investigate, if the relatively high holding voltage value is temperature dependent, we have repeated TLP measurements at different temperatures, starting from 25 °C to 125 °C, using a temperature controlled climatic chamber. In Figs. 5 and 6 we report the holding voltage extraction during these tests. As it can be seen in the Figs. 5 and 6, with the increase of the temperature, the holding voltage decreases. This dependence of the holding voltage with the temperature supports the hypothesis that the dependence of the holding voltage on the pulse width is due to some thermal effect.
In order to study the physical behavior of these SCR structures, we have made simulations with Synopsys TCAD tools [4,5]. In Fig. 7 we report the analyzed structure obtained by process simulation (DIOS Synopsys) [4]. Superimposed to the process simulation result, and sketched in Fig. 8a, the equivalent electrical circuit is shown. As depicted, unlike the traditional SCR (made only by PNP1 and NPN2), other two parasitic BJTs (PNP3 and PNP4) are present. In order to better analyze the effect of the two new BJTs included in the SCR loop, we have analyzed by 2D-device simulations the standard SCR-LVT structure (i.e. without the two transistors, PNP3 and PNP4). This standard
A. Tazzoli et al. / Microelectronics Reliability 47 (2007) 1444–1449
Fig. 7. Structure of the new SCR-LVT-HV tested, obtained by process simulation.
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Simulated currents at each terminal (as function of the applied voltage) of the SCR-schematic without PNP3 and PNP4 (see Fig. 8b) are reported in Fig. 10. As it can be seen, when the voltage across the SCR reaches around 9 V, after the device snapback (i.e. in the negative resistance region), PNP1 turns on, and the current starts to flow also into the PEmit terminal. Considering the structure of the new SCR studied in this work (see the schematic in Fig. 8a), the simulated currents at each terminals as function of the device voltage drop are reported in Fig. 11. In this case, when PNP1 turns on, also PNP3 and PNP4 do the same. Therefore the only difference with the previous case is that also PNP3 and PNP4 contribute to sustain I(PEmitt), interacting with the main feedback of PNP1 and NPN2. This then causes the holding voltage to increase to a value of around 7 V. The base-emitter voltages of PNP3 and PNP4 of the complete SCR-LVT, after that the holding point has been reached, are respectively VBE3 = 6 V and VBE4 = 1 V, while the base-collector voltages are VBC3 = 1.5 V and VBC4 = 2 V (see Fig. 12). This confirms that all the parasitic BJTs are properly turned on, in agreement with the
Fig. 8. Equivalent circuits of the studied SCR-LVT-HV, respectively, with (a) and without (b) the parasitic BJTs PNP3 and PNP4.
structure has been obtained simply removing the p-substrate (see Fig. 8b for the schematic). In Fig. 9 we report the comparison of the simulated I–V curves of SCRs with and without PNP3 and PNP4. The dark curve, the I–V behavior of the SCR developed in this work exhibits an holding voltage of about 7 V. On the contrary, the light curve shows the behavior of the SCR without PNP3 and PNP4 (i.e. with the removed substrate). In this case, the simulated holding voltage is around 2 V.
Fig. 9. Comparison between the I–V characteristics of the complete SCR LVT-HV and without the two parasitic BJTs.
Fig. 10. Simulated current of various terminals of the SCR-HV without PNP3 and PNP4. The instant in which PNP1 turns on is highlighted.
Fig. 11. Simulated current of various terminals of the complete SCR LVT-HV. PNP1, PNP3 and PNP4 turn-on are highlighted.
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Fig. 12. Simulated voltage at various node of the complete SCR-HV. Fig. 15. Comparison between the simulated I–V characteristics of the complete SCR-HV varying the resistors at the NEmitt electrode.
Fig. 13. Distribution of the hole current density in the holding phase.
simulated distribution of the hole current density, shown in Fig. 13. All previous analyses have been carried out at 300 K. We have also simulated the SCRs behavior at different temperatures. In good agreement with the measurements, as the temperature increases the holding voltage decreases (see Fig. 14). This phenomenon is a direct consequence of the temperature dependence of the BJT currents. In fact, keeping constant the base-to-emitter voltage, and increasing the temperature of a BJT, the base current increases, leading the collector current to do the same, and this effect is more evident in BJTs with larger gain (and greater base-emitter voltage) [6]. This temperature dependence has a direct consequence on the SCR behavior. In fact, as the temperature increases, PNP1 works better than the other two parasitic BJTs, causing the decrease of the holding voltage of the SCR.
Fig. 14. Comparison between the simulated I–V characteristics of the complete SCR-LVT-HV at different environment temperature.
When the holding voltage reaches around 2 V (at a temperature of 175 °C), the decreasing trend saturates to the lower limit exhibited by the tested structure, about 2.4 V. This represents the situation where the effects of PNP3 and PNP4 are completely overcome by the effect of PNP1. Summarizing, the efficiency of the parasitic BJTs is determined by the gain of PNP3 and PNP4, and the base-emitter voltages. For this reason, a simple way to control the holding voltage could be the sizing of the series resistance of the various electrodes. In order to better investigate the SCR behavior, we have made many simulations with different electrodes resistances combinations. Finally, we have found that the terminals that meaningfully impact on the holding voltage are PEmitt and mainly NEmitt. In fact, the PEmitt terminal regulates the turn-on current and the base-emitter voltage of PNP1, while NEmitt influences the VBE of NPN2. Thank to these results, an easy way to control the holding voltage could be the proper sizing of the series resistance of the NEmitt terminal, as depicted by the simulation results reported in Fig. 15. 5. Conclusion In this work, new silicon-controlled rectifiers low voltage triggered have been developed and characterized. We have studied two type of SCR-LVT devices, differing from the doping profiles (named SCR-LVT-HV and SCR-LVTLV), but with the same layout. These devices could be effectively adopted as protection structures against electrostatic discharge events, thanks a great robustness, characterized by TLP measurements, of around 8 A. The important feature of tested devices is the high value of the holding voltage. This feature has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCRLVT structure. In this way, two parasitic transistors are inserted into the typical SCR structure, influencing the loop feedback gain of the two main npn and pnp BJTs.
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This leads to an increase of the sustaining (holding) voltage during the ESD event. We have noticed that this effect is more evident in HV devices than in LV ones, because of different doping profiles, that bring to different gain of the two parasitic bipolar transistors constituting the SCR structure. We have also observed a strong dependence of the holding voltage with the ESD pulse width due to the self-heating effects. In particular, we have observed that the holding voltage can decrease of around 4 V, lowering from 8 V with a 100 ns pulse width, down to 4 V with a 1 ms pulse width. Device simulation results perfectly fit with measurements, at room temperature as well as up to 125 °C. Furthermore, simulations have allowed to understand the factors influencing the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, providing guidelines to proper SCR design. In fact, we have demonstrated that the holding voltage value can be controlled by the layout design properly sizing the series resistance of the SCR electrodes.
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Acknowledgement The authors would like to thank Karl Su¨ss for providing a PM8 probe station in order to build the TLP-TDR on wafer system. References [1] Wang AZH. On-chip ESD protection for integrated circuits. An IC design perspective. 2nd ed. Kluwer Academic Publisher; 2002. [2] Amerasekera A, Duvvury C. ESD in silicon integrated circuits. 2nd ed. John WILEY and Sons; 2002. [3] Concannon A, Vashchenko VA, Beek MT, Hopper P. A device level negative feedback in the emitter line of SCR structures as a method to realize latch-up free ESD protection. In: Proceeding of international reliability and physics symposium, IRPS 2003; p. 105–11. [4] Synopsys, TCAD tools, http://www.synopsys.com/. [5] Esmark K, Gossner H, Standler W. Advanced simulation methods for ESD protection development. 2nd ed. John WILEY and Sons; 2002. [6] Sze SM, Ng Kwok K. Physics of semiconductor devices. 3rd ed. John WILEY and Sons; 2007.