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Si stressors in advanced CMOS technology
Solid-State Electronics 110 (2015) 19–22
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Facet engineering for SiGe/Si stressors in advanced CMOS technology Johnson Kasim a,⇑, Carsten Reichel b, Gabriela Dilliway b, Bo Bai b, Nadja Zakowsky b a b
GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D Street 2, 738406 Singapore, Singapore GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany
a r t i c l e
i n f o
Article history: Available online 5 March 2015 The review of this paper was arranged by Jean-Michel Hartmann Keywords: Stressors SiGe Si cap Faceting Silicidation
a b s t r a c t A two-layer SiGe stressor was introduced for our CMOS technology containing a bottom layer with high Ge content to induce more stress to the channel and a top layer with lower Ge content for better nickel silicidation. However, even with the top lower Ge layer, defects were found after silicidation causing contact punch through. Since it is well known that the silicidation improves for Si, the SiGe top layer was replaced by a Si layer (Si-cap). Evaluation on 750 °C and 850 °C grown Si-cap was done. Different temperature grown Si-caps showed different growth behavior with morphology of the Si-cap grown at 850 °C completely different than that of the Si cap grown at 750 °C. There was a clear {3 1 1} facet formation for the higher temperature Si-cap resulting in a pinning effect to the spacer edge similar to that observed for the SiGe-cap. The faceted Si-cap improved silicidation and device parameters enabling the extension of this integration approach for SiGe/Si stressors to the more advanced technology nodes. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction A stressor to improve the pMOS performance had been introduced in our 90 nm CMOS technology initially as a single SiGe layer [1,2]. Unlike the first reported and nowadays widely used SiGe stressor integration [3], the SiGe was grown undoped prior to the transistor implants in order to enable optimal control of the dopant profile through implantation while keeping SiGe close to the gate [1,4]. In order to induce more stress into the channel, a higher Ge content in the SiGe stressor is required. However, the higher Ge content impacts on the nickel silicidation resulting in a high defectivity of the silicide. Thus, a two-layer SiGe stressor had been introduced in our 45 nm CMOS technology containing a layer with high Ge content to induce more stress to the channel and on top a layer with lower Ge content (cap layer) for better silicidation [5]. However, the silicide defectivity became more critical for more advanced technology nodes. A high number of defects were found after the silicidation of the SiGe top layer causing contact punch through. It was not feasible to achieve the required quality of the silicide using a SiGe-cap even with low Ge content. Since it is well known that the silicidation improves for Si [6], the SiGe top layer was replaced by a Si layer (Si-cap). In this paper we will present the challenges to introduce a Si cap layer for this integration approach in which the SiGe/Si stressor is grown prior to transistor implants. The morphology of the cap layer is critical for this ⇑ Corresponding author. Tel.: +65 66702420. E-mail address: [email protected] (J. Kasim). http://dx.doi.org/10.1016/j.sse.2015.01.010 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.
integration scheme. Only a faceted Sicap layer that pins the cap to the nitride spacer edge enables healthy device parameters.
2. Experimental details In this study, the SiGe S/D stressors were grown with commercially available epi reactor. The process flow involved a Si recess etch process using reactive-ion etching (RIE), followed by cleaning and subsequent selective epitaxial SiGe growth using reduced pressure chemical vapor deposition (RP-CVD) at about 700 °C with DCS, GeH4, and HCl. Initially, the Si cap that replaced the SiGe cap was grown at a widely used temperature of 750 °C using DCS and HCl. Later, a higher temperature (850 °C) Si cap process was developed in order to enable facet formation. Cross-sectional transmission electron microscope (XTEM) was carried out to check the growth morphology of different caps grown on the SiGe. Finally, the device parameters were tested to analyze the electrical response of the samples with different stressors.
3. Results and discussion SiGe-cap grown at 700 °C shows a clear {3 1 1} facet resulting in a pinning effect at the spacer edge due to the lower growth rate on {3 1 1} (Fig. 1a). Si cap initially was grown at 750 °C to replace the SiGe-cap. However, the morphology of the Si-cap layer is changed compare to that of the SiGe-cap layer. The {3 1 1} Si-cap facet
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J. Kasim et al. / Solid-State Electronics 110 (2015) 19–22
Fig. 1. TEM cross section right after deposition for (a) SiGe cap grown at 700 °C and (b) Si cap grown at 750 °C. Scale bar is 20 nm.
Fig. 2. TEM cross section before the extension/halo implantation for (a) SiGe cap and (b) Si cap grown at 750 °C. Scale bar is 20 nm.
Fig. 3. (a) VT and (b) Ron for SiGe cap and Si cap grown at 750 °C.
did not form at low temperature and the Si growth was not pinned at the spacer edge (Fig. 1b). Due to several cleaning steps between epitaxial deposition and implant, there is a certain loss of SiGe- or Si-cap. Fig. 2 shows the remaining morphology for SiGe- and Si-caps before the extension/halo implants. The loss of Si or SiGe is not uniform, and particularly differs at the spacer edge, influenced by their as-grown morphology. Since critical transistor implants such as pMOS extension and halo implants are carried out later in the process flow, the SiGe source/drain shapes, especially the morphology near spacer edge, have direct impact on the device parameters. As shown in
Fig. 2b, the 750 °C Si-cap has excess Si at spacer edge before implantation steps. Since the junction implant profile follows the surface of the remaining Si-cap, the junction profile is pulled up underneath the remaining Si-cap at the spacer edge causing a dopant gap and thus increased parasitic series resistance and artificially raised transistor threshold voltage (VT). The impact of the Si-cap grown at 750 °C morphology on transistor threshold voltage (VT) is shown in Fig. 3a. There is a clear VT shift compared to that with SiGe-cap because the remaining Si at the spacer edge blocks the halo implants thus increasing VT. This VT shift could not easily be recovered by a higher extension dose or increased implant energy without the risk of lattice
J. Kasim et al. / Solid-State Electronics 110 (2015) 19–22
21
Fig. 4. TEM cross section for Si cap grown at 850 °C (a) right after deposition and (b) before halo implants. Scale bar is 20 nm.
Fig. 5. (a) VT and (b) Ron for SiGe cap and Si cap grown at 850 °C.
pinning effect to the spacer edge similar to the SiGe-cap (Fig. 1a). At a growth temperature of 850 °C the morphology of the Si-cap is well matched to that of the SiGe-cap grown at 700 °C. The morphology of the remaining Si-cap before implants is greatly improved (Fig. 4b). The surface of the remaining Si-cap is fairly flat and very similar to that of the SiGe-cap (Fig. 1a). The {3 1 1} facet of the Si-cap compensates well for the non-uniform Si loss between deposition and implants. For the higher temperature Si-cap, the VT and Ron are clearly recovered and in a reasonable range (Fig. 5a and b). Additionally, the dependence of the series resistance on VT is clearly reduced. This is demonstrated by the Ron vs. VT slope reductions from higher temperature Si-cap on Fig. 6. The matched morphology of the higher temperature Si-cap to that of the SiGe-cap post epitaxial deposition step, which can be seen by comparing Figs. 1a and 4a, leads to improved critical device parameters such as VT and Ron. Fig. 6. Ron vs. VT for SiGe cap and Si caps grown at 750 °C and 850 °C.
4. Conclusion damage and strain loss. Additionally the linear on resistance (Ron) is also increased (Fig. 3b) resulting in a performance degradation. For this implant-last integration approach, a faceted Si cap is needed in order to avoid the device performance degradation. Faceting is mainly driven by growth rate anisotropy and the angle between the planes [7]. At a temperature of 750 °C, no Si facet appears but at higher temperature the ratio of the growth rates between the Si {3 1 1} and {1 0 0} planes changes allowing a {3 1 1} facet formation [7–9]. A Si-cap process was developed at 850 °C using DCS and HCl to achieve faceted Si growth. The morphology of the Si-cap grown at 850 °C is completely changed compared to that of the Si-cap grown at 750 °C. There is a clear {3 1 1} facet for the higher temperature Si-cap (Fig. 4a) resulting in a
Changing the material of the cap layer for the stressor from SiGe to Si to improve the nickel silicidation is challenging for the integration where the stressor is grown prior to transistor implants. A significant change of the cap layer morphology as a result of the material change leads to clearly degraded device parameters. The facets of the SiGe-cap layer pinning this layer to the spacer edge are critical for subsequent transistor implants. Any new cap layer needs to be pinned to the spacer edge as well. The faceted Si-cap layer matching the morphology of the previously used SiGe-cap enables healthy device parameters and it finally enabled the extension of this integration approach for SiGe/Si stressors to the more advanced technology nodes.
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J. Kasim et al. / Solid-State Electronics 110 (2015) 19–22
References [1] [2] [3] [4]
Horstmann M et al. IEDM Technical Digest, 2005, p. 233. Wei A et al. Proc SSDM 2005, p. 32. Ghani T et al. IEDM Technical Digest, 2003, p. 978. Kammler T, Peidous I, Wei A, Romero K, Reichel C, Heinemann S, et al. ECS Trans 2006;3(7):713.
[5] Reichel C, Zeun A, Beernink G, Waite A, Wiatr M, Kessler M, et al. Proc ICSI 2009;8:87. [6] Seger J, Jarmar T, Ericson F, Smith U, Hallstedt J, Zhang ZB, et al. J Appl Phys 2004;96:7179. [7] Dutartre D, Talbot A, Loubet N. ECS Trans 2006;3(7):473. [8] Loubet N, Talbot A, Dutartre D. Semicond Sci Technol 2007;22:S149. [9] Dutartre D, Seiss B, Campidelli Y, Pellissier-Tanon D, Barge D, Pantel R. Thin Solid Films 2012;520:3163.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Facet engineering for SiGe/Si stressors in advanced CMOS technology Johnson Kasim a,⇑, Carsten Reichel b, Gabriela Dilliway b, Bo Bai b, Nadja Zakowsky b a b
GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D Street 2, 738406 Singapore, Singapore GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany
a r t i c l e
i n f o
Article history: Available online 5 March 2015 The review of this paper was arranged by Jean-Michel Hartmann Keywords: Stressors SiGe Si cap Faceting Silicidation
a b s t r a c t A two-layer SiGe stressor was introduced for our CMOS technology containing a bottom layer with high Ge content to induce more stress to the channel and a top layer with lower Ge content for better nickel silicidation. However, even with the top lower Ge layer, defects were found after silicidation causing contact punch through. Since it is well known that the silicidation improves for Si, the SiGe top layer was replaced by a Si layer (Si-cap). Evaluation on 750 °C and 850 °C grown Si-cap was done. Different temperature grown Si-caps showed different growth behavior with morphology of the Si-cap grown at 850 °C completely different than that of the Si cap grown at 750 °C. There was a clear {3 1 1} facet formation for the higher temperature Si-cap resulting in a pinning effect to the spacer edge similar to that observed for the SiGe-cap. The faceted Si-cap improved silicidation and device parameters enabling the extension of this integration approach for SiGe/Si stressors to the more advanced technology nodes. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction A stressor to improve the pMOS performance had been introduced in our 90 nm CMOS technology initially as a single SiGe layer [1,2]. Unlike the first reported and nowadays widely used SiGe stressor integration [3], the SiGe was grown undoped prior to the transistor implants in order to enable optimal control of the dopant profile through implantation while keeping SiGe close to the gate [1,4]. In order to induce more stress into the channel, a higher Ge content in the SiGe stressor is required. However, the higher Ge content impacts on the nickel silicidation resulting in a high defectivity of the silicide. Thus, a two-layer SiGe stressor had been introduced in our 45 nm CMOS technology containing a layer with high Ge content to induce more stress to the channel and on top a layer with lower Ge content (cap layer) for better silicidation [5]. However, the silicide defectivity became more critical for more advanced technology nodes. A high number of defects were found after the silicidation of the SiGe top layer causing contact punch through. It was not feasible to achieve the required quality of the silicide using a SiGe-cap even with low Ge content. Since it is well known that the silicidation improves for Si [6], the SiGe top layer was replaced by a Si layer (Si-cap). In this paper we will present the challenges to introduce a Si cap layer for this integration approach in which the SiGe/Si stressor is grown prior to transistor implants. The morphology of the cap layer is critical for this ⇑ Corresponding author. Tel.: +65 66702420. E-mail address: [email protected] (J. Kasim). http://dx.doi.org/10.1016/j.sse.2015.01.010 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.
integration scheme. Only a faceted Sicap layer that pins the cap to the nitride spacer edge enables healthy device parameters.
2. Experimental details In this study, the SiGe S/D stressors were grown with commercially available epi reactor. The process flow involved a Si recess etch process using reactive-ion etching (RIE), followed by cleaning and subsequent selective epitaxial SiGe growth using reduced pressure chemical vapor deposition (RP-CVD) at about 700 °C with DCS, GeH4, and HCl. Initially, the Si cap that replaced the SiGe cap was grown at a widely used temperature of 750 °C using DCS and HCl. Later, a higher temperature (850 °C) Si cap process was developed in order to enable facet formation. Cross-sectional transmission electron microscope (XTEM) was carried out to check the growth morphology of different caps grown on the SiGe. Finally, the device parameters were tested to analyze the electrical response of the samples with different stressors.
3. Results and discussion SiGe-cap grown at 700 °C shows a clear {3 1 1} facet resulting in a pinning effect at the spacer edge due to the lower growth rate on {3 1 1} (Fig. 1a). Si cap initially was grown at 750 °C to replace the SiGe-cap. However, the morphology of the Si-cap layer is changed compare to that of the SiGe-cap layer. The {3 1 1} Si-cap facet
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J. Kasim et al. / Solid-State Electronics 110 (2015) 19–22
Fig. 1. TEM cross section right after deposition for (a) SiGe cap grown at 700 °C and (b) Si cap grown at 750 °C. Scale bar is 20 nm.
Fig. 2. TEM cross section before the extension/halo implantation for (a) SiGe cap and (b) Si cap grown at 750 °C. Scale bar is 20 nm.
Fig. 3. (a) VT and (b) Ron for SiGe cap and Si cap grown at 750 °C.
did not form at low temperature and the Si growth was not pinned at the spacer edge (Fig. 1b). Due to several cleaning steps between epitaxial deposition and implant, there is a certain loss of SiGe- or Si-cap. Fig. 2 shows the remaining morphology for SiGe- and Si-caps before the extension/halo implants. The loss of Si or SiGe is not uniform, and particularly differs at the spacer edge, influenced by their as-grown morphology. Since critical transistor implants such as pMOS extension and halo implants are carried out later in the process flow, the SiGe source/drain shapes, especially the morphology near spacer edge, have direct impact on the device parameters. As shown in
Fig. 2b, the 750 °C Si-cap has excess Si at spacer edge before implantation steps. Since the junction implant profile follows the surface of the remaining Si-cap, the junction profile is pulled up underneath the remaining Si-cap at the spacer edge causing a dopant gap and thus increased parasitic series resistance and artificially raised transistor threshold voltage (VT). The impact of the Si-cap grown at 750 °C morphology on transistor threshold voltage (VT) is shown in Fig. 3a. There is a clear VT shift compared to that with SiGe-cap because the remaining Si at the spacer edge blocks the halo implants thus increasing VT. This VT shift could not easily be recovered by a higher extension dose or increased implant energy without the risk of lattice
J. Kasim et al. / Solid-State Electronics 110 (2015) 19–22
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Fig. 4. TEM cross section for Si cap grown at 850 °C (a) right after deposition and (b) before halo implants. Scale bar is 20 nm.
Fig. 5. (a) VT and (b) Ron for SiGe cap and Si cap grown at 850 °C.
pinning effect to the spacer edge similar to the SiGe-cap (Fig. 1a). At a growth temperature of 850 °C the morphology of the Si-cap is well matched to that of the SiGe-cap grown at 700 °C. The morphology of the remaining Si-cap before implants is greatly improved (Fig. 4b). The surface of the remaining Si-cap is fairly flat and very similar to that of the SiGe-cap (Fig. 1a). The {3 1 1} facet of the Si-cap compensates well for the non-uniform Si loss between deposition and implants. For the higher temperature Si-cap, the VT and Ron are clearly recovered and in a reasonable range (Fig. 5a and b). Additionally, the dependence of the series resistance on VT is clearly reduced. This is demonstrated by the Ron vs. VT slope reductions from higher temperature Si-cap on Fig. 6. The matched morphology of the higher temperature Si-cap to that of the SiGe-cap post epitaxial deposition step, which can be seen by comparing Figs. 1a and 4a, leads to improved critical device parameters such as VT and Ron. Fig. 6. Ron vs. VT for SiGe cap and Si caps grown at 750 °C and 850 °C.
4. Conclusion damage and strain loss. Additionally the linear on resistance (Ron) is also increased (Fig. 3b) resulting in a performance degradation. For this implant-last integration approach, a faceted Si cap is needed in order to avoid the device performance degradation. Faceting is mainly driven by growth rate anisotropy and the angle between the planes [7]. At a temperature of 750 °C, no Si facet appears but at higher temperature the ratio of the growth rates between the Si {3 1 1} and {1 0 0} planes changes allowing a {3 1 1} facet formation [7–9]. A Si-cap process was developed at 850 °C using DCS and HCl to achieve faceted Si growth. The morphology of the Si-cap grown at 850 °C is completely changed compared to that of the Si-cap grown at 750 °C. There is a clear {3 1 1} facet for the higher temperature Si-cap (Fig. 4a) resulting in a
Changing the material of the cap layer for the stressor from SiGe to Si to improve the nickel silicidation is challenging for the integration where the stressor is grown prior to transistor implants. A significant change of the cap layer morphology as a result of the material change leads to clearly degraded device parameters. The facets of the SiGe-cap layer pinning this layer to the spacer edge are critical for subsequent transistor implants. Any new cap layer needs to be pinned to the spacer edge as well. The faceted Si-cap layer matching the morphology of the previously used SiGe-cap enables healthy device parameters and it finally enabled the extension of this integration approach for SiGe/Si stressors to the more advanced technology nodes.
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J. Kasim et al. / Solid-State Electronics 110 (2015) 19–22
References [1] [2] [3] [4]
Horstmann M et al. IEDM Technical Digest, 2005, p. 233. Wei A et al. Proc SSDM 2005, p. 32. Ghani T et al. IEDM Technical Digest, 2003, p. 978. Kammler T, Peidous I, Wei A, Romero K, Reichel C, Heinemann S, et al. ECS Trans 2006;3(7):713.
[5] Reichel C, Zeun A, Beernink G, Waite A, Wiatr M, Kessler M, et al. Proc ICSI 2009;8:87. [6] Seger J, Jarmar T, Ericson F, Smith U, Hallstedt J, Zhang ZB, et al. J Appl Phys 2004;96:7179. [7] Dutartre D, Talbot A, Loubet N. ECS Trans 2006;3(7):473. [8] Loubet N, Talbot A, Dutartre D. Semicond Sci Technol 2007;22:S149. [9] Dutartre D, Seiss B, Campidelli Y, Pellissier-Tanon D, Barge D, Pantel R. Thin Solid Films 2012;520:3163.