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Comparison of oxide leakage currents induced by ion implantation and high field electric stress
Solid-State Electronics 45 (2001) 1355±1360
Comparison of oxide leakage currents induced by ion implantation and high ®eld electric stress D. Goguenheim a,*, A. Bravaix a, C. Monserie b,1, J.M. Moragues b,1, P. Lambert b,1, P. Boivin b,1 a
Laboratoire Mat eriaux et Microelectronique de Provence L2MP UMR CNRS 6137, Inst. Sup erieur d'Electronique de la M editerran ee ISEM, Maison des Technologies, Place Georges Pompidou, F-83000 Toulon, France b STMicroelectronics, Z.I.Rousset, B.P. 2, 13106 Rousset Cedex, France Received 20 March 2000
Abstract We compare in this work the electrical properties of gate leakage currents induced through the thin SiO2 oxide layer of metal-oxide-semiconductor structures by high-energy ion implantation (Boron B2 ) and high ®eld electrical stresses where electrons are injected from the gate in the Fowler±Nordheim regime. Even if the high-frequency capacitance± voltage characteristics are very dierent after both treatments, comparable increases and similar shapes are found at low ®eld in static gate current±voltage curves, typical of equivalent oxide damage. Moreover, these stress or implantation induced leakage currents are both removed in a similar way by a thermal anneal under forming gas at 430°C. We conclude that similar defects could be induced through the oxide by both processes and generate those excess currents by a defect assisted tunneling mechanism. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: SiO2 oxide; Boron; Ion implantation; Stress induced leakage currents; Fowler±Nordheim stress; Thermal anneal
1. Introduction The emergence of low-®eld excess leakage currents through the thin oxide thickness < 10 nm of metaloxide-semiconductor (MOS) structures is a common feature to many damaging processes encountered by the MOS device. It has already been reported after high ®eld electrical stresses leading to free carrier injections in the Fowler±Nordheim (FN) regime [1,2], uniform or localized hot hole injections [3±5], ionizing radiations [6] or plasma charging [7]. On another hand, ion implantation of dierent species directly or through many covering layers, followed by a thermal anneal to activate the dopants and to restore the silicon crystal integrity is now
* Corresponding author. Tel.: +33-494-038955; fax: +33-494038951. E-mail address: [email protected] (D. Goguenheim). 1 Tel.: +33-442-688953; fax: +33-442-532288.
a routine process in semiconductor industry. Many studies on the damage induced by the implant focus on defects and concentration pro®les found in bulk silicon after the implantation and their behavior during the anneal [8±18]. Indeed, the most well-known eect of implantation is the creation of a high-resistivity amorphous layer above a given threshold dose [8±10] due to the displacement of a large number of silicon atoms after scattering events with the ionic incoming atoms, and the generation of point, complex or extended defects like vacancies, interstitial clusters or dislocation loops [11± 14]. One important issue is to ®nd the most adequate implant parameters (species, dose, implant angle linked to the channeling eect) [15±17] and annealing conditions (temperature, duration, standard thermal anneal or rapid thermal anneal (RTA)) to lower this damage [8,18]. But few recent studies [19] deal with the eect of the implantation process on the oxide (silicon dioxide, SiO2 ) electrical properties when the implant is performed through it. So, the purpose of this work was to
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study and compare the electrical properties of oxide leakage currents induced by a high-energy ion implantation process (referred to in the following as implantation induced leakage currents, IILC) or high electric ®eld stresses (referred to as stress induced leakage currents, SILC). More precisely, we have focused on the oxide electric ®eld dependence and the passivation properties of those excess currents [20,21]. 2. Sample description and experiments The devices studied are P-type capacitors with N polysilicon±Si gates (area 20164 lm2 , polysilicon thickness 150 nm) recovered by W±Si (thickness 450 nm) on SiO2 tunnel oxide (oxide thickness Tox 7:6 nm. The samples have been implanted with boron (B2 ) through the tunnel oxide polysilicon WSi layer using an energy of 240 or 180 keV (dose: 4 1012 cm 2 ). We have performed three kinds of experiments: high-frequency capacitance±voltage measurements at 100 kHz (C(V)), static gate current vs gate voltage measurements (I(V)) and constant current (CCS) or voltage (CVS) stresses in non-implanted devices bias under negative gate voltage conditions chosen to induce electron injection from the gate in the FN regime. The 240 keV implanted and electrically stressed devices have then been submitted to a thermal anneal at 430°C during 45 min under forming gas N2 5%H2 .
Fig. 1. Eect of the stress on C(V) characteristics of nonimplanted devices ((Ð): virgin device, (D): after a CCS stress at IG 250 nA during 40 000 s, (m): after a CVS stress at VG 8:6 V during 11 000 s) compared to implanted ones ((s): 240 keV, (h): 180 keV).
3. Eect of the implant and of the electrical stress The eects of the 240 or 180 keV implantation and of the electrical stresses are shown in Fig. 1 on C(V) characteristics and in Figs. 2 and 3 on I(V) characteristics. From Fig. 1, we can deduce that two types of damage are induced by the implant: by the shift of the C(V) curve towards positive voltages a large negative ®xed charge (DNOX 2:0 1012 cm 2 in the 240 keV case and DNOX 1:5 1012 cm 2 in the 180 keV case), and by the strong stretch out of the curve a large interface state density (DNSS 2 1012 eV 1 cm 2 in the 240 keV case and DNSS 9 1011 eV 1 cm 2 in the 180 keV case around the mid-gap), while the electrical stresses have very little eect on the C(V) curve (DNSS 6 2.7 1011 eV 1 cm 2 around the mid-gap and DNOX 6 3 1011 cm 2 ). The evolution of the I(V) curve during a CVS stress is further compared in Fig. 2 to the ®nal characteristics obtained after a 240 or 180 keV implant. A more general comparison with dierent stressing conditions (CVS or CCS) is given in Fig. 3. It reveals that the low ®eld damage induced by the stresses has a similar shape (rather straight line on a log scale, characteristic of an exponential increase in the current) than the one induced by the implant on the I(V) char-
Fig. 2. Evolution of the I(V) characteristics during a CVS stress at VG 8:5 V during 40 000 s ((.): before stress, (Ð): during the stress, (m): after stress) and comparison to the damage due to a 240-keV (O) or a 180-keV (h) implant.
acteristics, but remains lower in magnitude, in spite of the huge values of the injected charge (up to 60 C cm 2 ). Contrary to the latter point, the C(V) characteristics in the implanted and stressed cases remain very dierent (Fig. 1) because the damage due to the implantation is much larger and not only located in the oxide and at the interface, but largely extends inside the bulk, where it induces point, complex or extended defects [8,12,13], or clusters of defects (interstitials, vacancies or complex) [11]. However, it can be shown [22] that this extra bulk damage has a similar electrical eect on the C(V) curve than two very important band tails in the interface state
D. Goguenheim et al. / Solid-State Electronics 45 (2001) 1355±1360
Fig. 3. Eect of the dierent CVS ((m): VG 8:6 V during 1:1 104 s) or CCS stresses ((r): IG 182 nA, ( ): IG 200 nA, (.): IG 250 nA during 4 104 s) on I(V) characteristics of non-implanted devices compared to implanted ones ((s): 240 keV, (h): 180 keV) and virgin non-implanted devices (Ð).
density located towards the bands, that would be induced by the implant in addition to the mid-gap interface state density value. This could be explained by considering that a large amount of bulk defects, and especially extended defects can generate, not only localized traps levels in the Si gap but also a continuous density of states in the gap throughout the damaged region of the substrate. As the C(V) technique is only sensitive to the cumulative charge trapped on defects and depending on the applied voltage, it explains why it can be represented by an extra interface state density, even if the defects are localized in the bulk. Additional experiments, like deep level transient spectroscopy or other charge transient experiments would be required to distinguish between bulk and interface contributions [8,18]. The FN plots of both total and excess parts of the current (Fig. 4) show that the resulting IILC and SILC components exhibit the classical feature of SILC currents, which is to be well ®tted by a FN component with an apparent energy barrier of approximately 1 eV [23]. We also see in Fig. 4 that the leakage low-®eld current in the implanted case is very close to the one obtained after stress in this representation, which is indicative of a similar damage and conduction mechanism in the bulk oxide, as these currents are known to be essentially limited by the bulk oxide properties.
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Fig. 4. FN plots of virgin (h), stressed (m): CVS stress at VG 8:6 V during 11 000 s, (.): CCS stress at IG 250 nA during 40 000 s, (D): SILC after the CVS stress, (Ñ): SILC after the CCS stress) and 240-keV-implanted devices ( ).
implanted samples. The main conclusions that arise are the following: (1) After the thermal anneal, we ®nd an important shift towards negative voltages of the C(V) curve in any case, i.e. stressed or implanted samples (see Figs. 5 and 6). This shift may be partly attributed to the passivation of the huge oxide negative charge trapped in the oxide in the case of implanted samples, but also to the induction in the oxide of a positive charge. This can be obtained by monitoring the shifts of the C(V) curves giving a variation of the oxide charge DNOX 5:8 1011 0:4 11 2 12 10 cm and DNOX 1:3 10 cm 2 in stressed and implanted samples respectively. Indeed it was found that this anneal induced a 3:5 1011 cm 2 positive charge just after the anneal even in virgin samples.
4. Eect of the thermal anneal We have analyzed (Figs. 5±9) the eects of the thermal forming gas anneal on stressed and 240-keV-
Fig. 5. C(V) characteristics of virgin (Ð), CVS stressed at VG 8:6 V during 11 000 s (m) and then annealed (Ñ) devices.
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Fig. 6. C(V) characteristics of non-implanted (h), 240-keVimplanted (D), and then annealed (.) devices.
Fig. 7. I(V) characteristics of virgin (Ð), CVS stressed at VG 8:6 V during 11 000 s (m) and then annealed (.) devices.
(2) The interface state density around mid-gap is largely passivated in both cases. However, we found a complete anneal DNSS 2:6 1011 eV 1 cm 2 in the case of stressed samples and only a partial anneal DNSS 5:6 1011 eV 1 cm 2 in the case of implanted samples. (3) The thermal treatment completely passivates the large shoulder in the accumulation regime of implanted devices representative of bulk localized or extended defects due to the implant (see and compare Figs. 1 and 6). According to Refs. [11,12], this removal of bulk damage after a 430°C anneal would be coherent with the dissociation, eective around this temperature, of vacancies and interstitial clusters (with a lower rate for vacancies than for interstitial clusters) ®rst induced by the implant. Those species would further diuse towards the Si/SiO2
Fig. 8. I(V) characteristics of non-implanted (h), 240-keVimplanted (m), and annealed (Ñ) devices.
Fig. 9. FN plots of virgin (h), 240-keV-implanted ( , s), CVS stressed at VG 8:6 V during 11 000 s (m, D) devices before ( , m) and after (h, s, D) anneal.
surface acting as a sink for migrating defects and where their recombination would take place. (4) Taking into account the shift in the I(V) curve due to the positive charge, it seems that the anneal also removes most of the excess current except a small shoulder at very low level in FN stressed samples (see Fig. 7). This feature is similar to the one obtained after an anneal on implanted devices (see Fig. 8). This point is even more evidenced on the FN plot of the current before and after anneal for implanted and stressed samples (see Fig. 9). It is shown here that taking into account the variations of the ¯at-band voltage in the calculation of the electric ®eld, IILC and SILC which are related to the 1-eV-like barrier part of the characteristics, are removed, and that one recovers the virgin characteristics (2.75 eV barrier part of the FN plot). The complete anneal after a ther-
D. Goguenheim et al. / Solid-State Electronics 45 (2001) 1355±1360
mal treatment above 300°C is a typical feature reported for SILC [20,21] probably related to the out diusion of charged defects like trapped holes or H . This would fully explain the total release of the negative charge that is trapped in the oxide during the implant. The identical behavior of IILC and SILC before and after the anneal is a strong indication that similar damage had been induced by both degradation processes in the oxide, as these excess currents are known to be directly linked to neutral oxide traps, through a defect assisted tunneling mechanism [24]. It is interesting to notice that the main damage of high-energy implantation through SiO2 is related to broken bonds or displaced atoms giving rise to numbers of unsaturated dangling bonds on Si or O atoms [19]. These electrically active point defects should induce localized levels in the gap of the bulk oxide that would trigger the defect assisted tunneling mechanism. Their passivation by a diusing hydrogen-related species during the thermal anneal could explain the observed decrease of IILC and of SILC in a similar way. 5. Conclusion We have found that SILC induced after high ®eld electric stresses and IILC induced by high-energy boron implantation through the oxide gate layer have similar electric ®eld dependence and thermal annealing properties under forming gas. These low-®eld leakage currents may arise from the same defect assisted tunneling mechanism through the oxide. The defects responsible for these currents are passivated in a similar way by a 430°C thermal anneal under forming gas. This is a strong indication that the same kind of electrically active defects could be induced by both damaging mechanisms through the oxide. References [1] Maserjian J, Zamani N. Behavior of the Si/SiO2 interface observed by Fowler±Nordheim tunneling. J Appl Phys 1982;53(1):559±67. [2] Olivo P, Nguyen TN, Ricco B. Modeling and simulation of stress-induced leakage current in ultrathin SiO2 ®lms. IEEE Trans Electron Dev 1993;ED-35(12):231±3. [3] Matsukawa N, Yamada S, Amemiya K, Hazama H. A hot hole-induced low-level leakage current in thin silicon dioxide ®lms. IEEE Trans Electron Dev 1996;ED-43(11): 1924±9. [4] Wang T, Zous NK, Lai JL, Huang C. Hot hole stress induced leakage current (SILC) transient in tunnel oxides. IEEE Electron Dev Lett 1998;EDL-19(11):411±3. [5] Goguenheim D, Bravaix A, Vuillaume D, Mondon F, Jourdain M, Meinertzhagen A. Stress induced leakage currents in N-MOSFETs submitted to channel hot carrier injections. J Non-Crystall Solids 1999;245:41±7.
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[6] Ceschia M, Paccagnella A, Scarpa A, Cester A, Ghidini G. The dependence of the ionizing radiation induced leakage current versus the total dose on ultra-thin gate oxides. Microelectron Reliab 1999;39(2):221±6. [7] Kim SU. Analysis of thin gate oxide degradation during fabrication of advanced CMOS ULSI circuits. IEEE Trans Electron Dev 1998;ED-45(3):731±6. [8] Duenas S, Castan E, Enriquez L, Barbolla J, Montserrat J, Lora-Tamayo E. Characterization of the damage induced in boron-implanted and RTA annealed silicon by the capacitance±voltage transient technique. Semicond Sci Technol 1994;9:1637±48. [9] M uller-Jahreis U, Thiele P, Boua®a M, Seghir A. Determination of low-energy ion implantation damage parameters by an ellipsometric method. J Phys III France 1995;5:575±84. [10] Milita S, Servidori M. Damage in ion implanted silicon measured by X-ray diraction. J Appl Phys 1996;79(11): 8278±84. [11] Benett DJ, Price TE. Distribution of damage clusters in ion-implanted silicon. Semicond Sci Technol 1993;8:1496± 500. [12] Bedrossian PJ, Caturla MJ, Diaz de la Rubia T. Damage evolution and surface defect segregation in low-energy ionimplanted silicon. Appl Phys Lett 1997;70(2):176±8. [13] Tian S, Morris MF, Morris SJ, Obradovic B, Wang G, Tasch AF, Snell CM. A detailed physical model for ion implant induced damage in silicon. IEEE Trans Electron Dev 1998;ED-45(6):1226±37. [14] Holland OW, Budai JD, Nielsen B. The role of defect excesses in damage formation in Si during ion implantation at elevated temperature. Mater Sci Engng 1998;A253:240± 8. [15] Carnera A, Gasparotto A, Berti M, Fabbri R. In¯uence of channeling eects on ion distribution and damage pro®les during high-energy ion implantation in Si. Mikrochim Acta 1994;114/115:205±11. [16] Hobler G, Simionescu A, Palmetshofer L, Tian C, Stingeder G. Boron channeling implantations in silicon: modeling of electronic stopping and damage accumulation. J Appl Phys 1995;77(8):3697±703. [17] Chao HS, Crowder SW, Grin PB, Plummer JD. Species and dose dependence of ion implantation damage induced transient enhanced diusion. J Appl Phys 1996;79(5):2352± 63. [18] Kaabi L, Ben Brahim J, Remaki B, Gontrand C, El Omari H, Bureau JC, Sassi Z, Balland B. The residual electrically active damage in low energy boron implanted silicon: rapid thermal annealing and implant mass eects. Eur Phys J Appl Phys 1998;3:49±52. [19] Garrido B, Samitier J, Morante JR, Montserrat J, Dominguez C. Con®gurational statistical model for the damaged structure of silicon oxide after ion implantation. Phys Rev B 1994;49(21):14845±9. [20] Riess P, Kies R, Ghibaudo G, Pananakakis G, Brini J. Reversibility of charge trapping and SILC creation in thin oxides after stress/anneal cycling. Microelectron Reliab 1998;38:1057±61. [21] Riess P, Ghibaudo G, Pananakakis G, Brini J. Annealing kinetics and reversibility of stress-induced leakage current in thin oxides. Appl Phys Lett 1998;72(23):3041±3.
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[22] Moragues JM, Lambert P, Monserie C, Boivin P, Bravaix A, Goguenheim D. Impact of Boron Implantation on thin oxide reliability. IEEE Trans.Electron Dev, submitted for publication. [23] Scarpa A, Ghibaudo G, Ghidini G, Pananakakis G, Paccagnella A. Stress induced leakage current in ultra-thin
gate oxides after constant current stress. Microelectron Engng 1997;36:145±8. [24] Chou AI, Lai K, Kumar K, Chowdhury P, Lee JC. Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism. Appl Phys Lett 1997;70(25):3407±9.
Comparison of oxide leakage currents induced by ion implantation and high ®eld electric stress D. Goguenheim a,*, A. Bravaix a, C. Monserie b,1, J.M. Moragues b,1, P. Lambert b,1, P. Boivin b,1 a
Laboratoire Mat eriaux et Microelectronique de Provence L2MP UMR CNRS 6137, Inst. Sup erieur d'Electronique de la M editerran ee ISEM, Maison des Technologies, Place Georges Pompidou, F-83000 Toulon, France b STMicroelectronics, Z.I.Rousset, B.P. 2, 13106 Rousset Cedex, France Received 20 March 2000
Abstract We compare in this work the electrical properties of gate leakage currents induced through the thin SiO2 oxide layer of metal-oxide-semiconductor structures by high-energy ion implantation (Boron B2 ) and high ®eld electrical stresses where electrons are injected from the gate in the Fowler±Nordheim regime. Even if the high-frequency capacitance± voltage characteristics are very dierent after both treatments, comparable increases and similar shapes are found at low ®eld in static gate current±voltage curves, typical of equivalent oxide damage. Moreover, these stress or implantation induced leakage currents are both removed in a similar way by a thermal anneal under forming gas at 430°C. We conclude that similar defects could be induced through the oxide by both processes and generate those excess currents by a defect assisted tunneling mechanism. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: SiO2 oxide; Boron; Ion implantation; Stress induced leakage currents; Fowler±Nordheim stress; Thermal anneal
1. Introduction The emergence of low-®eld excess leakage currents through the thin oxide thickness < 10 nm of metaloxide-semiconductor (MOS) structures is a common feature to many damaging processes encountered by the MOS device. It has already been reported after high ®eld electrical stresses leading to free carrier injections in the Fowler±Nordheim (FN) regime [1,2], uniform or localized hot hole injections [3±5], ionizing radiations [6] or plasma charging [7]. On another hand, ion implantation of dierent species directly or through many covering layers, followed by a thermal anneal to activate the dopants and to restore the silicon crystal integrity is now
* Corresponding author. Tel.: +33-494-038955; fax: +33-494038951. E-mail address: [email protected] (D. Goguenheim). 1 Tel.: +33-442-688953; fax: +33-442-532288.
a routine process in semiconductor industry. Many studies on the damage induced by the implant focus on defects and concentration pro®les found in bulk silicon after the implantation and their behavior during the anneal [8±18]. Indeed, the most well-known eect of implantation is the creation of a high-resistivity amorphous layer above a given threshold dose [8±10] due to the displacement of a large number of silicon atoms after scattering events with the ionic incoming atoms, and the generation of point, complex or extended defects like vacancies, interstitial clusters or dislocation loops [11± 14]. One important issue is to ®nd the most adequate implant parameters (species, dose, implant angle linked to the channeling eect) [15±17] and annealing conditions (temperature, duration, standard thermal anneal or rapid thermal anneal (RTA)) to lower this damage [8,18]. But few recent studies [19] deal with the eect of the implantation process on the oxide (silicon dioxide, SiO2 ) electrical properties when the implant is performed through it. So, the purpose of this work was to
0038-1101/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 0 ) 0 0 2 6 5 - 3
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study and compare the electrical properties of oxide leakage currents induced by a high-energy ion implantation process (referred to in the following as implantation induced leakage currents, IILC) or high electric ®eld stresses (referred to as stress induced leakage currents, SILC). More precisely, we have focused on the oxide electric ®eld dependence and the passivation properties of those excess currents [20,21]. 2. Sample description and experiments The devices studied are P-type capacitors with N polysilicon±Si gates (area 20164 lm2 , polysilicon thickness 150 nm) recovered by W±Si (thickness 450 nm) on SiO2 tunnel oxide (oxide thickness Tox 7:6 nm. The samples have been implanted with boron (B2 ) through the tunnel oxide polysilicon WSi layer using an energy of 240 or 180 keV (dose: 4 1012 cm 2 ). We have performed three kinds of experiments: high-frequency capacitance±voltage measurements at 100 kHz (C(V)), static gate current vs gate voltage measurements (I(V)) and constant current (CCS) or voltage (CVS) stresses in non-implanted devices bias under negative gate voltage conditions chosen to induce electron injection from the gate in the FN regime. The 240 keV implanted and electrically stressed devices have then been submitted to a thermal anneal at 430°C during 45 min under forming gas N2 5%H2 .
Fig. 1. Eect of the stress on C(V) characteristics of nonimplanted devices ((Ð): virgin device, (D): after a CCS stress at IG 250 nA during 40 000 s, (m): after a CVS stress at VG 8:6 V during 11 000 s) compared to implanted ones ((s): 240 keV, (h): 180 keV).
3. Eect of the implant and of the electrical stress The eects of the 240 or 180 keV implantation and of the electrical stresses are shown in Fig. 1 on C(V) characteristics and in Figs. 2 and 3 on I(V) characteristics. From Fig. 1, we can deduce that two types of damage are induced by the implant: by the shift of the C(V) curve towards positive voltages a large negative ®xed charge (DNOX 2:0 1012 cm 2 in the 240 keV case and DNOX 1:5 1012 cm 2 in the 180 keV case), and by the strong stretch out of the curve a large interface state density (DNSS 2 1012 eV 1 cm 2 in the 240 keV case and DNSS 9 1011 eV 1 cm 2 in the 180 keV case around the mid-gap), while the electrical stresses have very little eect on the C(V) curve (DNSS 6 2.7 1011 eV 1 cm 2 around the mid-gap and DNOX 6 3 1011 cm 2 ). The evolution of the I(V) curve during a CVS stress is further compared in Fig. 2 to the ®nal characteristics obtained after a 240 or 180 keV implant. A more general comparison with dierent stressing conditions (CVS or CCS) is given in Fig. 3. It reveals that the low ®eld damage induced by the stresses has a similar shape (rather straight line on a log scale, characteristic of an exponential increase in the current) than the one induced by the implant on the I(V) char-
Fig. 2. Evolution of the I(V) characteristics during a CVS stress at VG 8:5 V during 40 000 s ((.): before stress, (Ð): during the stress, (m): after stress) and comparison to the damage due to a 240-keV (O) or a 180-keV (h) implant.
acteristics, but remains lower in magnitude, in spite of the huge values of the injected charge (up to 60 C cm 2 ). Contrary to the latter point, the C(V) characteristics in the implanted and stressed cases remain very dierent (Fig. 1) because the damage due to the implantation is much larger and not only located in the oxide and at the interface, but largely extends inside the bulk, where it induces point, complex or extended defects [8,12,13], or clusters of defects (interstitials, vacancies or complex) [11]. However, it can be shown [22] that this extra bulk damage has a similar electrical eect on the C(V) curve than two very important band tails in the interface state
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Fig. 3. Eect of the dierent CVS ((m): VG 8:6 V during 1:1 104 s) or CCS stresses ((r): IG 182 nA, ( ): IG 200 nA, (.): IG 250 nA during 4 104 s) on I(V) characteristics of non-implanted devices compared to implanted ones ((s): 240 keV, (h): 180 keV) and virgin non-implanted devices (Ð).
density located towards the bands, that would be induced by the implant in addition to the mid-gap interface state density value. This could be explained by considering that a large amount of bulk defects, and especially extended defects can generate, not only localized traps levels in the Si gap but also a continuous density of states in the gap throughout the damaged region of the substrate. As the C(V) technique is only sensitive to the cumulative charge trapped on defects and depending on the applied voltage, it explains why it can be represented by an extra interface state density, even if the defects are localized in the bulk. Additional experiments, like deep level transient spectroscopy or other charge transient experiments would be required to distinguish between bulk and interface contributions [8,18]. The FN plots of both total and excess parts of the current (Fig. 4) show that the resulting IILC and SILC components exhibit the classical feature of SILC currents, which is to be well ®tted by a FN component with an apparent energy barrier of approximately 1 eV [23]. We also see in Fig. 4 that the leakage low-®eld current in the implanted case is very close to the one obtained after stress in this representation, which is indicative of a similar damage and conduction mechanism in the bulk oxide, as these currents are known to be essentially limited by the bulk oxide properties.
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Fig. 4. FN plots of virgin (h), stressed (m): CVS stress at VG 8:6 V during 11 000 s, (.): CCS stress at IG 250 nA during 40 000 s, (D): SILC after the CVS stress, (Ñ): SILC after the CCS stress) and 240-keV-implanted devices ( ).
implanted samples. The main conclusions that arise are the following: (1) After the thermal anneal, we ®nd an important shift towards negative voltages of the C(V) curve in any case, i.e. stressed or implanted samples (see Figs. 5 and 6). This shift may be partly attributed to the passivation of the huge oxide negative charge trapped in the oxide in the case of implanted samples, but also to the induction in the oxide of a positive charge. This can be obtained by monitoring the shifts of the C(V) curves giving a variation of the oxide charge DNOX 5:8 1011 0:4 11 2 12 10 cm and DNOX 1:3 10 cm 2 in stressed and implanted samples respectively. Indeed it was found that this anneal induced a 3:5 1011 cm 2 positive charge just after the anneal even in virgin samples.
4. Eect of the thermal anneal We have analyzed (Figs. 5±9) the eects of the thermal forming gas anneal on stressed and 240-keV-
Fig. 5. C(V) characteristics of virgin (Ð), CVS stressed at VG 8:6 V during 11 000 s (m) and then annealed (Ñ) devices.
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Fig. 6. C(V) characteristics of non-implanted (h), 240-keVimplanted (D), and then annealed (.) devices.
Fig. 7. I(V) characteristics of virgin (Ð), CVS stressed at VG 8:6 V during 11 000 s (m) and then annealed (.) devices.
(2) The interface state density around mid-gap is largely passivated in both cases. However, we found a complete anneal DNSS 2:6 1011 eV 1 cm 2 in the case of stressed samples and only a partial anneal DNSS 5:6 1011 eV 1 cm 2 in the case of implanted samples. (3) The thermal treatment completely passivates the large shoulder in the accumulation regime of implanted devices representative of bulk localized or extended defects due to the implant (see and compare Figs. 1 and 6). According to Refs. [11,12], this removal of bulk damage after a 430°C anneal would be coherent with the dissociation, eective around this temperature, of vacancies and interstitial clusters (with a lower rate for vacancies than for interstitial clusters) ®rst induced by the implant. Those species would further diuse towards the Si/SiO2
Fig. 8. I(V) characteristics of non-implanted (h), 240-keVimplanted (m), and annealed (Ñ) devices.
Fig. 9. FN plots of virgin (h), 240-keV-implanted ( , s), CVS stressed at VG 8:6 V during 11 000 s (m, D) devices before ( , m) and after (h, s, D) anneal.
surface acting as a sink for migrating defects and where their recombination would take place. (4) Taking into account the shift in the I(V) curve due to the positive charge, it seems that the anneal also removes most of the excess current except a small shoulder at very low level in FN stressed samples (see Fig. 7). This feature is similar to the one obtained after an anneal on implanted devices (see Fig. 8). This point is even more evidenced on the FN plot of the current before and after anneal for implanted and stressed samples (see Fig. 9). It is shown here that taking into account the variations of the ¯at-band voltage in the calculation of the electric ®eld, IILC and SILC which are related to the 1-eV-like barrier part of the characteristics, are removed, and that one recovers the virgin characteristics (2.75 eV barrier part of the FN plot). The complete anneal after a ther-
D. Goguenheim et al. / Solid-State Electronics 45 (2001) 1355±1360
mal treatment above 300°C is a typical feature reported for SILC [20,21] probably related to the out diusion of charged defects like trapped holes or H . This would fully explain the total release of the negative charge that is trapped in the oxide during the implant. The identical behavior of IILC and SILC before and after the anneal is a strong indication that similar damage had been induced by both degradation processes in the oxide, as these excess currents are known to be directly linked to neutral oxide traps, through a defect assisted tunneling mechanism [24]. It is interesting to notice that the main damage of high-energy implantation through SiO2 is related to broken bonds or displaced atoms giving rise to numbers of unsaturated dangling bonds on Si or O atoms [19]. These electrically active point defects should induce localized levels in the gap of the bulk oxide that would trigger the defect assisted tunneling mechanism. Their passivation by a diusing hydrogen-related species during the thermal anneal could explain the observed decrease of IILC and of SILC in a similar way. 5. Conclusion We have found that SILC induced after high ®eld electric stresses and IILC induced by high-energy boron implantation through the oxide gate layer have similar electric ®eld dependence and thermal annealing properties under forming gas. These low-®eld leakage currents may arise from the same defect assisted tunneling mechanism through the oxide. The defects responsible for these currents are passivated in a similar way by a 430°C thermal anneal under forming gas. This is a strong indication that the same kind of electrically active defects could be induced by both damaging mechanisms through the oxide. References [1] Maserjian J, Zamani N. Behavior of the Si/SiO2 interface observed by Fowler±Nordheim tunneling. J Appl Phys 1982;53(1):559±67. [2] Olivo P, Nguyen TN, Ricco B. Modeling and simulation of stress-induced leakage current in ultrathin SiO2 ®lms. IEEE Trans Electron Dev 1993;ED-35(12):231±3. [3] Matsukawa N, Yamada S, Amemiya K, Hazama H. A hot hole-induced low-level leakage current in thin silicon dioxide ®lms. IEEE Trans Electron Dev 1996;ED-43(11): 1924±9. [4] Wang T, Zous NK, Lai JL, Huang C. Hot hole stress induced leakage current (SILC) transient in tunnel oxides. IEEE Electron Dev Lett 1998;EDL-19(11):411±3. [5] Goguenheim D, Bravaix A, Vuillaume D, Mondon F, Jourdain M, Meinertzhagen A. Stress induced leakage currents in N-MOSFETs submitted to channel hot carrier injections. J Non-Crystall Solids 1999;245:41±7.
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