Stress induced leakage currents in thin oxides

MICROELECTRONIC ENGINEERING ELSEVIER

Stress Induced

Microelectronic

Engineering

Leakage Currents

28 (1995) 63-66

in Thin Oxides

I>. .J. DiMaria IBM I’. .J. Watson

Research

(:enter,

I,eakage currents introduced in dioxide layers after high-field stress port in the oxide layer. I;rorn these electron traps in thin oxides are the

P.0. Box 218, Yorktown

llcights,

NY 10.598

the low-lield, direct-tunneling regime of thin silicon arc related to defects produced by hot electron transstudies, it is concluded that the “generation” of neutral dominant cause of this phenomenon.

1. INTRODUCTION

In the early 1980’s, Maserjian and %amani Jirst reported the observation that currents measured on thin silicon dioxide (SK),) layers (4-S nm thick) at low applied-electric-Jields were performed increased after stressing at high Jields.’ ‘I‘hc low-&Id current mcasurcments where direct tunneling (DT) was operative, typically 5 3 V for n-type silicon (Si) or aluminum (Al) electrodes. In the 117’regime, electrons tunnel directly from cathode to anode contact. l‘he stressing was performed at higher fields under Fowler-Nordheim (FN) conditions where electrons tunnel first into the oxide conduction band before entering the anode contact. Although electron heating in SK), was not a well understood phenomenon until the mid-1980’s,27’ Maserjian and Zamani assumed that the increase in the IX current was caused by oxide film dctcrioration under stress conditions producing hot electrons.’ ‘I‘hcy ftlrthcr tried to relate the DI’ current increaxcs to the presence of positive oxide charges found near the anode after FN stress. Since their seminal report, many researchers have repeated the experiments of Maserjian and Zamani obtaining similar results .4-e Some researchers have proposed that these stressinduced-leakage-currents (SII,(:s) are caused by interface-state gcncration,a while others claim that it is due to bulk-oxide clcctron-trap-generation. 5 Also recently, the positive charge model of Maserjian and Zamani has re-appeared with the charges due to trapped holes injected from the anode. 7 In the study undertaken here, all possibilities have been examined with the conclusion that the best explanation is due to the generation of neutral oxide-electron-traps.

2. EXPERIMENTAL In these studies, many wafer sets containing both n- and p-channel Jield-efrccttransistors (IFI’s) of various sizes and geometries fabricated over a period of IO years have been studied. ‘I‘he Si substrates were ( 100) orientation with resistivitics varying from 0. I to 30 ohm-cm and oxide thickness varying from 3.7 to 5.5 nm. All gate clectrodcs were n-type, degenerately-doped, self-aligned poly-Si with areas varying from 6.4.5x10-4 to 8.95x10-6 0167.9317/95/$09.50 D 1995 - Elsevier Science B.V. All rights reserved. SSDZ0167-9317(95)00016-X

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D. J. DiMaria / Microelectronic Engineering 28 (1995) 63-66

~1112.All gate oxides wcrc thermally grown at a temperature IIcrc did not dcpcnd on device arca or gcomctry.

of 900 (1. The results prcscntcd

A wide variety of measurement techniques have been used to track and spatially locate the trapped oxide charge (both positive and negative) and interface states. ‘fhcse included high-frequency capacitance-voltage ((IV), current-voltage (IV), and current as a function of time (It) on FIX dcvices.839 The CV technique was used to measure oxide charges and intcrfacc states (“fast” and “slow”). The It and IV techniques were used to measure the magnitude of oxide charge, locate the charge spatially, and sense for lateral nonuniformities (1,NUs). All measurements were performed at room tempcraturc. 2.1. Stress Induced

Leakage Currents Although many researchers have used ramped-voltage techniques to investigate SII,Cs, the cfl‘ects of the oxide field and injected electron fluence can not be easily separated. ‘1‘0 minitni/c this problem, SILCs can be generated by stressing at constant applied field (gate voltage) for increasingly larger amounts of I:N-injected electron-flucnce. After stressing, the resulting SII,C is measured at a lower gate voltage where electron energy and fluence not do produce any additional oxide damage or current increases.

An cxamplc of these SII,C mcasurcments is shown in Fig. I. I Icre, normalized current incrcascs arc plotted as a function of FN-injcctcd electron fluence during stress for various stressing conditions ( I~,sf~Pss).‘I‘he sensing voltage ( P’ET*n”e) used to measure the SII,(:s after stressing was 3 V. The normalized current increase (A.I+.I,) is defined by A.J = .J - .I, where .I, and .I are the initial current of the as-fabricated device and the current measured after 1-N stress (SI 1-C) at the sensing voltage, respectively. ‘1‘0 investigate the dependence of SII,Cs on hot-electron energy during stress, the data in I?g. 1 have been manipulated to obtain SIK generation-probabilities (Fig. 2) as a function of gate voltage stress. The data in IGg. 2 arc obtained from the slopes of the data in IGg. I in the linear regime. These data show a strong increase near 5 V. This corresponds to z 2 eV for a ballistic electron in the SK), arriving at the anode/oxide interface (5 V minus the -_ 3 V barrier at the cathode/oxide interface).” 2.2. Oxide Charging and Defects In this section, trap creation will be shown to correlate energetically with SII,Cs. IIole gcncration by any mode (bandgap impact ionization or anode injection) does not. Many difrcrcnt defects sites with din‘ercnt processing dependencies from one wafer run to another ‘l‘hesc dcfccts include intcrfacc states, gencrationcan occur with trap creation. rccomhination centers in the Si substrate, neutral electron traps in the oxide bulk distributcd away from the cathodc/oxidc interface, and positively-charged oxide-sites (mostly “slow states”) near the anode/oxide interfacc8r9 lising a combination of(Y and It techniques for difl‘erent gate polarities, the interface states and trapped oxide charges (both positive and negative) can be determined as a function of FN-injected electron fluence for various stress voltages (electron energies). An example of these mcasurcments is shown in I?g. 3 on devices similar to those used to obtain the SII,C data (see Fig. I). With increasing fluence, these data show a transition from a positive charge state of the oxide caused by hole trapping (iv*) to a “net” negative charge state (Nn) caused mostly by trap creation. This type of characteristic has been discussed previously in structures with thicker oxide layers where most of the holes wcrc produced

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12

D. J. DiMaria / Microelectronic Engineering 28 (I 995) 63-66

66

by bandgap ionization9 The plateau regions for the positive charge build-up is due to a steady-state condition caused by trapped-hole/free-electron annihilation.9 The negative charge state shown in l?g 3 is the “net” sum of both the positive charges from the trapped holes (if present), background electron trapping in as-fabricated sites (usually a small amount on thin films), and clcctron trapping in some of the neutral-electron-traps generated during trap creation.9 Similar to the procedure used for the calculation of SILC generation rates using the slope of the data in the linear region, the trapped charge verses fluence data in Fig. 3 has been converted into the trapping/generation probabilities verse ITN-stressing voltage shown in t:ig. 4. Figure 4 shows that hole trapping (therefore, generation) can only be detected in thin oxides at positive gate voltages greater than z 8 V (or I&, z 5 eV). Since SItXs appear at electron energies of zz 2 eV, hole generation/trapping by any mechanism will not be considered further. Also shown in I:ig. 4 arc two other forms of charge buildup. ‘l‘hcsc are negative charge buildup in the neutral electrons traps distributed away from the cathode/oxide interface and positively-charged (N,) donor-like “slow’ states created in the SiO, near the anode/oxide interface.8~9 Both the trapped electrons and the positively-charged sites show approximately the same 2 eV threshold (= 5 V of stress voltage dropped across the SiO,) charactcristic of trap creation. 8~9The generation probabilities for the anode positive charge were determined in a similar manner to that for the electron trapping using CV and It measurcments under negative-gate-voltage stressing on similar devices. Although not shown here, the interface state densities determined from the broadening of the hf-CV characteristics of the IX’t‘s were small (on the order ofz 1x10~~)cm-2) for the wafer set used for these data. 3. CONCLUSIONS Clearly, the trap creation phenomenon is important in understanding SlLCs. IIowcvcr, it is not obvious which defect component or components (interface states, distributed neutral-electron traps, or positively-charged sites near the anode) controls the SIIX ohservations. To reduce the possibilities, the defect generation due to trap creation was compared to the Stt,Cs for direrent wafer sets fabricated ycdrs apart using direrent Si-processing technologies. Overall, the neutral electron traps were shown to give the best correlation with StI,Cs on the same devices. Since these generated sites are less than half full of electrons at the stress fields used here, 879they can easily act as “stepping stones” for the tunneling carriers in the D’t regime. REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9.

.I. Maserjian and N. Zamani, .J. Appl. Phys. 53, 559 (1982). D..J. DiMaria, T.N. ‘I‘heis, .J.R. Kirtley, 17.1,. I’esavento, D.W. Dong, and S. I). Brorson, J. Appl. Phys. 57, 1214 (1985). M.V. Fischctti, D.J. DiMaria, I,. Dori, .J. Batey, E. Tierney, and J. Stasiak, Phys. Rev. B 35, 4404 (1987). R.R. Rofan and C. 1Iu, lIZI Jllectron I>ev. J,ett. 22, 632 (1991). D..J. Dumin, IIZIIE Trans. I+.zctron Dev. 40, 986 (1993). N.K. Pate1 and A. Toriumi, Appl. t’hys. Lett. 64, 1809 (1994). K.1;. Schuegraf and C. IIu, 1131E Trans. on Electron Dcv. 41, 761 (1994). D..J. DiMaria and .J.W. Stasiak, J. Appl. Phys. 65, 2342 (1989). 1l.J. DiMaria, II. Cartier, and 1). Arnold, J. Appl. Phys. 7.1, 3367 (1993).