- Email: [email protected]
GaN HEMTs
Microelectronics Reliability 51 (2011) 224–228
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Critical factors influencing the voltage robustness of AlGaN/GaN HEMTs M. Cäsar ⇑, M. Dammann, V. Polyakov, P. Waltereit, R. Quay, M. Mikulla, O. Ambacher Fraunhofer Institute for Applied Solid-State Physics, Tullastr. 72, D-79108 Freiburg, Germany
a r t i c l e
i n f o
Article history: Received 16 July 2010 Received in revised form 3 September 2010 Accepted 7 September 2010 Available online 13 October 2010
a b s t r a c t The influence of the electric field on the reliability of AlGaN/GaN HEMTs is investigated in this work. We first demonstrate that at a certain electric field strength at the gate edge the gate characteristics of the device changes. This degradation is irreversible and is strongly influenced by growth parameter. A drain-voltage step-stress method is applied to the devices for investigating different layouts, and a consequent application enabled us to assign parameters mitigating the peak field strength and improve reliability. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Microelectronic devices based on nitride materials offer a variety of intrinsic advantages like high breakdown voltage and high saturation velocity, which makes them ideal candidates for highfrequency and high-power applications [1]. The most commonly used nitride device realization, the AlGaN/GaN HEMT, is still facing reliability problems even after years of intensive research [2]. One major setback of these devices is a reduction of the output current under pulsed operation, the so-called current collapse [3]. Furthermore, a possible degradation of the fabricated structure, induced by the inverse piezo effect, may also limit the stability during device operation [4]. This effect potentially induces a defective region in the layer structure, resulting from an increased strain in the AlGaN-barrier. 2. Technology and experimental 2.1. Technology The AlGaN/GaN HEMTs investigated in this work have a gate length of 0.25 lm and are optimized for X-band-application. The processing is described by Dammann [5]. A schematic cross section is presented in Fig. 1. The devices consist of an AlGaN/GaN heterostructure which is grown on semi-insulating SiC substrates by MOCVD and provides excellent 2 DEG-channel densities (8 1012 cm2) and mobilities (1500 cm2/Vs). The device processing is performed by standard techniques using e-beam and optical lithography. To improve reliability, the transistor is equipped with a field plate on the drain side edge of the gate with length of lFP and the field plate has a distance to the semiconductor surface, which is ⇑ Corresponding author. Tel.: +49 761 5159 231; fax: +49 761 5159 565. E-mail address: [email protected] (M. Cäsar). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.09.006
covered with a passivation of silicon nitride, of thickness t. The integration into MMICs is done in microstrip transmission line technology with substrate thinning to 100 lm and backside processing with via holes. In standard monitorings after processing a high uniformity across a single wafer (uniformity in sheet resistance better than 3%), as well as high reproducibility from wafer to wafer is confirmed [6]. For reliability assessment in this work, 8 60 lm wide HEMTs are investigated on wafer.
2.2. Experimental 2.2.1. Characteristics of the observed degradation 2.2.1.1. Degradation monitoring and key figures. A weak point in a polar semiconductor HEMT is located in the vicinity of the drain edge of the gate, where large electric fields during voltage-robustness-test can be created. By stepwise increasing of the potential difference, i.e. drain voltage, a study of degradation phenomena can be performed when the device integrity is checked. A typical voltage-robustness-test, a HTRB-step-stress-test (High-Temperature-Reverse-Bias), is applied under pinch-off condition at high temperature, and degradation of the AlGaN/GaN HEMT can be observed. In order to study this phenomena, this step-stress-testing method (steps of DUD = 2 V every 10 min with UG = 7 V) was applied to devices fabricated at Fraunhofer on two different Epitaxys (Epi A and Epi B). The structures were grown under different conditions, leading to differences in their mechanical as well as in their electrical properties. This is apparent in 25% increased drain saturation current for Epi B, whereas the initial strain is also increased by 50% for Epi B. During the measurement, Epi A shows no indication of degradation in Fig. 2, as it exhibits a constant level of gate current throughout the whole test (until UD = 86 V), with only a slight increase of the reverse gate current. The identical test performed on Epi B however results in a sudden increase in both forward and reverse
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225
Fig. 1. Schematic layer structure of the investigated AlGaN/GaN HEMT.
Fig. 4. Schottky characteristics (at T = 150 °C) from the HTRB-step-stress-test from Fig. 2 for Epi B.
Fig. 2. Ig_off (UG = 5 V; UD = 0 V) and Ig_on (0.2 V; 0 V) in a HTRB-Test with UG = 7 V, T = 150 °C.
gate current at a critical voltage of UD = 38 V, when device degradation sets in. Similar degradation during reverse bias testing is observed by Joh and del Alamo [4]. These deviations for varied growth conditions are further apparent in the Schottky characteristics, where devices from Epi A in Fig. 3 exhibits the same behavior throughout the test, with only small changes resulting from the measurement procedure. On the contrary, characteristics from Epi B in Fig. 4 show an behav-
Fig. 3. Schottky characteristics (at T = 150 °C) from the HTRB-step-stress-test from Fig. 2 for Epi A.
Fig. 5. Schottky barrier height and ideality factor from HTRB-step-stress-test from Figs. 3 and 4.
ior around the critical voltage, where a change in carrier transport dynamic seems to be appearing. Until UD = 36 V in the test, the measurements show almost identical IV-characteristic. The characteristic after the UD = 38 V stress-step however, shows a different behavior in reverse and forward direction compared to the previous observed. From this point onwards, degradation of the Schottky contact sets in and a steady increase in gate current is observable after each voltage step. This effect can be shown more pronounced, when the evaluated Schottky parameter are inspected in Fig. 5, showing a severe degradation of the Schottky barrier height in conjunction with an ideality factor increase after the critical voltage is achieved. The increase in the Schottky current is enlarged in the lower voltage region, where the transport mechanism is normally governed by a recombination of electrons from the Schottky barrier with holes from the semiconductor in the depletion zone under the gate [7]. We therefore speculate that the elevated current is either caused by increased recombination, which would on the other hand require additional recombination centers like traps created during test [2]. Another possibility is an enhanced tunneling of the injected electrons from the gate through the AlGaN-barrier on crystallographic defects [8]. This would minimize the lifetime of the carrier in the depletion zone before the tunneling process occurs. With both interpretations, the increased ideality factor and a lower Schottky barrier height could be explained.
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Fig. 8. HTRB-Test for different gate voltages at T = 150 °C on Epi B.
Fig. 6. Schottky characteristics (at T = 50 °C) after Illumination with UV-light for a device with Epi B.
Table 1 Extracted Schottky parameters from the measurements of Figs. 6 and 7 for devices after HTRB-Test and UV-illumination or storage.
n
U (eV)
n
U (eV)
Before test
After test
After storage
1.20 1.28
1.62 0.77
1.64 0.74
Before test
After test
After UV-Illum
1.31 1.11
1.66 0.73
1.65 0.73
The devices were exposed to an HTRB-Test (until UD = 86 V) with aforementioned degradation indications, and subsequently stored for t = 150 h at T = 200 °C. As apparent in Fig. 7, the Schottky characteristic remain almost unchanged after storage. This behavior is verifying the assumption, that reverse bias testing induces a permanent degradation of the device. These findings also reduce the role of diffusion processes as a degradation driver, since no further degeneration of the device characteristic is evident, even at higher temperature during the voltage-stress time. 2.2.1.4. Verification of a voltage driven degradation. Further proof of a voltage depended degradation is given with the experiment given in Fig. 8, where a series of HTRB-Test (steps of DUD = 2 V every 1 min) with different gate voltages starting at 3 V (below PinchOff) to 7 V is applied to each time a new device. As observable in this figure, a more negative biasing of the gate leads to an early onset and a stronger degradation of the device shown by the in situ gate current. A reason for this behavior is found when the higher electric field in the vicinity of the gate due to the increased gate potential is taken into account. This enhanced electric field leads to stronger degradation as previous discussed. 2.2.2. Influence of technological parameters on field distribution Realizing the detrimental effect of electric fields higher than a certain critical value, a field plate in conjunction with the passivation layer is implemented in our device structure to adjust the field distribution. An accurate design reduces the field strength at the gate edge and increases the starting voltage when device
Fig. 7. Schottky characteristics (at T = 50 °C) after HTRB-Test and storage at 200 °C for 150 h on Epi B.
2.2.1.2. Recoverability of degradation. In order to study the recoverability within this degradation scheme, the device was exposed to an HTRB-Test as described above (until UD = 86 V). The device showed the same degradation indications as previous observed and the gate characteristics are presented in Fig. 6. Afterwards the devices were exposed to UV-light (kmin 305 nm, 4 eV) for 30 min and characterized again, which is also presented in Fig. 6. As observable, an illumination of the device is not changing the Schottky characteristics of the device. This fact of non-recoverability is also noticeable in the extracted Schottky parameter in Table 1. 2.2.1.3. Stability of degradation. Additionally the long term stability of the induced degradation at elevated temperature was studied.
Fig. 9. Density of interface states of special grown MIS-structures for passivations with different refractive index.
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degradation occurs [9]. We applied our step-stress-testing method presented in the previous section and evaluated different layouts and parameters. From this measurements we can conclude, that an increase of the length of the field plate, a higher dielectric constant of the passivation as well as a decrease of the thickness of the passivation layer have a positive effect on degradation behavior. 2.2.2.1. Dielectric constant. While evaluating different passivation methods, a significant impact of the composition of the passivations on the device characteristic was observed. One possible explanation is demonstrated in Fig. 9, where different densities of interface states on special fabricated MIS-structures on GaN for different passivations (characterized by their refracting index) are presented. A higher density of interface states is supposed to be responsible for reduced device performance [10]. In order to only account for the intrinsic effects of different passivations, an experimental verification was withdrawn and the impact of different passivation methods on the field distribution was calculated using the commercial software package ATLAS SILVACO. The outcome is illustrated in Fig. 10, where a reduced electric field at the gate edge is apparent for the device possessing a passivation layer with the higher dielectric constant. This fact can be explained, when an enhanced drop of the potential in the region under the field plate and the passivation is considered, leading to smaller field strength at the gate edge, as indicated in Fig. 10. 2.2.2.2. Passivation layer thickness. The influence of the thickness of the passivation on the degradation behavior was investigated with an HTRB-step-stress-test with a different nitride. The in situ gate current for a thickness t1 and a thickness t2 = 2 t1 are compared in Fig. 11. In the case of t1 thickness, no degradation is apparent, with very low gate currents (Ig < 300 nA/mm) throughout the test. For the device with thickness t2 an increase of the gate current occurs after t = 300 min of stress time, when device degradation sets in and a steady increase of the current is observed. This observation is also seen when the gate characteristics of the two transistors before and after the test are considered in Fig. 12. Here, the device with thickness t2 is showing a noticeable increase in reverse and forward gate current, whereas the device with thinner passivation t1 shows no signs of degradation. Extractions of the Schottky parameters, which are presented in Table 2, reveal the same indication with the aforementioned degradation signs.
Fig. 10. Simulation of the modulus of the electric field for passivation with different dielectric constants under constant voltage operation.
Fig. 11. Gate currents during step-stress-testing (UG = 7 V, T = 150 °C, DUD = 5 V/ 60 min, UD_start = 30 V) with different nitride thicknesses t2 = 2 t1 and lFP2.
Fig. 12. Gate characteristics of devices before and after the test with different passivation thicknesses as shown in Fig. 11.
Table 2 Extracted Schottky parameters from the measurements of Fig. 12 with different nitrite thicknesses. Device/thickness
Value
Before
After
t1 t2 t1 t2
U (eV) U (eV)
1.10 1.04 1.61 1.75
1.10 0.87 1.60 2.30
n n
2.2.2.3. Field plate length. Another factor influencing the voltage robustness was identified, when the dependence of the field plate length on the drain side of the gate was investigated with an HTRBTest. Devices with a length of lFP1, lFP2 > lFP1 and lFP3 > lFP2 of the field plate were fabricated and exposed to the same test as described before. The results are shown in Fig. 13, where one can observe a significantly reduced gate current for longer field plates. In Fig. 14, the corresponding gate characteristics of the devices before and after the test are presented, showing a reduced degradation for longer field plates. This observation is in line with the measured higher gate current during the test. Furthermore, the extracted Schottky parameters in Table 3 exhibits the same degradation indications as observed in previous sections with a decrease of the barrier height and an increase of the ideality factor.
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effect is more pronounced on the maximum oscillating frequency than on the transition frequency [11]
fT;i ; fmax ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Rs þRg 2:5C GD 1 þ R Þ 4 ggds g m Rgs þ Rs þ1=g þ 45 CCGD ð1 þ g s gm C GS GS m
Fig. 13. Gate currents of devices during step-stress-testing (UG = 7 V, T = 150 °C, DUD = 5 V/60 min, UD_start = 30 V) with different field plate length and nitride thickness t2.
m
which can be deduced from the equation, since an unpleasant ratio of the gate-drain capacitance (CGD) compared to the gate source capacitance (CGS) is achieved, resulting in a strong reduction of the fmax. We investigated the effect of this change in the capacitances on the rf-characteristics with the devices from the HTRB-Test observable in Fig. 13. The increased field plate length for lFP2 implies a reduction of the maximum available gain of 1 db gain compared to the device with lFP1, and the fmax changes from 40 GHz to 37.2 GHz. The extracted Gate–Drain capacitance increases from 102 fF/mm for lFP1 to 122 fF/mm for lFP2. Extension of the field plate to lFP3 instead of the length lFP2 diminishes the rf-performance by another 1 dB in the maximum available gain, the fmax decreases to 34 GHz and CGD increases to 144 fF/mm. 3. Summary and conclusion The results from this work indicate that the electric field strength at the gate edge beyond a certain point harms the device. This degradation is permanent and cannot be recovered, and is strongly depended on epitaxial growth parameter. During technology evaluation to mitigate the peak electric field strength, it was found that the passivation thickness, the permittivity of the passivation layer and the field plate extent have a positive influence on the reliability behavior, which on the other side reduce the rf-performance. When comparing the effect of investigated parameter during growth and processing of AlGaN/GaN HEMTs in the framework of this study, a trade-off between power and stability during operation of this technology is suggested. Acknowledgements
Fig. 14. Gate characteristics of devices before and after the test with different field plate length as shown in Fig. 13.
Table 3 Extracted Schottky parameters from the measurements of Fig. 14 with different field plate length. lFP1
n
U (eV)
lFP2
lFP3
Before
After
Before
After
Before
After
2.16 0.93
6.55 0.38
1.93 1.01
3.76 0.53
2.13 0.96
2.13 0.96
2.2.3. Influence of the critical factors on rf-performance The technological parameters investigated in the previous paragraphs, which improve the voltage robustness of the device, change on the other side the rf-performance during device operation. For instance, the extension of the field plate as seen in Fig. 7 results in an enlargement of the gate capacitance (CG), which influences as a consequence the transition frequency.
fT ¼
gm : 2pC G
The increase of the field plate on the drain edge side has in addition a more severe impact on the gate-drain capacitance CGD. This
The authors acknowledge financial support by the German Ministry of Education and Research (BMBF), the German Ministry of Defence (BMVg) and the European Space Agency (GREAT 2 Project, Contract 21499/08/NL/PA). References [1] Quay R. Gallium nitride electronics, springer series in materials science, vol. 96; 2008. [2] Meneghesso G. Reliability of GaN high-electron-mobility transistors: state of the art and perspectives. IEEE Trans Dev Mater Reliab 2008;8:332. [3] Kohn E. Transient characteristics of GaN-based heterostructure field-effect transistors. IEEE Trans Microwave Theory Tech 2003;51(2):634. [4] Joh J, del Alamo Jose A. Critical voltage for electrical degradation of GaN highelectron mobility transistors. IEEE Electron Dev Lett 2008;29. [5] Dammann M. Reliability status of GaN transistors and MMICs in Europe. In: International reliability physics symposium, Anaheim; 2010. [6] Waltereit P. High efficiency and low leakage AlGaN/GaN HEMTs for a robust, reproducible and reliable X-band MMIC space technology. In: CS MANTECH conference, Portland; 2010. [7] Sharma B. Metal-semiconductor Schottky barrier junctions and their applications. Plenum Press; 1984. [8] del Alamo JA, Joh J. GaN HEMT reliability. Microelectron Reliab 2009;49:1200–6. [9] Karmalkar S, Mishra UK. Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate. IEEE Trans Electron Dev 2001;48:1515. [10] Bernát J. Effect of surface passivation on performance of AlGaN/GaN/Si HEMTs. Solid-State Electron 2003;47(11):2097–103. [11] Das MB. A high aspect ratio design approach to millimeter-wave HEMT structures. IEEE Trans Electron Dev 1985;ED-32:11–4.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Critical factors influencing the voltage robustness of AlGaN/GaN HEMTs M. Cäsar ⇑, M. Dammann, V. Polyakov, P. Waltereit, R. Quay, M. Mikulla, O. Ambacher Fraunhofer Institute for Applied Solid-State Physics, Tullastr. 72, D-79108 Freiburg, Germany
a r t i c l e
i n f o
Article history: Received 16 July 2010 Received in revised form 3 September 2010 Accepted 7 September 2010 Available online 13 October 2010
a b s t r a c t The influence of the electric field on the reliability of AlGaN/GaN HEMTs is investigated in this work. We first demonstrate that at a certain electric field strength at the gate edge the gate characteristics of the device changes. This degradation is irreversible and is strongly influenced by growth parameter. A drain-voltage step-stress method is applied to the devices for investigating different layouts, and a consequent application enabled us to assign parameters mitigating the peak field strength and improve reliability. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Microelectronic devices based on nitride materials offer a variety of intrinsic advantages like high breakdown voltage and high saturation velocity, which makes them ideal candidates for highfrequency and high-power applications [1]. The most commonly used nitride device realization, the AlGaN/GaN HEMT, is still facing reliability problems even after years of intensive research [2]. One major setback of these devices is a reduction of the output current under pulsed operation, the so-called current collapse [3]. Furthermore, a possible degradation of the fabricated structure, induced by the inverse piezo effect, may also limit the stability during device operation [4]. This effect potentially induces a defective region in the layer structure, resulting from an increased strain in the AlGaN-barrier. 2. Technology and experimental 2.1. Technology The AlGaN/GaN HEMTs investigated in this work have a gate length of 0.25 lm and are optimized for X-band-application. The processing is described by Dammann [5]. A schematic cross section is presented in Fig. 1. The devices consist of an AlGaN/GaN heterostructure which is grown on semi-insulating SiC substrates by MOCVD and provides excellent 2 DEG-channel densities (8 1012 cm2) and mobilities (1500 cm2/Vs). The device processing is performed by standard techniques using e-beam and optical lithography. To improve reliability, the transistor is equipped with a field plate on the drain side edge of the gate with length of lFP and the field plate has a distance to the semiconductor surface, which is ⇑ Corresponding author. Tel.: +49 761 5159 231; fax: +49 761 5159 565. E-mail address: [email protected] (M. Cäsar). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.09.006
covered with a passivation of silicon nitride, of thickness t. The integration into MMICs is done in microstrip transmission line technology with substrate thinning to 100 lm and backside processing with via holes. In standard monitorings after processing a high uniformity across a single wafer (uniformity in sheet resistance better than 3%), as well as high reproducibility from wafer to wafer is confirmed [6]. For reliability assessment in this work, 8 60 lm wide HEMTs are investigated on wafer.
2.2. Experimental 2.2.1. Characteristics of the observed degradation 2.2.1.1. Degradation monitoring and key figures. A weak point in a polar semiconductor HEMT is located in the vicinity of the drain edge of the gate, where large electric fields during voltage-robustness-test can be created. By stepwise increasing of the potential difference, i.e. drain voltage, a study of degradation phenomena can be performed when the device integrity is checked. A typical voltage-robustness-test, a HTRB-step-stress-test (High-Temperature-Reverse-Bias), is applied under pinch-off condition at high temperature, and degradation of the AlGaN/GaN HEMT can be observed. In order to study this phenomena, this step-stress-testing method (steps of DUD = 2 V every 10 min with UG = 7 V) was applied to devices fabricated at Fraunhofer on two different Epitaxys (Epi A and Epi B). The structures were grown under different conditions, leading to differences in their mechanical as well as in their electrical properties. This is apparent in 25% increased drain saturation current for Epi B, whereas the initial strain is also increased by 50% for Epi B. During the measurement, Epi A shows no indication of degradation in Fig. 2, as it exhibits a constant level of gate current throughout the whole test (until UD = 86 V), with only a slight increase of the reverse gate current. The identical test performed on Epi B however results in a sudden increase in both forward and reverse
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225
Fig. 1. Schematic layer structure of the investigated AlGaN/GaN HEMT.
Fig. 4. Schottky characteristics (at T = 150 °C) from the HTRB-step-stress-test from Fig. 2 for Epi B.
Fig. 2. Ig_off (UG = 5 V; UD = 0 V) and Ig_on (0.2 V; 0 V) in a HTRB-Test with UG = 7 V, T = 150 °C.
gate current at a critical voltage of UD = 38 V, when device degradation sets in. Similar degradation during reverse bias testing is observed by Joh and del Alamo [4]. These deviations for varied growth conditions are further apparent in the Schottky characteristics, where devices from Epi A in Fig. 3 exhibits the same behavior throughout the test, with only small changes resulting from the measurement procedure. On the contrary, characteristics from Epi B in Fig. 4 show an behav-
Fig. 3. Schottky characteristics (at T = 150 °C) from the HTRB-step-stress-test from Fig. 2 for Epi A.
Fig. 5. Schottky barrier height and ideality factor from HTRB-step-stress-test from Figs. 3 and 4.
ior around the critical voltage, where a change in carrier transport dynamic seems to be appearing. Until UD = 36 V in the test, the measurements show almost identical IV-characteristic. The characteristic after the UD = 38 V stress-step however, shows a different behavior in reverse and forward direction compared to the previous observed. From this point onwards, degradation of the Schottky contact sets in and a steady increase in gate current is observable after each voltage step. This effect can be shown more pronounced, when the evaluated Schottky parameter are inspected in Fig. 5, showing a severe degradation of the Schottky barrier height in conjunction with an ideality factor increase after the critical voltage is achieved. The increase in the Schottky current is enlarged in the lower voltage region, where the transport mechanism is normally governed by a recombination of electrons from the Schottky barrier with holes from the semiconductor in the depletion zone under the gate [7]. We therefore speculate that the elevated current is either caused by increased recombination, which would on the other hand require additional recombination centers like traps created during test [2]. Another possibility is an enhanced tunneling of the injected electrons from the gate through the AlGaN-barrier on crystallographic defects [8]. This would minimize the lifetime of the carrier in the depletion zone before the tunneling process occurs. With both interpretations, the increased ideality factor and a lower Schottky barrier height could be explained.
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Fig. 8. HTRB-Test for different gate voltages at T = 150 °C on Epi B.
Fig. 6. Schottky characteristics (at T = 50 °C) after Illumination with UV-light for a device with Epi B.
Table 1 Extracted Schottky parameters from the measurements of Figs. 6 and 7 for devices after HTRB-Test and UV-illumination or storage.
n
U (eV)
n
U (eV)
Before test
After test
After storage
1.20 1.28
1.62 0.77
1.64 0.74
Before test
After test
After UV-Illum
1.31 1.11
1.66 0.73
1.65 0.73
The devices were exposed to an HTRB-Test (until UD = 86 V) with aforementioned degradation indications, and subsequently stored for t = 150 h at T = 200 °C. As apparent in Fig. 7, the Schottky characteristic remain almost unchanged after storage. This behavior is verifying the assumption, that reverse bias testing induces a permanent degradation of the device. These findings also reduce the role of diffusion processes as a degradation driver, since no further degeneration of the device characteristic is evident, even at higher temperature during the voltage-stress time. 2.2.1.4. Verification of a voltage driven degradation. Further proof of a voltage depended degradation is given with the experiment given in Fig. 8, where a series of HTRB-Test (steps of DUD = 2 V every 1 min) with different gate voltages starting at 3 V (below PinchOff) to 7 V is applied to each time a new device. As observable in this figure, a more negative biasing of the gate leads to an early onset and a stronger degradation of the device shown by the in situ gate current. A reason for this behavior is found when the higher electric field in the vicinity of the gate due to the increased gate potential is taken into account. This enhanced electric field leads to stronger degradation as previous discussed. 2.2.2. Influence of technological parameters on field distribution Realizing the detrimental effect of electric fields higher than a certain critical value, a field plate in conjunction with the passivation layer is implemented in our device structure to adjust the field distribution. An accurate design reduces the field strength at the gate edge and increases the starting voltage when device
Fig. 7. Schottky characteristics (at T = 50 °C) after HTRB-Test and storage at 200 °C for 150 h on Epi B.
2.2.1.2. Recoverability of degradation. In order to study the recoverability within this degradation scheme, the device was exposed to an HTRB-Test as described above (until UD = 86 V). The device showed the same degradation indications as previous observed and the gate characteristics are presented in Fig. 6. Afterwards the devices were exposed to UV-light (kmin 305 nm, 4 eV) for 30 min and characterized again, which is also presented in Fig. 6. As observable, an illumination of the device is not changing the Schottky characteristics of the device. This fact of non-recoverability is also noticeable in the extracted Schottky parameter in Table 1. 2.2.1.3. Stability of degradation. Additionally the long term stability of the induced degradation at elevated temperature was studied.
Fig. 9. Density of interface states of special grown MIS-structures for passivations with different refractive index.
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degradation occurs [9]. We applied our step-stress-testing method presented in the previous section and evaluated different layouts and parameters. From this measurements we can conclude, that an increase of the length of the field plate, a higher dielectric constant of the passivation as well as a decrease of the thickness of the passivation layer have a positive effect on degradation behavior. 2.2.2.1. Dielectric constant. While evaluating different passivation methods, a significant impact of the composition of the passivations on the device characteristic was observed. One possible explanation is demonstrated in Fig. 9, where different densities of interface states on special fabricated MIS-structures on GaN for different passivations (characterized by their refracting index) are presented. A higher density of interface states is supposed to be responsible for reduced device performance [10]. In order to only account for the intrinsic effects of different passivations, an experimental verification was withdrawn and the impact of different passivation methods on the field distribution was calculated using the commercial software package ATLAS SILVACO. The outcome is illustrated in Fig. 10, where a reduced electric field at the gate edge is apparent for the device possessing a passivation layer with the higher dielectric constant. This fact can be explained, when an enhanced drop of the potential in the region under the field plate and the passivation is considered, leading to smaller field strength at the gate edge, as indicated in Fig. 10. 2.2.2.2. Passivation layer thickness. The influence of the thickness of the passivation on the degradation behavior was investigated with an HTRB-step-stress-test with a different nitride. The in situ gate current for a thickness t1 and a thickness t2 = 2 t1 are compared in Fig. 11. In the case of t1 thickness, no degradation is apparent, with very low gate currents (Ig < 300 nA/mm) throughout the test. For the device with thickness t2 an increase of the gate current occurs after t = 300 min of stress time, when device degradation sets in and a steady increase of the current is observed. This observation is also seen when the gate characteristics of the two transistors before and after the test are considered in Fig. 12. Here, the device with thickness t2 is showing a noticeable increase in reverse and forward gate current, whereas the device with thinner passivation t1 shows no signs of degradation. Extractions of the Schottky parameters, which are presented in Table 2, reveal the same indication with the aforementioned degradation signs.
Fig. 10. Simulation of the modulus of the electric field for passivation with different dielectric constants under constant voltage operation.
Fig. 11. Gate currents during step-stress-testing (UG = 7 V, T = 150 °C, DUD = 5 V/ 60 min, UD_start = 30 V) with different nitride thicknesses t2 = 2 t1 and lFP2.
Fig. 12. Gate characteristics of devices before and after the test with different passivation thicknesses as shown in Fig. 11.
Table 2 Extracted Schottky parameters from the measurements of Fig. 12 with different nitrite thicknesses. Device/thickness
Value
Before
After
t1 t2 t1 t2
U (eV) U (eV)
1.10 1.04 1.61 1.75
1.10 0.87 1.60 2.30
n n
2.2.2.3. Field plate length. Another factor influencing the voltage robustness was identified, when the dependence of the field plate length on the drain side of the gate was investigated with an HTRBTest. Devices with a length of lFP1, lFP2 > lFP1 and lFP3 > lFP2 of the field plate were fabricated and exposed to the same test as described before. The results are shown in Fig. 13, where one can observe a significantly reduced gate current for longer field plates. In Fig. 14, the corresponding gate characteristics of the devices before and after the test are presented, showing a reduced degradation for longer field plates. This observation is in line with the measured higher gate current during the test. Furthermore, the extracted Schottky parameters in Table 3 exhibits the same degradation indications as observed in previous sections with a decrease of the barrier height and an increase of the ideality factor.
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effect is more pronounced on the maximum oscillating frequency than on the transition frequency [11]
fT;i ; fmax ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Rs þRg 2:5C GD 1 þ R Þ 4 ggds g m Rgs þ Rs þ1=g þ 45 CCGD ð1 þ g s gm C GS GS m
Fig. 13. Gate currents of devices during step-stress-testing (UG = 7 V, T = 150 °C, DUD = 5 V/60 min, UD_start = 30 V) with different field plate length and nitride thickness t2.
m
which can be deduced from the equation, since an unpleasant ratio of the gate-drain capacitance (CGD) compared to the gate source capacitance (CGS) is achieved, resulting in a strong reduction of the fmax. We investigated the effect of this change in the capacitances on the rf-characteristics with the devices from the HTRB-Test observable in Fig. 13. The increased field plate length for lFP2 implies a reduction of the maximum available gain of 1 db gain compared to the device with lFP1, and the fmax changes from 40 GHz to 37.2 GHz. The extracted Gate–Drain capacitance increases from 102 fF/mm for lFP1 to 122 fF/mm for lFP2. Extension of the field plate to lFP3 instead of the length lFP2 diminishes the rf-performance by another 1 dB in the maximum available gain, the fmax decreases to 34 GHz and CGD increases to 144 fF/mm. 3. Summary and conclusion The results from this work indicate that the electric field strength at the gate edge beyond a certain point harms the device. This degradation is permanent and cannot be recovered, and is strongly depended on epitaxial growth parameter. During technology evaluation to mitigate the peak electric field strength, it was found that the passivation thickness, the permittivity of the passivation layer and the field plate extent have a positive influence on the reliability behavior, which on the other side reduce the rf-performance. When comparing the effect of investigated parameter during growth and processing of AlGaN/GaN HEMTs in the framework of this study, a trade-off between power and stability during operation of this technology is suggested. Acknowledgements
Fig. 14. Gate characteristics of devices before and after the test with different field plate length as shown in Fig. 13.
Table 3 Extracted Schottky parameters from the measurements of Fig. 14 with different field plate length. lFP1
n
U (eV)
lFP2
lFP3
Before
After
Before
After
Before
After
2.16 0.93
6.55 0.38
1.93 1.01
3.76 0.53
2.13 0.96
2.13 0.96
2.2.3. Influence of the critical factors on rf-performance The technological parameters investigated in the previous paragraphs, which improve the voltage robustness of the device, change on the other side the rf-performance during device operation. For instance, the extension of the field plate as seen in Fig. 7 results in an enlargement of the gate capacitance (CG), which influences as a consequence the transition frequency.
fT ¼
gm : 2pC G
The increase of the field plate on the drain edge side has in addition a more severe impact on the gate-drain capacitance CGD. This
The authors acknowledge financial support by the German Ministry of Education and Research (BMBF), the German Ministry of Defence (BMVg) and the European Space Agency (GREAT 2 Project, Contract 21499/08/NL/PA). References [1] Quay R. Gallium nitride electronics, springer series in materials science, vol. 96; 2008. [2] Meneghesso G. Reliability of GaN high-electron-mobility transistors: state of the art and perspectives. IEEE Trans Dev Mater Reliab 2008;8:332. [3] Kohn E. Transient characteristics of GaN-based heterostructure field-effect transistors. IEEE Trans Microwave Theory Tech 2003;51(2):634. [4] Joh J, del Alamo Jose A. Critical voltage for electrical degradation of GaN highelectron mobility transistors. IEEE Electron Dev Lett 2008;29. [5] Dammann M. Reliability status of GaN transistors and MMICs in Europe. In: International reliability physics symposium, Anaheim; 2010. [6] Waltereit P. High efficiency and low leakage AlGaN/GaN HEMTs for a robust, reproducible and reliable X-band MMIC space technology. In: CS MANTECH conference, Portland; 2010. [7] Sharma B. Metal-semiconductor Schottky barrier junctions and their applications. Plenum Press; 1984. [8] del Alamo JA, Joh J. GaN HEMT reliability. Microelectron Reliab 2009;49:1200–6. [9] Karmalkar S, Mishra UK. Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate. IEEE Trans Electron Dev 2001;48:1515. [10] Bernát J. Effect of surface passivation on performance of AlGaN/GaN/Si HEMTs. Solid-State Electron 2003;47(11):2097–103. [11] Das MB. A high aspect ratio design approach to millimeter-wave HEMT structures. IEEE Trans Electron Dev 1985;ED-32:11–4.