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Operational frequency degradation induced trapping in scaled GaN HEMTs
MR-12289; No of Pages 6 Microelectronics Reliability xxx (2017) xxx–xxx
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Operational frequency degradation induced trapping in scaled GaN HEMTs Brendan Ubochi ⁎, Soroush Faramehr, Khaled Ahmeda, Petar Igić, Karol Kalna Electronic Systems Design Centre (ESDC), College of Engineering, Swansea University, Bay Campus, Fabian Way, Swansea, SA1 8EN, Wales, United Kingdom
a r t i c l e
i n f o
Article history: Received 25 August 2016 Received in revised form 3 January 2017 Accepted 13 February 2017 Available online xxxx Keywords: GaN HEMTs Traps Degradation Radio frequency Device modelling
a b s t r a c t Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to LG = 0.5 μm, LG = 0.25 μm and LG = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (ID-VGS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of ET =EV + 0.9 eV (carbon) with concentrations of NIT =5 ×1016cm−3, NIT =5× 1017cm−3 and NIT = 5 × 1018cm−3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm. © 2017 Published by Elsevier Ltd.
1. Introduction A huge potential of gallium nitride (GaN) high electron mobility transistors (HEMTs) in future radio frequency (RF) and power applications has been fuelling their research and development in the recent years. Material properties of wide-band-gap nitrides such as spontaneous (SP) and piezoelectric (PZ) polarizations allow creation of a twodimensional electron gas (2DEG) with sheet densities above 1012 cm−2, a high electron mobility (up to 2000 cm2V−1s−1 in 2DEG), a large energy band gap (3.4 eV), a good thermal conductivity (160 WK− 1m−1) ensuring a good heat dissipation, and a very high breakdown field (3.3 MV cm−1) make it an ideal candidate for all devices requiring fast carrier transport with high breakdown voltage [1, 2]. However, the maximum RF power output is not always reproducible due to the existence of defects/traps in the GaN device structure inhibiting the wide commercial use of these devices. The trap related phenomena, affecting the reliability of device, may result in a reduction of the drain current, virtual gate formation, transconductance frequency dispersion [3], light sensitivity [4] and restricted microwave output power [5]. These effects are largely due to the formation of a nonequilibrium charge distribution in the device. Various proposals have been made regarding the nature, location, and effects of traps in GaN devices [6] such as a correlation between RF output power degradation and bulk traps [7], and a high electrical stress induced traps [6] opposing the traditional explanation by a self-heating [8].
⁎ Corresponding author. E-mail address: [email protected] (B. Ubochi).
Since experimental techniques are insufficient to provide a detailed understanding of carrier transport process in GaN based devices, physically-based simulations are required to uncover complex transport phenomena [9]. Since the GaN HEMTs for power and RF applications have typically microscale (power/RF) or sub-microscale dimensions (RF), drift-diffusion and hydrodynamics transport models [1] are suitable for fast turn-out modelling while ensemble Monte Carlo simulations are used for in-depth modelling into details of hotcarrier non-equilibrium transport [10]. A compromise is a combination of the Fermi kinetic transport model with Maxwell equations to efficiently capture the essential physics of hot-carriers to model the electromagnetic wave effects in the HEMTs [11]. This paper studies the effects of electric field induced bulk traps on the DC and RF characteristics of GaN HEMTs. The investigations are carried out using Atlas simulation toolbox by Silvaco [12] using the driftdiffusion transport model for all simulations. The study is based on careful calibration of device I-V characteristics using a well-developed methodology [1]. The RF parameters are calculated from the small signal conductance and capacitance values during small signal analysis. The admittance parameters (Y) are obtained directly from the small signal parameters and then converted to scattering parameters (S) using matrix transformation [12]. Experimentally reported values for the cut-off frequency for GaN HEMTs have a fT × LG product of 13 GHz μm [13], although this can be improved by increasing the gate recess depth [14] and has been shown to depend on the substrate material [15]. We will show that results from our simulations are in a good agreement with the experimentally reported ones [16,17]. We give an in-sight, firstly, on the variation of drain current and cut-off frequency with scaling down the device.
http://dx.doi.org/10.1016/j.microrel.2017.02.008 0026-2714/© 2017 Published by Elsevier Ltd.
Please cite this article as: B. Ubochi, et al., Operational frequency degradation induced trapping in scaled GaN HEMTs, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.008
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Fig. 1. Schematic of the hetero-structure of the investigated 1 μm gate length GaN HEMT.
Thereafter, traps are placed in the device according to Ref. [6] in order to predict their effect on the DC and RF performance of the device. The induced traps are predicted to cause a positive shift in the threshold voltage and a general reduction in the cut-off frequency. 2. Device structure and simulation methodology Fig. 1 illustrates the schematic cross-section of an investigated asymmetrical 1 μm gate length GaN HEMT. It consists of a 2 nm GaN cap, 20 nm AlGaN barrier, 1 nm AlN spacer, and 3 μm GaN buffer, all grown on a SiC substrate with source-to-gate and gate-to-drain separations of LSG = 2 μm and LGD = 3 μm, respectively. Fig. 2 shows the conduction band profile overlapped with electron current density showing the role of the thin aluminium nitride (AlN) layer in additional confinement of the 2DEG. The simulations have been calibrated against experimentally measured transfer characteristics (ID-VGS). In the calibration, we have used donor interface traps located at the surface of GaN cap with an energy, concentration and electron and hole capture cross-sections of ET = EV + 2.9 eV [18], ND = 4.2 × 1019 cm−3 and σn , p = 1 × 10−19 cm2, respectively, in order to pin the Fermi level at the surface. The value of
Fig. 3. Transfer characteristics (ID-VGS) at VDS = 1 V to VDS = 5 V in a step of 1 V comparing calibrated simulations (full lines) to experimental measurements (dot lines).
the electron capture cross-section has been used to model the onset of drain current. In order to control a leakage current through the buffer and thus to better confine electrons into the channel, acceptor traps are located in the GaN buffer with an energy, concentration and electron and hole capture cross-sections of ET = EC − 2.2 eV [19], NA = 3.9 × 1016 cm−3 and σn , p = 1 × 10−15 cm2 [19], respectively. The free carrier distribution is modeled using the Boltzmann statistics. The device is uniformly n-type doped with a concentration of 1 × 1016 cm−3. In order to model carrier velocity variation with field strength, we have used the parallel field dependent mobility model [20] which can be expressed as 2 μ n;p ðEÞ ¼ μ n;p0 41 þ
μ n;p0 E V n;p SAT
!β 3−β1 5
ð1Þ
where VnSAT and VpSAT are the saturation velocities for electrons and holes, μn0 and μp0 are the electron and hole low field mobility and β is a power coefficient to describe a strength of current saturation. The modeled and experimental transfer characteristics are shown in Fig. 3 using parameters of Table 1. The small signal current gain, h21, expressed in terms of the scattering parameters, S, is given by [21]: h21 ¼
−2S21 ð1−S11 Þð1 þ S22 Þ þ ðS12 S21 Þ
ð2Þ
Finally, the current gain is plotted as a function of frequency from where the cut-off frequency is extracted by extrapolation. 3. Lateral and vertical scaling of the device The maximum drain current for the investigated 1 μm gate length GaN HEMT is IDmax = 516.7 mA/mm (see Fig. 3) while the extracted cut-off frequency is f = 12.1 GHz which closely agrees with the
Table 1 Material parameters used in simulations.
Fig. 2. Conduction band (CB) energy (blue full circles) overlapped with electron current density (red line) at the drain side of the gate at VGS = 0 V and VDS = 5 V. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
Material properties
GaN
AlN
Electron saturation velocity Electron mobility Hole mobility β
1 × 107 cm s−1 1070 cm2 V−1s−1 30 cm2 V−1s−1 2
1.4 × 107 cm s−1 150 cm2 V−1s−1 14 cm2 V−1s−1 2
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Fig. 4. Simulated transfer characteristics (ID-VGS) at VDS = 5 V using a lateral scaling only for four devices.
Fig. 5. Simulated transfer characteristics (ID-VGS) at VDS = 5 V of the 1 μm gate length device using a vertical scaling of the gate-to-channel distance (GC) only.
experimental results of 11.5 GHz (1 μm gate length Al0.22Ga0.78N/GaN HEMT on sapphire) reported in Ref. [17]. We have then scaled down the gate length from LG = 1 μm to LG = 0.5 μm, LG = 0.25 μm, LG = 0.125 μm and, correspondingly, the source-to-gate and gate-to-drain distances in order to predict possible improvements in the RF performance of the scaled device. We have labelled the four devices as A, B, C, and D corresponding to the gate lengths, respectively. Fig. 4 shows the transfer characteristics (ID-VGS) at VDS = 5 V for the laterally only scaled down devices. Results from Table 2 indicate that in addition to the progressive increase in the maximum drain current, the cut-off frequency of the 1 μm gate-length HEMT can be increased nearly 7.5 times (91.4 GHz) when the gate is scaled down proportionally in lateral dimensions from 1 μm to 0.125 μm. The cut-off frequency for the 1 μm, 0.5 μm, and 0.25 μm gate lengths is in agreement with the reported values of 15 GHz, 33 GHz and 53 GHz in Ref. [22] for the corresponding gate lengths. The effect of vertical scaling is investigated by reducing the gate-tochannel separation (LGC) as the gate length is scaled down. Here, corresponding to devices A, E, and F, the gate-to-channel separations for LG = 1 μm, LG = 0.5 μm, and LG = 0.25 μm are LGC = 33 nm, LGC = 17 nm, and LGC = 8.25 nm, respectively. Note that a constant aspect ratio of 30.3 is maintained in all three devices. While the cut-off frequency has increased from fT = 12.1 GHz (LG = 1 μm) to fT = 22.6 GHz (LG = 0.5 μm) and to fT = 43 GHz (LG = 0.25 μm), the maximum drain current has reduced from 516.7 mA/mm to 325 mA/mm and to 320 mA/mm, respectively. This reduction in drain current can be associated with the reduction in the ionized surface donors which scales proportionally with the AlGaN barrier thickness above a certain critical thickness [23]. We further investigate this reduction in the drain current by using a fixed gate length of 1 μm with increasing aspect ratios of 25% and 50% corresponding to the gate-to-channel separations of LGC = 26 nm and LGC = 22 nm, respectively. In reducing the gate-to-channel separation, we have reduced only the thickness of the AlGaN barrier. Fig. 5 illustrates that the drain current degrades as the thickness of the barrier layer is reduced. Notice that the respective scaling of the gate-to-channel distance will result in
a better control of the channel transport [24] but would lead, at the same time, to the decrease in the channel 2DEG. This reduction in the 2DEG density will result in a slight decrease in the cut-off frequency by 0.82% and 3.72% for a 25% and 50% increase in the aspect ratio and in a decrease of the on-current by 3.1% and 3.5%, respectively. 4. Trapping effects on DC and RF performance Although degradation mechanisms in GaN HEMTs have yet to be fully understood, a number of explanations have been advanced as possible mechanisms leading to degradation in these devices. Some of these include: (i) virtual gate formation as a result of tunnelling from the gate [25]; (ii) Poole-Frenkel gate leakage surface conduction [26]; (iii) hot electron trapping and interface state creation [27]; (iv) hot electron trapping at the surface and AlGaN barrier [28,29]; (v) trap generation in the drain access region by hot electron damage, (vi) and electric field induced strain enhancement and relaxation [6]. A virtual gate formation is observed when the device is biased in off-state with a high negative gate-to-source voltage whereas the hot electron trapping occurs for the device biased in the on-state. It has been shown that degradation in the transconductance due to a high on-state stress is far more greater than that due to an off-state stress [27]. We assume that the trap generation in the drain access region provides a more plausible picture of the high electric field induced degradation. We also assume that traps could be generated at the vicinity of the gate due to the high electric fields, in addition to the ones that may be created at the surface due to process damage [30]. Substitutional carbon in GaN, CN, acting as acceptors is often unavoidably present during material growth. The unintentionally doped carbon concentration has been experimentally shown to reduce from 4 × 1017 cm−3 to 5 × 1016 cm−3 when the growth pressure is increased from 65 to 500 Torr [31]. We use the knowledge of these acceptor traps to simulate the effects of traps generation by assuming that these deep traps are created due to an applied electric field. Our results, expectedly, should be seen as a typical indication of the electric field induced trapping effects. We thus have located traps at an energy ET = EV + 0.9 eV [32], laterally from
Table 2 Extracted maximum drain current and cut-off frequency from the four scaled devices A–D. The devices E and F have additionally scaled down the gate-to-channel separation as indicated. Predicted values
Device A (LG = 1 μm, LGC = 33 nm)
Device B (LG = 0.5 μm)
Device C (LG = 0.25 μm)
Device D (LG = 0.125 μm)
Device E (LG = 0.5 μm, LGC = 17 nm)
Device F (LG = 0.25 μm, LGC = 8.25 nm)
IDmax (mA/mm) fT (GHz)
516.7 12.1
693 26.4
837.5 52.1
949 91.4
325 22.6
319.9 43
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L = −0.1 μm to L = 2.4 μm where the gate edge is set to be at zero (see Fig. 6). No significant change in the peak of the transconductance has been observed when this region is extended to the drain [6]. We show, however, in Fig. 7 that extending this traps generation region increasingly below the gate leads to a positive shift in the threshold voltage. This is consistent with observations in Ref. [29] which reports that donor-like traps are generated under on-state stress. These donor-like traps are spatially located underneath the gate and lead to a negative threshold voltage shift. Similarly, with increasing acceptor trap densities for traps extending to L = −0.1 μm from the gate edge (beneath the gate), a small positive increase in the threshold voltage is observed as shown in Fig. 8. More importantly, the decrease in the slope of these characteristics, which translates to decreasing transconductance, leads to a reduction in the cut-off frequency with increasing trap densities. Compared to the device without acceptor traps whose cut-off frequency is fT = 12.1 GHz, a reduction in the extracted cut-off frequencies by 7.7% and 17.6% for acceptor traps densities of NIT = 5 × 1017 cm−3 and NIT = 1 × 1018 cm−3, respectively, is observed. The large trapping density of 1 × 1018 cm−3 leads also to a significant shift of threshold voltage by about 0.6 V. If the trap density does not exceed NIT = 1 × 1017 cm−3, the cut-off frequency is not affected as can be seen from nearly overlapping ID–VGS characteristics in Fig. 8. In Fig. 9, we compare the effects of electric field generated traps densities of 5 × 1016 cm−3, 5 × 1017 cm−3 and 5 × 1018 cm−3 respectively. The drain current becomes extremely small as it is strongly suppressed by carriers captured by acceptor traps if the generated trap density is 5 × 1018 cm−3 as shown in Fig. 9. On the other hand, Fig. 9 also shows that the drain current changes insignificantly in the characteristic when the acceptor traps density is assumed to be 5 × 1016 cm−3. Note here that the acceptor traps density can reach 1012 cm−2 (equivalent to 1019 cm−3) as shown in Ref. [6] to reproduce experimental observations in GaN HEMTs. 5. Trapping effects on a laterally scaled device In order to gain some insight into how device behaviour in a laterally scaled device is affected by the traps, we have scaled down the traps generation region in proportion to the various device dimensions. Assuming a relatively small value of the trap density up to 1017 cm−3 for smaller device dimensions may not, in reality, represent accurately the effects of traps as smaller devices would experience higher electric fields under similar biases. We observe in Fig. 9 that the current is seemingly unaffected due to small kinetic energy of electrons insufficient to trap them into a trap energy level (ET = EV + 0.9 eV) at a relatively
Fig. 6. Scheme of simulated acceptor traps distribution in the 1 μm gate length GaN HEMT.
Fig. 7. Simulated transfer characteristics (ID-VGS) at a fixed VDS assuming increasing an indicated lateral location of acceptor traps generated underneath the gate on the drain side (see Fig. 6).
small VGS. All scaled devices show an increasing decline of the oncurrent when the trap density is NIT = 5 × 1017 cm−3 and even further, there is no current for a trap density of NIT = 5 × 1018 cm−3 as shown. However, there is a distinguishable negative threshold voltage shift of −0.7 V for the 0.125 μm gate length device even the 0.25 μm gate length device exhibits a small shift of about −0.2 V as well. As the device dimension is reduced, due to the high lateral fields, the carriers have higher kinetic energies and are expected to travel at higher velocities thereby increasing the probability of carrier capture. Fig. 10 shows a relationship between the inverse cut-off frequency, fT, and the gate length. Similar to our previous observations, the effect of acceptor traps having a fixed density of NIT = 5 × 1017 cm−3 on the cut-off frequency is predicted to reduce as the dimensions of the device is scaled down. This diminishing effect of traps during the GaN HEMT scaling occurs despite a reduction of the saturation current of 17.6% for the 1 μm gate length transistor to 20.4% for the smallest 0.125 μm gate length one. 6. Conclusions The detrimental effect of traps generated by a high electric field in the stressed GaN HEMTs has been studied in scaled devices. The study is based on accurate calibration of the TCAD model to experimental transfer and output characteristics of 1 μm gate length GaN HEMT
Fig. 8. Simulated transfer characteristics (ID-VGS) at VDS = 5 V of the HEMT for indicated acceptor trap density.
Please cite this article as: B. Ubochi, et al., Operational frequency degradation induced trapping in scaled GaN HEMTs, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.008
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to 0.125 μm. When the traps density exceeds 5 × 1018 cm−3, the device current becomes diminished with a complete collapse of fT. Acknowledgements This research is funded by the Sêr Cymru National Research Network in Advanced Engineering and Materials [Grant code: NRN081]. We thank Edward Wasige and Abdullah Al-Khalidi of the University of Glasgow for providing us with the experimental data. References
Fig. 9. Simulated transfer characteristics (ID-VGS) at VDS = 5 V of the 1 μm gate length device for the lateral scaling only comparing devices with no traps and with acceptor trap densities of 5 × 1016 cm−3, 5 × 1017 cm−3 and 5 × 1018 cm−3, respectively.
with fT = 12.1 GHz obtained using commercial simulation software Atlas by Silvaco. The scaled device exhibits improvement in the RF performance by increase in the cut-off frequency (fT = 12.1 GHz) by 118% (fT = 26.4 GHz), 330% (fT = 52.1 GHz) to 655% (fT = 91.4 GHz), when the gate is scaled down proportionally in lateral dimensions from 1 μm to 0.5 μm, 0.25 μm and 0.125 μm respectively. We have also found that the vertical scaling aiming to increase the gate control [24] or to make the device normally-off [33] will reduce the current density with an attendant negative effect on both DC and RF power performance. We have seen that the high electric field induced trapping leads to a positive threshold voltage shift for traps increasingly located under the gate, and to an increase in the on-resistance for traps located in the drain access region. We have also reported that, at low VGS, the current is seemingly unaffected due to small kinetic energy of electrons making the carrier trapping negligible. For shorter gate lengths, the linear part of the transfer characteristic and, hence, the maximum transconductance are apparently unaffected by traps despite a reduction of the saturation current by 17.6% in the 1 μm gate length transistor to about 20.4% for the smallest 0.125 μm gate length one. Finally, the effect of traps on fT, assuming a traps density of 5 × 1017 cm−3, for a laterally scaled device is consequently reduced during the scaling of gate length from 1 μm
Fig. 10. Simulated 1/fT versus gate length (LG) at VDS = 5 V for laterally scaled devices without traps and with acceptor trap density of 5 × 1016 cm−3 and 5 × 1017 cm−3.
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Operational frequency degradation induced trapping in scaled GaN HEMTs Brendan Ubochi ⁎, Soroush Faramehr, Khaled Ahmeda, Petar Igić, Karol Kalna Electronic Systems Design Centre (ESDC), College of Engineering, Swansea University, Bay Campus, Fabian Way, Swansea, SA1 8EN, Wales, United Kingdom
a r t i c l e
i n f o
Article history: Received 25 August 2016 Received in revised form 3 January 2017 Accepted 13 February 2017 Available online xxxx Keywords: GaN HEMTs Traps Degradation Radio frequency Device modelling
a b s t r a c t Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to LG = 0.5 μm, LG = 0.25 μm and LG = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (ID-VGS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of ET =EV + 0.9 eV (carbon) with concentrations of NIT =5 ×1016cm−3, NIT =5× 1017cm−3 and NIT = 5 × 1018cm−3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm. © 2017 Published by Elsevier Ltd.
1. Introduction A huge potential of gallium nitride (GaN) high electron mobility transistors (HEMTs) in future radio frequency (RF) and power applications has been fuelling their research and development in the recent years. Material properties of wide-band-gap nitrides such as spontaneous (SP) and piezoelectric (PZ) polarizations allow creation of a twodimensional electron gas (2DEG) with sheet densities above 1012 cm−2, a high electron mobility (up to 2000 cm2V−1s−1 in 2DEG), a large energy band gap (3.4 eV), a good thermal conductivity (160 WK− 1m−1) ensuring a good heat dissipation, and a very high breakdown field (3.3 MV cm−1) make it an ideal candidate for all devices requiring fast carrier transport with high breakdown voltage [1, 2]. However, the maximum RF power output is not always reproducible due to the existence of defects/traps in the GaN device structure inhibiting the wide commercial use of these devices. The trap related phenomena, affecting the reliability of device, may result in a reduction of the drain current, virtual gate formation, transconductance frequency dispersion [3], light sensitivity [4] and restricted microwave output power [5]. These effects are largely due to the formation of a nonequilibrium charge distribution in the device. Various proposals have been made regarding the nature, location, and effects of traps in GaN devices [6] such as a correlation between RF output power degradation and bulk traps [7], and a high electrical stress induced traps [6] opposing the traditional explanation by a self-heating [8].
⁎ Corresponding author. E-mail address: [email protected] (B. Ubochi).
Since experimental techniques are insufficient to provide a detailed understanding of carrier transport process in GaN based devices, physically-based simulations are required to uncover complex transport phenomena [9]. Since the GaN HEMTs for power and RF applications have typically microscale (power/RF) or sub-microscale dimensions (RF), drift-diffusion and hydrodynamics transport models [1] are suitable for fast turn-out modelling while ensemble Monte Carlo simulations are used for in-depth modelling into details of hotcarrier non-equilibrium transport [10]. A compromise is a combination of the Fermi kinetic transport model with Maxwell equations to efficiently capture the essential physics of hot-carriers to model the electromagnetic wave effects in the HEMTs [11]. This paper studies the effects of electric field induced bulk traps on the DC and RF characteristics of GaN HEMTs. The investigations are carried out using Atlas simulation toolbox by Silvaco [12] using the driftdiffusion transport model for all simulations. The study is based on careful calibration of device I-V characteristics using a well-developed methodology [1]. The RF parameters are calculated from the small signal conductance and capacitance values during small signal analysis. The admittance parameters (Y) are obtained directly from the small signal parameters and then converted to scattering parameters (S) using matrix transformation [12]. Experimentally reported values for the cut-off frequency for GaN HEMTs have a fT × LG product of 13 GHz μm [13], although this can be improved by increasing the gate recess depth [14] and has been shown to depend on the substrate material [15]. We will show that results from our simulations are in a good agreement with the experimentally reported ones [16,17]. We give an in-sight, firstly, on the variation of drain current and cut-off frequency with scaling down the device.
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Fig. 1. Schematic of the hetero-structure of the investigated 1 μm gate length GaN HEMT.
Thereafter, traps are placed in the device according to Ref. [6] in order to predict their effect on the DC and RF performance of the device. The induced traps are predicted to cause a positive shift in the threshold voltage and a general reduction in the cut-off frequency. 2. Device structure and simulation methodology Fig. 1 illustrates the schematic cross-section of an investigated asymmetrical 1 μm gate length GaN HEMT. It consists of a 2 nm GaN cap, 20 nm AlGaN barrier, 1 nm AlN spacer, and 3 μm GaN buffer, all grown on a SiC substrate with source-to-gate and gate-to-drain separations of LSG = 2 μm and LGD = 3 μm, respectively. Fig. 2 shows the conduction band profile overlapped with electron current density showing the role of the thin aluminium nitride (AlN) layer in additional confinement of the 2DEG. The simulations have been calibrated against experimentally measured transfer characteristics (ID-VGS). In the calibration, we have used donor interface traps located at the surface of GaN cap with an energy, concentration and electron and hole capture cross-sections of ET = EV + 2.9 eV [18], ND = 4.2 × 1019 cm−3 and σn , p = 1 × 10−19 cm2, respectively, in order to pin the Fermi level at the surface. The value of
Fig. 3. Transfer characteristics (ID-VGS) at VDS = 1 V to VDS = 5 V in a step of 1 V comparing calibrated simulations (full lines) to experimental measurements (dot lines).
the electron capture cross-section has been used to model the onset of drain current. In order to control a leakage current through the buffer and thus to better confine electrons into the channel, acceptor traps are located in the GaN buffer with an energy, concentration and electron and hole capture cross-sections of ET = EC − 2.2 eV [19], NA = 3.9 × 1016 cm−3 and σn , p = 1 × 10−15 cm2 [19], respectively. The free carrier distribution is modeled using the Boltzmann statistics. The device is uniformly n-type doped with a concentration of 1 × 1016 cm−3. In order to model carrier velocity variation with field strength, we have used the parallel field dependent mobility model [20] which can be expressed as 2 μ n;p ðEÞ ¼ μ n;p0 41 þ
μ n;p0 E V n;p SAT
!β 3−β1 5
ð1Þ
where VnSAT and VpSAT are the saturation velocities for electrons and holes, μn0 and μp0 are the electron and hole low field mobility and β is a power coefficient to describe a strength of current saturation. The modeled and experimental transfer characteristics are shown in Fig. 3 using parameters of Table 1. The small signal current gain, h21, expressed in terms of the scattering parameters, S, is given by [21]: h21 ¼
−2S21 ð1−S11 Þð1 þ S22 Þ þ ðS12 S21 Þ
ð2Þ
Finally, the current gain is plotted as a function of frequency from where the cut-off frequency is extracted by extrapolation. 3. Lateral and vertical scaling of the device The maximum drain current for the investigated 1 μm gate length GaN HEMT is IDmax = 516.7 mA/mm (see Fig. 3) while the extracted cut-off frequency is f = 12.1 GHz which closely agrees with the
Table 1 Material parameters used in simulations.
Fig. 2. Conduction band (CB) energy (blue full circles) overlapped with electron current density (red line) at the drain side of the gate at VGS = 0 V and VDS = 5 V. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
Material properties
GaN
AlN
Electron saturation velocity Electron mobility Hole mobility β
1 × 107 cm s−1 1070 cm2 V−1s−1 30 cm2 V−1s−1 2
1.4 × 107 cm s−1 150 cm2 V−1s−1 14 cm2 V−1s−1 2
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Fig. 4. Simulated transfer characteristics (ID-VGS) at VDS = 5 V using a lateral scaling only for four devices.
Fig. 5. Simulated transfer characteristics (ID-VGS) at VDS = 5 V of the 1 μm gate length device using a vertical scaling of the gate-to-channel distance (GC) only.
experimental results of 11.5 GHz (1 μm gate length Al0.22Ga0.78N/GaN HEMT on sapphire) reported in Ref. [17]. We have then scaled down the gate length from LG = 1 μm to LG = 0.5 μm, LG = 0.25 μm, LG = 0.125 μm and, correspondingly, the source-to-gate and gate-to-drain distances in order to predict possible improvements in the RF performance of the scaled device. We have labelled the four devices as A, B, C, and D corresponding to the gate lengths, respectively. Fig. 4 shows the transfer characteristics (ID-VGS) at VDS = 5 V for the laterally only scaled down devices. Results from Table 2 indicate that in addition to the progressive increase in the maximum drain current, the cut-off frequency of the 1 μm gate-length HEMT can be increased nearly 7.5 times (91.4 GHz) when the gate is scaled down proportionally in lateral dimensions from 1 μm to 0.125 μm. The cut-off frequency for the 1 μm, 0.5 μm, and 0.25 μm gate lengths is in agreement with the reported values of 15 GHz, 33 GHz and 53 GHz in Ref. [22] for the corresponding gate lengths. The effect of vertical scaling is investigated by reducing the gate-tochannel separation (LGC) as the gate length is scaled down. Here, corresponding to devices A, E, and F, the gate-to-channel separations for LG = 1 μm, LG = 0.5 μm, and LG = 0.25 μm are LGC = 33 nm, LGC = 17 nm, and LGC = 8.25 nm, respectively. Note that a constant aspect ratio of 30.3 is maintained in all three devices. While the cut-off frequency has increased from fT = 12.1 GHz (LG = 1 μm) to fT = 22.6 GHz (LG = 0.5 μm) and to fT = 43 GHz (LG = 0.25 μm), the maximum drain current has reduced from 516.7 mA/mm to 325 mA/mm and to 320 mA/mm, respectively. This reduction in drain current can be associated with the reduction in the ionized surface donors which scales proportionally with the AlGaN barrier thickness above a certain critical thickness [23]. We further investigate this reduction in the drain current by using a fixed gate length of 1 μm with increasing aspect ratios of 25% and 50% corresponding to the gate-to-channel separations of LGC = 26 nm and LGC = 22 nm, respectively. In reducing the gate-to-channel separation, we have reduced only the thickness of the AlGaN barrier. Fig. 5 illustrates that the drain current degrades as the thickness of the barrier layer is reduced. Notice that the respective scaling of the gate-to-channel distance will result in
a better control of the channel transport [24] but would lead, at the same time, to the decrease in the channel 2DEG. This reduction in the 2DEG density will result in a slight decrease in the cut-off frequency by 0.82% and 3.72% for a 25% and 50% increase in the aspect ratio and in a decrease of the on-current by 3.1% and 3.5%, respectively. 4. Trapping effects on DC and RF performance Although degradation mechanisms in GaN HEMTs have yet to be fully understood, a number of explanations have been advanced as possible mechanisms leading to degradation in these devices. Some of these include: (i) virtual gate formation as a result of tunnelling from the gate [25]; (ii) Poole-Frenkel gate leakage surface conduction [26]; (iii) hot electron trapping and interface state creation [27]; (iv) hot electron trapping at the surface and AlGaN barrier [28,29]; (v) trap generation in the drain access region by hot electron damage, (vi) and electric field induced strain enhancement and relaxation [6]. A virtual gate formation is observed when the device is biased in off-state with a high negative gate-to-source voltage whereas the hot electron trapping occurs for the device biased in the on-state. It has been shown that degradation in the transconductance due to a high on-state stress is far more greater than that due to an off-state stress [27]. We assume that the trap generation in the drain access region provides a more plausible picture of the high electric field induced degradation. We also assume that traps could be generated at the vicinity of the gate due to the high electric fields, in addition to the ones that may be created at the surface due to process damage [30]. Substitutional carbon in GaN, CN, acting as acceptors is often unavoidably present during material growth. The unintentionally doped carbon concentration has been experimentally shown to reduce from 4 × 1017 cm−3 to 5 × 1016 cm−3 when the growth pressure is increased from 65 to 500 Torr [31]. We use the knowledge of these acceptor traps to simulate the effects of traps generation by assuming that these deep traps are created due to an applied electric field. Our results, expectedly, should be seen as a typical indication of the electric field induced trapping effects. We thus have located traps at an energy ET = EV + 0.9 eV [32], laterally from
Table 2 Extracted maximum drain current and cut-off frequency from the four scaled devices A–D. The devices E and F have additionally scaled down the gate-to-channel separation as indicated. Predicted values
Device A (LG = 1 μm, LGC = 33 nm)
Device B (LG = 0.5 μm)
Device C (LG = 0.25 μm)
Device D (LG = 0.125 μm)
Device E (LG = 0.5 μm, LGC = 17 nm)
Device F (LG = 0.25 μm, LGC = 8.25 nm)
IDmax (mA/mm) fT (GHz)
516.7 12.1
693 26.4
837.5 52.1
949 91.4
325 22.6
319.9 43
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L = −0.1 μm to L = 2.4 μm where the gate edge is set to be at zero (see Fig. 6). No significant change in the peak of the transconductance has been observed when this region is extended to the drain [6]. We show, however, in Fig. 7 that extending this traps generation region increasingly below the gate leads to a positive shift in the threshold voltage. This is consistent with observations in Ref. [29] which reports that donor-like traps are generated under on-state stress. These donor-like traps are spatially located underneath the gate and lead to a negative threshold voltage shift. Similarly, with increasing acceptor trap densities for traps extending to L = −0.1 μm from the gate edge (beneath the gate), a small positive increase in the threshold voltage is observed as shown in Fig. 8. More importantly, the decrease in the slope of these characteristics, which translates to decreasing transconductance, leads to a reduction in the cut-off frequency with increasing trap densities. Compared to the device without acceptor traps whose cut-off frequency is fT = 12.1 GHz, a reduction in the extracted cut-off frequencies by 7.7% and 17.6% for acceptor traps densities of NIT = 5 × 1017 cm−3 and NIT = 1 × 1018 cm−3, respectively, is observed. The large trapping density of 1 × 1018 cm−3 leads also to a significant shift of threshold voltage by about 0.6 V. If the trap density does not exceed NIT = 1 × 1017 cm−3, the cut-off frequency is not affected as can be seen from nearly overlapping ID–VGS characteristics in Fig. 8. In Fig. 9, we compare the effects of electric field generated traps densities of 5 × 1016 cm−3, 5 × 1017 cm−3 and 5 × 1018 cm−3 respectively. The drain current becomes extremely small as it is strongly suppressed by carriers captured by acceptor traps if the generated trap density is 5 × 1018 cm−3 as shown in Fig. 9. On the other hand, Fig. 9 also shows that the drain current changes insignificantly in the characteristic when the acceptor traps density is assumed to be 5 × 1016 cm−3. Note here that the acceptor traps density can reach 1012 cm−2 (equivalent to 1019 cm−3) as shown in Ref. [6] to reproduce experimental observations in GaN HEMTs. 5. Trapping effects on a laterally scaled device In order to gain some insight into how device behaviour in a laterally scaled device is affected by the traps, we have scaled down the traps generation region in proportion to the various device dimensions. Assuming a relatively small value of the trap density up to 1017 cm−3 for smaller device dimensions may not, in reality, represent accurately the effects of traps as smaller devices would experience higher electric fields under similar biases. We observe in Fig. 9 that the current is seemingly unaffected due to small kinetic energy of electrons insufficient to trap them into a trap energy level (ET = EV + 0.9 eV) at a relatively
Fig. 6. Scheme of simulated acceptor traps distribution in the 1 μm gate length GaN HEMT.
Fig. 7. Simulated transfer characteristics (ID-VGS) at a fixed VDS assuming increasing an indicated lateral location of acceptor traps generated underneath the gate on the drain side (see Fig. 6).
small VGS. All scaled devices show an increasing decline of the oncurrent when the trap density is NIT = 5 × 1017 cm−3 and even further, there is no current for a trap density of NIT = 5 × 1018 cm−3 as shown. However, there is a distinguishable negative threshold voltage shift of −0.7 V for the 0.125 μm gate length device even the 0.25 μm gate length device exhibits a small shift of about −0.2 V as well. As the device dimension is reduced, due to the high lateral fields, the carriers have higher kinetic energies and are expected to travel at higher velocities thereby increasing the probability of carrier capture. Fig. 10 shows a relationship between the inverse cut-off frequency, fT, and the gate length. Similar to our previous observations, the effect of acceptor traps having a fixed density of NIT = 5 × 1017 cm−3 on the cut-off frequency is predicted to reduce as the dimensions of the device is scaled down. This diminishing effect of traps during the GaN HEMT scaling occurs despite a reduction of the saturation current of 17.6% for the 1 μm gate length transistor to 20.4% for the smallest 0.125 μm gate length one. 6. Conclusions The detrimental effect of traps generated by a high electric field in the stressed GaN HEMTs has been studied in scaled devices. The study is based on accurate calibration of the TCAD model to experimental transfer and output characteristics of 1 μm gate length GaN HEMT
Fig. 8. Simulated transfer characteristics (ID-VGS) at VDS = 5 V of the HEMT for indicated acceptor trap density.
Please cite this article as: B. Ubochi, et al., Operational frequency degradation induced trapping in scaled GaN HEMTs, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.008
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to 0.125 μm. When the traps density exceeds 5 × 1018 cm−3, the device current becomes diminished with a complete collapse of fT. Acknowledgements This research is funded by the Sêr Cymru National Research Network in Advanced Engineering and Materials [Grant code: NRN081]. We thank Edward Wasige and Abdullah Al-Khalidi of the University of Glasgow for providing us with the experimental data. References
Fig. 9. Simulated transfer characteristics (ID-VGS) at VDS = 5 V of the 1 μm gate length device for the lateral scaling only comparing devices with no traps and with acceptor trap densities of 5 × 1016 cm−3, 5 × 1017 cm−3 and 5 × 1018 cm−3, respectively.
with fT = 12.1 GHz obtained using commercial simulation software Atlas by Silvaco. The scaled device exhibits improvement in the RF performance by increase in the cut-off frequency (fT = 12.1 GHz) by 118% (fT = 26.4 GHz), 330% (fT = 52.1 GHz) to 655% (fT = 91.4 GHz), when the gate is scaled down proportionally in lateral dimensions from 1 μm to 0.5 μm, 0.25 μm and 0.125 μm respectively. We have also found that the vertical scaling aiming to increase the gate control [24] or to make the device normally-off [33] will reduce the current density with an attendant negative effect on both DC and RF power performance. We have seen that the high electric field induced trapping leads to a positive threshold voltage shift for traps increasingly located under the gate, and to an increase in the on-resistance for traps located in the drain access region. We have also reported that, at low VGS, the current is seemingly unaffected due to small kinetic energy of electrons making the carrier trapping negligible. For shorter gate lengths, the linear part of the transfer characteristic and, hence, the maximum transconductance are apparently unaffected by traps despite a reduction of the saturation current by 17.6% in the 1 μm gate length transistor to about 20.4% for the smallest 0.125 μm gate length one. Finally, the effect of traps on fT, assuming a traps density of 5 × 1017 cm−3, for a laterally scaled device is consequently reduced during the scaling of gate length from 1 μm
Fig. 10. Simulated 1/fT versus gate length (LG) at VDS = 5 V for laterally scaled devices without traps and with acceptor trap density of 5 × 1016 cm−3 and 5 × 1017 cm−3.
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