Investigation into trapping modes and threshold instabilities of state-of-art commercial GaN HEMTs

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Investigation into trapping modes and threshold instabilities of state-of-art commercial GaN HEMTs K. Mukherjee , C. De Santi, M. Rzin, Z. Gao, G. Meneghesso, M. Meneghini, E. Zanoni ⁎

Department of Information Engineering, University of Padova, Padova, Italy

ABSTRACT

This work is aimed at investigating the performance and reliability limits of a commercially available state-of-the-art RF GaN HEMT technology. Measurement strategies to recognize and assess trap-induced degradations, prevalent in mature technologies, are discussed. Double pulsed measurements are used to capture and quantify threshold instabilities, and their evolution with temperature, for short quiescent near-threshold and off-state stress conditions. A versatile transient measurement technique evaluates threshold voltage fluctuations in the 10 μs–100 s temporal range, during stress or recovery phases, for different trap-filling configurations. Corresponding recovery transients between 27 °C to 130 °C are analysed to extract a trap activation energy of 0.53–0.56 eV for this technology. Finally, drain and gate step-stress tests are performed, providing an overview into the robustness of the gate contact under high electric fields.

1. Introduction Highly reliable GaN HEMTs have entered the commercial RF market over the last decade, a testament to the impressive growth of performance metrics in telecommunication and power amplifier application domains. However, even mature technological processes are subject to trap induced limitations, especially under high frequencies or aggressive operational biases. Over the last decade, detailed discussions into stress induced degradation modes and trapping kinetics [1–12] have contributed to improving our understanding into the physics, activation and impact of trap states in RF devices under aggravated operational conditions. However, most papers deal with research-level devices, and in most cases the analyses are carried out on small transistors, taken from process control monitor (PCM) structures located on wafers [1–4]. On the other hand, commercial devices have a completely different layout, handle much higher current densities and power dissipation levels; yet, no extensive description of trapping and degradation limits on commercial RF GaN HEMTs has been presented in the literature to date. This work serves to bridge this gap by extending our learnings and interpretations to provide a comprehensive outlook into the robustness and operational instabilities of one of the few commercially available RF GaN technologies. This evaluation also facilitates better comparisons between the contemporary and next generation of prospective device performances. 6 bare die GaN HEMTs available in Gel-Pak containers, have been subjected to step stress and pulsed analyses. The devices under study

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are intended for applications in cellular frameworks or linear amplifiers, with an operational drain voltage (VD) of 50 V and for frequencies up to 6 GHz. Absolute drain-source and gate-source voltage (VG) ranges are defined as (0–150 V) and (−10 to +2 V) respectively with a drain current limit of 3.2 A at 25 °C. The typical threshold voltage Vth is −3.0 V. In Section 2, double pulsed measurements are discussed for a gate lag configuration (quiescent VG = 0 V to −9 V, quiescent VD (=0 V)), and a drain lag configuration (VG,Q = −6 V, VD,Q = 0 V to 50 V). The shifts in threshold voltages are studied with temperature and bias. Section 3 describes Vth transients during 100 s of gate voltage stress (0 V to −10 V), followed by recovery of 100 s at (VG, VD) = (−4 V, 0 V). The evolution in Vth with time and temperature are discussed. Section 4 describes the step stress tests to evaluate robustness: reverse stepping VG with a floating drain (4.1), stepping VD while VG is biased beyond pinch-off (4.2). Section 5 summarises and concludes the work. 2. Double pulsed measurements The double pulsed I-V measurements [2,10–11] monitor dynamic device behavior with a high degree of flexibility and accuracy. Quiescent gate (VG,Q) and drain (VD,Q) biases that represent aggravating trap-filling or stress conditions are used to capture the presence and extent of relatively fast traps, otherwise undiscernible in DC behavior. The biasing setup alternates between constant voltage quiescent conditions (Q (VG, VD) for time tQ = 100 μs), and measurement ID-VG sweep conditions (VG = −5 to −1 V in 0.1 V steps at

Corresponding author. E-mail address: [email protected] (K. Mukherjee).

https://doi.org/10.1016/j.microrel.2019.113464 Received 15 May 2019; Received in revised form 11 July 2019; Accepted 21 July 2019 0026-2714/ © 2019 Elsevier Ltd. All rights reserved.

Please cite this article as: K. Mukherjee, et al., Microelectronics Reliability, https://doi.org/10.1016/j.microrel.2019.113464

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VD = 0.1 V, tmeas = 1 μs) to capture threshold voltage drifts (from IDVG, extracted at ID = 2.5 mA) in response to changing quiescent settings. For the gate pulsing set at VD = 0 V, Q (VG, VD) conditions are varied from (0,0) to (−9,0) V in 1 V steps as displayed in Fig. 1(a) for room temperature conditions. Similarly, Fig. 1(b) illustrates the drain pulsing effects where VG,Q is fixed at −6 V in deep pinch-off, while VD,Q is increased from 0 V to 50 V in 10 V steps. Associated Vth deviations from the initial value at (VG, VD) = (0 V, 0 V) are presented in Fig. 1(c) and (d) respectively, along with its evolution with temperature, from corresponding measurements performed at T = 100 °C and 130 °C. For VG,Q effects in Fig. 1(a) and (c), Vth drifts are dissimilar for nearthreshold (0 V > VG,Q > −4 V) and pinch-off (VG,Q < −4 V) conditions: (i) Under pinch-off, progressive positive Vth shifts could be a consequence of injected electrons from the gate into trap levels within the barrier or buffer [11]. Maximum ΔVth is lower than 0.4 V, and usually recoverable within minutes. (ii) For VG,Q close to device threshold, Vth shows small negative shifts, i.e. moves towards more negative values. In this device, the effect is appreciable only at 100 °C, however in some other devices, this shift is quite pronounced, even at room temperature. It could be associated to vertical leakage currents in the barrier layer. For VG,Q values higher than (less negative) than Vth, the channel is not completely depleted and most of the applied potential falls between the gate and the channel. As such, the significant potential difference across the barrier layer could support higher tunnelling probabilities [12]. Thus, leakage flow across the barrier in conjunction with perturbations in the effective VGD potential could lead to the observed negative ∆Vth. The field could be the dominant accelerating factor to tunnelling, owing to which temperature effects are nominal. When the channel is completely depleted, such as for │VG,Q│ > > │Vth│, the vertical leakage components are inhibited. Thus, Vth drifts to more positive values due to the accumulation of electrons in the barrier. Off-state trapping effects, and the associated positive ΔVth, is generally reduced at high T and notable at high │VG,Q│. This could be due to shorter trap emission times. From Fig. 1(b) and (d), it is evident that a high VD,Q with higher associated field, has a stronger effect on pulsed ID-VG and thus, on Vth deviation, than VG,Q. Positive ΔVth at room temperature ranges from 0.7 V to 1.2 V between different devices, and increases linearly with VD,Q. Responsible traps can be attributed to deep levels, dominantly under the gate [2,13], dependent on material or processing constraints. Here too, the trapping impact is lower at a high T. 3. Extraction of threshold transients A second pulsing setup is employed to further investigate the effect of reverse VG. It is specifically tailored to capture threshold drifts or transients over short-to medium stress and recovery cycles. It allows visualization of recovery current transients (and thus, Vth evolution), which allows accurate extraction of de-trapping time constants. By extension, thermally assisted recovery transients can yield Arrhenius plots, allowing us to identify properties of deep levels responsible for Vth deviation [2,14–15], most importantly, the activation energy. Effects of reverse gate stress (VG,Stress) for 100 s stress times are investigated, when followed by 100 s of recovery at (VG,VD) = (−4 V, 0 V). Numerous ID-VG measurements for VG = −5 V to −1 V at VD = 0.1 V are made either during the stress or the subsequent recovery period. The ramp time is 10 μs. Fig. 2(a) illustrates the drift in threshold voltage extracted from IDVG characterization during the stress period as VG,Stress varies from

Fig. 1. Double pulsed measurements. ID-VG at T = 27 °C for (a) gate pulsing quiescent conditions Q(VG,VD) = (0,0) to (−9,0) and (b) drain pulsing quiescent conditions Q(VG,VD) = (0,0), (−6,0) to (−6,50). Corresponding shifts in threshold voltage with (c) gate quiescent voltage and (d) drain quiescent voltage at T = 27 °C, 100 °C and 130 °C.

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−4 V to −10 V at room temperature. Fig. 2(b) presents Vth transients for VG,Stress = −10 V during the recovery period for different T = 27–130 °C. By exponential fitting of the recovery transients such as in Fig. 2(b), different trap signatures can be identified. Focusing on trap E1 as indicated in Fig. 2(b), Arrhenius plots are obtained for all VG,Stress cases, as displayed in Fig. 2(c). Amplitudes of the corresponding exponential fit function representing shifts in Vth for each VG,Stress as a function of T are summarised in Fig. 2(d). In Fig. 2(a), ΔVth under off-state stress (VG,Stress ≤ −6 V) shifts towards positive (less negative) values as the stress cycle progresses. Vth drift grows steadily until stress times of 100 ms, beyond which Vth saturates, because all active trap states are occupied. As previously discussed, positive ΔVth is attributable to electron injection from the gate into trap levels, possibly extending across AlGaN/GaN layers. During the 1–100 s stress period, Vth shows little change as the available trap density is filled, and the stress field or time are insufficient to form new trap states. ΔVth is expectedly higher at greater VG,Stress which induces higher electric fields. Maximum ΔVth is around 0.3–0.4 V, comparable to gate pulsing effects observed with double pulsed measurements. An additional note is a small disparity in initial |Vth| ≈ (0.05–0.1 V) observed between VG,Stress = −8 V and − 10 V cycles (at t = 10−5 s in Fig. 2(a)). This displays that complete recovery of Vth for high VG,Stress > 6 V takes longer than the 100 s recovery window. The VG = −4 V characteristic shows a different trend. Stable initially, ΔVth shifts to negative values beyond 10 ms before saturating. This is probably due to barrier leakage effects dominating at small VG. This is in accordance with observations for VG,Q ≤ Vth in Section 2, where small negative ΔVth was observed for stress times of 10 μs. Vth transients during recovery period in Fig. 2(b) show a dominant peak between 100 μs to 1 ms as well as a considerable reduction in drift at higher T for VG,Stress = −10 V. The E1 peak is observed for all VG,Stress conditions between 0 V to −10 V. Arrhenius plots for each VG,Stress in Fig. 2(c) reveal a trap activation energy between 0.53 and 0.57 eV, reported in several other works [2,14–16]. Since this trap affects all VG,Stress biases, it is potentially a defect located within the epitaxial layers. Its origin has been greatly debated in previous works [2,14] which indicate links with intrinsic defects. Although this trap has a clear relationship to Fe doping levels in the buffer, there have been several instances [2] where the trap signature is present even without Fe doping. Hence, while we might assume a link to buffer composition, definitive answers cannot yet be provided. Finally, the transient amplitudes in Fig. 2(d) clearly distinguish two different bias and temperature dependencies for Vth modulation under varying VG,Stress. Trap-induced leakage mechanisms confined within the barrier (for |VG,Stress| ≤ 4 V) show small increases in Vth drift with temperatures up to 100 °C before decreasing. This drift becomes less dominant as |VG,Stress| increases (from −2 V to −4 V) wherein the lateral fields rise, and the channel is increasingly depleted. For higher |VG,Stress| ≥ 6 V cases, with a pinched-off channel, electron injection starts being relevant. Higher |VG,Stress| promotes stronger injection, and correspondingly higher trapped densities. Associated Vth shifts are thus proportional to |VG,Stress|. Higher temperatures reduce trapping efficiency and hence Vth drifts are expectedly lower. 4. Step-stress measurements 4.1. Gate step-stress with floating drain Fig. 2. Transient threshold voltage extraction for recovery at (VG, VD) = (−4 V,0 V). (a) Vth transients during gate stress −4 V to −10 V (b) Vth transients for temperatures = 27–130 °C during recovery (100 s) following VG,Stress = −10 V. (c) Arrhenius plots by exponential fitting of recovery Vth time constants for the E1 trap signature, for VG,Stress = 0 V to −10 V (step: 2 V) (d) corresponding exponential fit amplitudes at varying T and VG,Stress.

The robustness of the gate-source (G-S) diode is tested by reverse biasing the gate in incremental steps of −5 V from 0 V to −135 V for a step duration of 120 s. The drain is kept floating. After each step, a G-S diode characterization is performed for VG = −6 V to +1 V. Fig. 3 displays (a) gate current evolution with time through the step stress test and (b) associated DC IG-VG characteristics representing the degradation in the gate leakage with higher |VGS|. 3

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Fig. 3. Gate-source step stress experiment (with VS=VB = 0 V) from 0 V to −135 V (a) Evolution of IG with time and (b) IGS-VGS characteristics following each gate voltage step.

Fig. 4. Drain step stress from 0 V–250 V for VG = −9 V (with VS=VB = 0 V) with the major transitional points (a) Evolution of ID with stress time and (b) Vth extracted at ID = 2.5 mA from ID-VG measurements following each VD step.

The gate contact exhibits very robust behavior, enduring up to 130 V of reverse bias before demonstrating a catastrophic increase in leakage. During the first few stress steps (up to −65 V in Fig. 3(a)), the injection of electrons is suppressed by increasingly trapped electrons under the gate edge, which leads to an overall decrease in leakage during a stress interval. Leakage evolution in Fig. 3(b) suggests that the first departure from the steady state diode characteristic occurs at VGS = −45 V, which is well beyond the device application limit (−10 V). There is a shift in behavior from VG = −60 V to VG = −65 V (Fig. 3(b)) reflected in a couple decades of increase in tunnelling currents in the post-stress diode behavior (for VGS > −3 V). This could be due to onset of trap-assisted leakage paths and physical degradation. We also begin to notice jumps in the leakage current under stress (Fig. 3(a)) around −65 V. This is presumably due to the higher electric field creating further defects or breakdown points [3] in the deeper epilayers. The post stress diode leakage in Fig. 3(b) increases rapidly between −65 V and −95 V. For VGS ≤ −95 V, IG,Stress gets increasingly noisier (Fig. 3(a)) as leakage paths grow and spread, usually associated with aggravated degradation [1]. IG,Stress during intervals for |VGS| higher than a critical voltage of 110 V begin displaying an absolute increase in magnitude (Fig. 3(a)). Between −110 V and −120 V, the diode leakage in Fig. 3(b) shows a reversal: i.e. a decreasing IGS. Beyond, −120 V, IGS in Fig. 3(b) starts rising again, also mirrored in strong spikes observed in stress gate current (Fig. 3(a)). This is the precursor to the final irreversible breakdown observed at −135 V.

tools to assess device susceptibility to leakage-assisted breakdown mechanisms driven by high gate-drain electric fields. Several step-stress experiments were performed within and beyond technology specifications, for VG = −6 V to −60 V and VD = 300 V. During these tests (not shown), the device withstood drain leakage ≥4 mA/mm for high VD stress steps (VDG > 360 V) without suffering catastrophic breakdown. Vth changes of 0.3–0.5 V appear only for VD > 100 V. Fig. 4(a) presents the step stress evolution for the gate biased at −9 V, as VD is increased in steps of 10 V (step duration: 120 s) from 0 V to 250 V. An ID-VG sweep (VG = −5 to −1 V at VD = 0.1 V) follows each stress step to assess drifts in Vth (as displayed in Fig. 4(b)), before breakdown conditions are reached. Several regions of stress-induced variations in drain current leakage and Vth shifts can be identified. (1) For VD stress < 110 V, ID,Stress decreases from the beginning of the stress interval, which could be a result of occupied electron traps repelling further electron injection from the gate. (a) Until VD ≤ 50 V, Vth (in Fig. 4(b)) extracted from accompanying post stress ID-VG curves shows a small 0.1–0.15 V positive drift. This current reduction could arise from negatively charged traps in the AlGaN barrier [2–3]. (b) For VD > 50 V, and higher fields, Vth begins to show a negative shift once pre-existing trap distributions in the barrier saturate. As VDS gets progressively higher, electrons trapped in the barrier may be pulled towards the drain, leading to the observed negative Vth shifts.

4.2. Drain step-stress in off-state

(2) For VD > 110 V, physical degradation and associated defects might be triggering leakage growth, now observable in a rising ID,Stress.

Off-state drain step-stress tests [1,3,11,17] are commonly employed 4

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Having negated the initial 0.15 V of positive ∆Vth, the negative ΔVth trend continues and falls below the initial Vth (−2.85 V in Fig. 4(b)). The distinct behavioral trends in the post stress Vth indicates that the −110 V point coincides with two simultaneous transitions: (i) decreasing stress currents to increasing stress currents (ii) the fall in Vth compensating the positive shift and now falling beyond Vth0. This is strongly indicative of a change in nature of the device or its robustness. (3) Beyond VD = 190 V, jumps in the leakage current are observed, probably in response to increased defect density in the barrier and bulk regions. The sudden reversal from negative to positive ∆Vth beyond 200 V (Fig. 4(b)) should be a manifestation of strong physical degradation, very probably linked to activation of defect assisted leakage paths, which would agree with the jumps observed in stress currents. The associated high loss in current would revert the direction of Vth drift.

decade is an attestation to how physical understanding remains critical to the next stage of RF device development. Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. References [1] M. Meneghini, A. Stocco, M. Bertin, D. Marcon, A. Chini, G. Meneghesso, E. Zanoni, Time-dependent degradation of AlGaN/GaN high electron mobility transistors under reverse bias, Appl. Phys. Lett. 100 (3) (2012) 033505. [2] M. Meneghini, et al., Buffer traps in Fe-doped AlGaN/GaN HEMTs: investigation of the physical properties based on pulsed and transient measurements, IEEE Transactions on Electron Devices 61 (12) (2014) 4070–4077 Dec https://doi.org/ 10.1109/TED.2014.2364855. [3] E. Zanoni, M. Meneghini, A. Chini, D. Marcon, G. Meneghesso, AlGaN/GaN-based HEMTs failure physics and reliability: mechanisms affecting gate edge and Schottky junction, IEEE Trans. Electron Devices 60 (10) (2013) 3119–3131. [4] H.P. Rao, G. Bosman, Study of RF reliability of GaN HEMTs using low-frequency noise spectroscopy, IEEE Trans. Device Mater. Reliab. 12 (1) (2012) 31–36 March https://doi.org/10.1109/TDMR.2011.2173497. [5] K. Hirche, J. Lätti, M. Rostewitz, K. Riepe, B. Lambert, R. Lossy, J. Würfl, P. Waltereit, J. Kühn, R. Quay, F. van Raay, M. Dammann, M. Cäsar, S. Müller, D. Marcon, S. Decoutere, M. Auf der Maur, A. Di Carlo, J. Pomeroy, M. Kuball, “GaN Reliability Enhancement and Technology Transfer Initiative (GREAT2)”, Abstract of the ESA/ESTEC Contract No. 21.499/08/NL/PA, (2015). [6] Alamo Joh, Mechanisms for electrical degradation of GaN high-electron mobility transistors, Proc. IEEE IEDM, 2006, pp. 1–4 Dec. [7] D. Marcon, T. Kauerauf, F. Medjdoub, J. Das, M. Van Hove, P. Srivastava, K. Cheng, M. Leys, R. Mertens, S. Decoutere, G. Meneghesso, E. Zanoni, G. Borghs, A comprehensive reliability investigation of the voltage-, temperature- and device geometry-dependence of the gate degradation on state-of-the-art GaN-on-Si HEMTs, Tech. Dig. - Int. Electron Devices Meet. IEDM, 2010, pp. 472–475. [8] S. Karboyan, J.G. Tartarin, M. Rzin, L. Brunel, A. Curutchet, N. Malbert, N. Labat, D. Carisetti, B. Lambert, M. Mermoux, E. Romain-Latu, F. Thomas, C. Bouexiere, C. Moreau, Influence of gate leakage current on AlGaN/GaN HEMTs evidenced by low frequency noise and pulsed electrical measurements, Microelectron. Reliab. 53 (2013) 1491–1495, https://doi.org/10.1016/j.microrel.2013.07.020. [9] F. Zeng, J. An, G. Zhou, W. Li, H. Wang, T. Duan, L. Jiang, H. Yu, A comprehensive review of recent progress on GaN high electron mobility transistors: devices, fabrication and reliability, Electronics 7 (2018) 377, https://doi.org/10.3390/ electronics7120377. [10] G. Meneghesso, M. Meneghini, I. Rossetto, E. Canato, J. Bartholomeus, C. De Santi, N. Trivellin, E. Zanoni, GaN HEMTs with p-GaN gate: Field- and time-dependent degradation, Proc. SPIE 10104, Gallium Nitride Materials and Devices XII, 1010419 2017, https://doi.org/10.1117/12.2250334 16 February. (doi:10.1117/12. 2250334). [11] M. Meneghini, et al., Field-dependent degradation mechanisms in GaN-based HEMTs, 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2016, pp. 77–80, , https://doi. org/10.1109/IPFA.2016.7564252. [12] E.J. Miller, X.Z. Dang, E.T. Yu, Gate leakage current mechanisms in AlGaN/GaN heterostructure field-effect transistors, J. Appl. Phys. 88 (10) (2000) 5951–5958. [13] M. Meneghini, N. Ronchi, A. Stocco, G. Meneghesso, U.K. Mishra, Y. Pei, E. Zanoni, Investigation of trapping and hot-electron effects in GaN HEMTs by means of a combined electrooptical method, IEEE Trans. Electron Devices 58 (9) (2011) 29963003. [14] A. Hierro, et al., Capture kinetics of electron traps in MBE-grown n-GaN, Phys. Status Solidi B 228 (1) (2001) 309–313. [15] H.K. Cho, C.S. Kim, C.-H. Hong, Electron capture behaviors of deep level traps in unintentionally doped and intentionally doped n -type GaN, J. Appl. Phys. 94 (3) (2003) 1485–1489. [16] A.R. Arehart, A. Sasikumara, G.D. Via, B. Poling, E.R. Heller, S.A. Ringel, Evidence for causality between GaN RF HEMT degradation and theEC-0.57 eV trap in GaN, Micro. Reb 56 (2016) 45–48. [17] J. Joh, L. Xia, J.A. del Alamo, Gate current degradation mechanisms of GaN high electron mobility transistors, Proc. IEEE IEDM, 2007, pp. 385–388. [18] D. Bisi, M. Meneghini, C. De Santi, A. Chini, M. Dammann, P. Bruckner, M. Mikulla, G. Meneghesso, E. Zanoni, Deep-level characterization in GaN HEMTs-part I: advantages and limitations of drain current transient measurements, IEEE Trans. Electron Devices 60 (10) (2013).

As validation to the ruggedness of the gate, leakage characteristics during stress do not become substantially noisy even at VD = 250 V, which might explain why no catastrophic breakdown is observed in this case. Overall, while physical structure is expected to be worsened following the step stress at VG = −9 V (approaching specified boundaries), even with a high source to drain leakage [11], gate breakdown is not achieved. The device remains functional with reduced performance. 5. Conclusion A combination of pulsed and step-stress analysis was performed for reliability assessment of a commercially available, mature RF GaN technology. Double pulsed measurements with tmeas/tQ = 1/100 μs/μs approaching technology biasing boundaries, captured positive Vth shifts of ΔVth = 0.3–0.4 V and ΔVth = 0.7–1.2 V under off-state, for maximum gate and drain quiescent stresses of −10 V and 50 V respectively. Some dispersion in ΔVth magnitudes ( ± 0.2 V) was observed within the six measured devices. These shifts are comparable to other works on AlGaN/GaN HEMTs [2,18]. Thus, deep levels with de-trapping constants longer than 100 μs are identified. Shifts are attributed to negative trapped charge accumulation due to electron injection, under the gate and across epitaxial layers. Small negative ΔVth = 0.1–0.2 V observed for sub and near threshold gate stresses is asserted to be the effect of vertical leakage in the barrier layer, associated with changes in effective potential. Trapping or detrapping instances between 10 μs to 100 s during high reverse gate stress and off-state recovery periods also show different Vth trends during low (negative ΔVth) and high (positive ΔVth) VG stress. Negative Vth drifts strengthen with longer stress times, and are presumably field dominated, displaying nominal modulation with temperature. Positive Vth drifts saturate after stress times of 100 ms, once active trap sites are fully occupied. Overall, the devices displayed very good tolerances to high field stress conditions. Gate-source diode breakdown was estimated at −135 V of reverse gate bias. For drain step stress at VG = −9 V, degradation due to increased source-drain leakage was observed, with a leakage of 3 mA at VD = 240 V. The trap level extracted from Vth transients, responsible for the positive shifts, with activation energy of 0.53–0.57 eV, closely agrees with other reports [2,16,18]. Although, most works link it to an intrinsic defect possibly located in the buffer, contrasting reports exist as well, and as such the origin of this trap remains unsubstantiated. The wide prevalence of this trap in transistors fabricated over the last

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