Current-mode capacitorless integrators and differentiators for implementing emulators of fractional-order elements

Accepted Manuscript Current-Mode Capacitorless Integrators and Differentiators for Implementing Emulators of Fractional-Order Elements Panagiotis Bertsias, Costas Psychalinos, Ahmed Elwakil, Brent Maundy PII: DOI: Reference:

S1434-8411(17)31250-5 http://dx.doi.org/10.1016/j.aeue.2017.06.036 AEUE 51954

To appear in:

International Journal of Electronics and Communications

Accepted Date:

28 June 2017

Please cite this article as: P. Bertsias, C. Psychalinos, A. Elwakil, B. Maundy, Current-Mode Capacitorless Integrators and Differentiators for Implementing Emulators of Fractional-Order Elements, International Journal of Electronics and Communications (2017), doi: http://dx.doi.org/10.1016/j.aeue.2017.06.036

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Current-Mode Capacitorless Integrators and Differentiators for Implementing Emulators of Fractional-Order Elements Panagiotis Bertsias1 (PhD Student), Costas Psychalinos1* (PhD), Ahmed Elwakil2 (PhD), and Brent Maundy3 (PhD) 1Electronics

Laboratory, Physics Department, University of Patras,

Rio Patras, GR 26504, Greece, (e-mail: [email protected]; [email protected]) 2 Department

of Electrical & Computer Engineering, College of Engineering, University of Sharjah, P.O. 27272, Sharjah, Emirates, (e-mail: [email protected])

3Department

of Electrical and Computer Engineering, University of Calgary, Alberta, T2N 1N4, Canada, (e-mail: [email protected])

* Corresponding author

Current-Mode Capacitorless Integrators and Dierentiators for Implementing Emulators of Fractional-Order Elements Panagiotis Bertsiasa , Costas Psychalinosa,∗, Ahmed Elwakilb , Brent Maundyc b

a Department of Physics, Electronics Laboratory, University of Patras, Patras, GR 26504,Greece. Department of Electrical & Computer Engineering, College of Engineering, University of Sharjah, P.O. 27272, Sharjah, Emirates. c Department of Electrical and Computer Engineering, University of Calgary, Alberta, T2N 1N4, Canada.

Abstract

Fractional-order capacitor and inductor emulator, implemented using current-mirrors as active elements and MOS transistors as capacitors, is introduced in this paper. Current-mirror integrators are used for performing the required current-mode integration/dierentiation operation within the emulator stage. Also, a voltageto-current converter, implemented using an Operational Transconductance Amplier, is utilized for realizing the required interface of the input signal. Thus, the proposed emulator is simultaneously capacitorless and resistorless and oers the advantage of electronic tuning of the characteristics as well as of the type of the emulated fractional-order element. In addition, a modied version of the emulator that allows current excitation is proposed. The evaluation of the behavior of the proposed schemes have been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 µm CMOS process. Keywords:

circuits.

Current-mode circuits, Fractional-order circuits, Fractional-order impedance, Capacitorless

1. Introduction

Fractional-order elements are very important devices for the hardware implementation of circuits, derived according to the concept of the fractional-order calculus, in various interdisciplinary applications [1]. A fractional-order capacitor, known also as Constant Phase Element (CPE), has an impedance

cos απ sin απ 1 2 2 ZCα ,α (s) = = + (1) Cα sα ω α Cα jω α Cα where Cα has the units of F arad/ sec1−α and 0 < α < 1 is the order of CPE. It is seen from (1) that apart from the frequency dependent resistive losses, the relationship between capacitance (C) in F arad and pseudo-capacitance is given by [2] ω α−1
C = Cα (2) sin απ 2 In a similar way, the relationship between inductance and pseudo-inductance in a fractional-order inductor (FI) ZLβ ,β (s) = Lβ sβ can be given by [2]   sin βπ 2 L = Lβ (3) ω 1−β where Lβ is the pseudo-inductance in units of Henry/ sec1−β . However, to simplify the targeted circuit design, the unit-less sin(απ/2) and sin(βπ/2) terms in (2)-(3) are absorbed within the values of Cα and Lβ ∗ Corresponding author (e-mail:[email protected])

Preprint submitted to AEU

June 29, 2017

2

✂1

i

i

✂2

-

+

gm,VI

Hr(s)=(s/ -

✁ ✄r +

Figure 1: General concept for CPE/FI emulation.

respectively and, therefore, the following transformation [3, 4] will be employed

C, L =

Cα , Lβ ω 1−α,β

(4)

Although signicant research is currently being pursued towards implementing passive solid-state CPEs exploring dierent types of materials [5, 6, 7, 8, 9, 10, 11], this type of element is not yet commercially available. As a result, the development of structures that approximate the behavior of CPEs around a center frequency ωo is important from a practical point of view. The initially proposed solution is based on the employment of passive RC networks [12, 13, 14, 15], but it has the obstacle that the whole network must be re-designed in order to change the characteristics of the element (i.e. Cα ,α) as well as the center frequency ωo of the approximation. Also, the implementation of FI emulators has been performed through the combination of a CPE emulator and a Generalized Impedance Converter (GIC) [16]. An alternative solution is based on the utilization of an approximated fractional-order dierentiator/integrator with a voltage-to-current (V /I ) converter. This has been followed in [17], where Current Feedback Operational Ampliers (CFOAs) have been used as active elements. Based on the same concept, the emulators in [18, 19, 20], where Operational Transconductance Ampliers (OTAs) have been used as active elements, oer the additional advantages of the electronic tuning of the order, impedance, and bandwidth of operation just by changing the values of time-constants and scaling factors. This originates from the employment of the bias dependent small-signal transconductance parameter (gm ) of the OTA cells to realize time-constants of the form: τ = C/gm . The capability for implementation in fully integrated form is only limited by the values of capacitors. The contribution made in this paper is that for the rst-time in the literature, capacitorless emulators of CPEs/FIs are introduced. This is achieved by the employment of MOS transistors for realizing the required passive capacitors and the derived structure oers signicant reduction of the totally required silicon area, compared with the emulator in [20]. The paper is organized as follows: the design procedure is presented in Section 2, while the transistor level implementation of the emulator is given in Section 3. A modied version of the emulator, that allows current excitation, is introduced in Section 4 where the performance of the emulators is evaluated using the Analog Design Environment of the Cadence software and the Design Kit proved by the Austrian Micro Systems (AMS) 0.35 µm CMOS process.

2. General Design Procedure of CPE/FI Emulators

The proposed concept for emulating CPEs/FIs around a center frequency ωo using a current-mode core block is demonstrated by the Functional Block Diagram (FBD) in Figure 1. According to this FBD, the voltage excitation is converted into a current through the OTA with transconductance gm,V I . This current is further processed by a stage described by the transfer function Hr (s) = (s/ωo )r . The emulated impedance is given by the expression in (5) 1  r Zeq (s) = (5) gm,V I · ωso

3

iin

+

1

1

G2

✁1s

1 1 G1

1

11 ✁2s

Go

iout

+

Figure 2: Approximation of the

iout

Hr (s) in Figure 1 using the current-mode technique.

Table 1: Design equations for the emulation of CPE

Parameter gm,V I

Expression Cα ωoα or L 1ωβ β  o  2 r −3r+2 8−2r 2

1 ωo

τ1

1 ωo

τ2

(r = α) and FI (r = −β) .



8−2r 2



r 2 +3r+2 r 2 +3r+2 r 2 −3r+2

G2 G1 Go

1 r 2 −3r+2 r 2 +3r+2

where r = {α, −β} for CPE and FI, respectively. Note that | Z(ωo ) |= 1/gm,V I and, therefore, the transconductance of the V /I converter determines the impedance of the emulated element at the center frequency ωo . The transfer function Hr (s) in (5) can be approximated using the 2nd -order form of the Continued Fraction Expansion [21, 22], and the derived expression of the impedance will be

Zeq (s) ≈

1 gm,V I

·

r 2 −3r+2 2 8−2r 2 2 r 2 +3r+2 s + ωo · r 2 +3r+2 s + ωo 2 2 2 r −3r+2 s2 + ωo · r28−2r +3r+2 s + ωo · r 2 +3r+2

(6)

The implementation of the approximation of the Hr (s), using an integer-order circuitry, could be performed by the Follow-the-Leader Feedback (FLF) block diagram depicted in Figure 2. In this case, the emulated impedance will be given by

Zeq (s) ≈

1 gm,V I

·

1 2 1 1 G2 s + G2 τ1 s + G2 τ1 τ2 s2 + GG2 1τ1 s + G2Gτo1 τ2

(7)

Thus, the values of time constants {τ1 , τ2 } as well as of scaling factors {Go , G1 , G2 } are calculated by equating the coecients of the expressions in (6) and (7). Using also (4), the design equations for emulating a CPE or FI with characteristics {Cα , α} or {Lβ , β}, around a center frequency ωo , are summarized in Table 1. An important benet of the presented scheme is its exibility, in the sense that it is capable of emulating both types of factional-order elements, through appropriate selection of the values of time-constants {τ1 , τ2 } and scaling factors {Go , G2 }. Having determined the type of the element, the center frequency can be controlled through {τ1 , τ2 }, while the order of the element is controlled through a simultaneous change of {τ1 , τ2 } and {Go , G2 }. It should be also mentioned at this point that changing the center frequency and/or the order of the element, the value of the impedance will be also changed and this could be compensated through appropriate adjusting of the bias current of the V /I converter. The value of the pseudo-capacitance/inductance is electronically controlled through the transconductance parameter gm,V I of the V /I converter. Therefore, it is obvious that in the case that the time-constants and scaling factors are implemented in such way that are controlled by appropriate dc currents, then the identity of the fractional-order element would be fully electronically controlled. This will be performed in the next Section, using appropriately congured current-mirror stages.

4

VDD

1

K Mp1

G Io

Io

Mp2

iout

iin Mnc1

Mnc2

Vc

Io

Mn2

Mn1

Mn3

C VSS K

1

KG

(a)

K

VDD

1

Mp1

G Io

Io

Mp2

iout

iin Mnc1

Io

Mnc2

Vc Mn2

Mn1

Mn3

Mcap

Vm

VSS K

1

KG

(b) Figure 3: Low-frequency lossless integrator with electronic tuning of time-constant using (a) passive and (b) active capacitor.

3. Capacitorless Electronically Controlled CPE/FI Emulator

According to the Functional Block Diagram in Figure 2, the basic building block for implementing the characteristic transfer function H(s) is the lossless integrator with scaled output. A possible implementation of such stage, using cascode current-mirrors, is demonstrated in Figure 3a, where the branches denoted with K or K ∗ G represent transistors with aspect ratio K or K ∗ G times the aspect ratio of the corresponding diode-connected transistor (i.e. Mn1 and Mp1), respectively [23]. The realized transfer function is

H(s) = G ·

1 KC gm s

(8)

where gm is the transconductance parameter of the diode-connected transistor Mn1 , and G and K are scaling factors relative to the aspect ratio of the diode-connected transistors. Assuming that all transistors operate Io in the sub-threshold region, the transconductance will be given by the expression gm = nV , where Io is the T bias current, n is the sub-threshold factor of a MOS transistor (1 < n < 2), and VT is the thermal voltage (26 mV at 27o C ). Thus, the time-constant in (8) can be expressed as

τ =K·

nCVT Io

(9)

It is obvious from (9) that this time-constant can be electronically adjusted through the dc bias current Io . In addition, a capacitor scaling by a factor K is performed and this facilitates the implementation of large time-constants using capacitors with values which are reasonable for integration. This is achieved as follows: the input current (iin ) along with the dc bias currentIo are both scaled by a factor 1/K , due to the current-mirror formed by transistors Mp1-Mp2. In other words, a compression of the instantaneous value of the input signal is performed at the input of the integrator. As a result, the dc bias current of the transistor

5

K

VDD

1

Mp1

Io

Io

Mp2

iin Mnc1

Io

Mn2

Vm 1

IB

IB

G*iout

Mnc2 Mn4

Vc Mn1

IA

iout

Mn3

Mcap

K

K

Mn7

Mn5 Mn6

VDC

IA

IB

VDC

VSS

Figure 4: Capacitorless lossless integrator with electronic tuning of both time-constant and scaling factor.

Io Mn1 will be equal to Io /K and, accordingly its transconductance will be reduced to a value:gm = KnV and T the realized time-constant will be given by (9). The signal must be expanded to its initial level and this is performed setting the aspect ratio of transistor Mn2 K times the aspect ratio of Mn1, while in order to achieve an extra scaling factor G at the output of integrator, the aspect ratio of Mn3 must be chosen equal to K ∗ G times the aspect ratio of Mn1. It should be also mentioned that the scaling is achieved without any imposed restriction on the maximum amplitude of the input signal that can be successfully handled by this stage [23]. This topology has also been used for realizing fractional-order lters [24]. The topology in Figure 3a can become capacitorless through the substitution of the passive capacitor by an appropriately congured MOS transistor. A way for achieving that is through the utilization of a simple pMOS transistor where drain, source and bulk are shorted together, as it is demonstrated in Figure 3b. The capacitance in the accumulation and inversion regions is almost voltage independent and is used for the implementation of the capacitor. For the AMS 0.35 µm CMOS process, operation in the aforementioned regions is guaranteed in the case that| Vsg |> 1V [25]. Owing to the fact that this solution is fully compatible with the standard CMOS process, it does not have any impact in the cost of fabrication. Thanks to thin oxide which oers a large capacitance per unit area; it is possible to implement desired capacitor values with approximately 5 times smaller area, in comparison with double-poly capacitors. The equivalent capacitance is given by the following empirical expression

Ceq = −7.536 · 10−16 − 1.94 · 10−10 · W + 1.702 · 10−10 · L + 1.305 · 10−8 · W 2 + 0.004469 · W · L

(10)

The topology in Figure 3b suers from the absence of the electronic tuning of the gain factor G, because this factor is implemented by an appropriate selection of the aspect ratio of transistor Mn2, which is xed in the case that the circuit will be implemented in fully integrated form. A possible solution for achieving programmability is using digital logic and banks of output branches, but this suers from the fact that only specic values of the scaling factors can be implemented [26]. In order to overcome this obstacle, the topology in Figure 4 is presented. The realization of the scaling factor G is achieved by the translinear loop formed of the identical transistors Mn4-Mn7 and, according to the translinear principle [27], the following expression is realized

IB · (IA + iout ) = IA · (IB + G · iout )

(11)

Performing a routine algebraic analysis in (11) it is readily obtained that the scaling factor is given by

G=

IB IA

(12)

and, therefore, it can be electronically tuned through the ratio of the bias currents IA and IB . The full circuitry of the proposed capacitorless CPE/FI emulator is demonstrated in Figure 5. The implementation of the V /I converter has been performed using the improved linearity OTA [28] which assuming that all transistors are biased in the sub-threshold region, has a transconductance given by:

gm,V I =

5Io,V I 9nVT

(13)

Io

1

1

Mn1

Mp2

1

G2

Mp1

Vc

1

Figure 5: Full circuitry of the proposed capacitorless CPE/FI emulator. VDC

Mn12

Mn13

IA

Mn14

IB2

IB2

Vm

IA

1 Mn4

Mp4

1

I

1

1

Mn3

Mnc2 Vc

Mnc1 Mn2

Io

Io

Mp3

K

✂

input summation

1

Io,VI

VDC

Mn15

IB2

I

Mn17

Mnc10

I

Mn7

1

I

1

Mp7

1

i

I

1

Vm

VSS

Mn18

Mnc11

I

Mp13

VDC

Mn19

IBo

IBo

Mn20

IBo

IA

Mn21 VDC

Mn22

IA

K

Mn11

Mn10 Vc Mn9 Vc

K

Mnc8 Mnc7

Mnc6

K

Mpc2

Vc

Mp11

I

2 Mp10

1 2

I

integrators

Mp9

1

2 Mn8

Mp8

K

2

output summation VDD Mp12

VSS

I

Mno4

Mnb3

1:5

Mp6

VDD 1

Mnc5

K

1 Mp5

Mnc4 Vc

I

1

VSS

Mno2 Mno3

Mnb2

Mn6

K

Mn16

Mn5 Vc

Mnc3

K

Mpc1

Vc

I

Mnb1

VDD

5:1

✂

Mno1

✂

✂

i

✂

✂

1

Mpo2

✂

Mpo1

✂

✂

V/I converter

I

2

Go

1

✂

✂

✂

VDD

6

7 Table 2: Aspect ratio of MOS transistor in Figure 5.

Transistor M n1, M n4, M n12, M n16 M n8 M nb1 M no2, M no3 M nc1...M nc11 M p1, M p12 M p3 M p5 M p8 M p10 M po1

aspect ratio 10 µm/2 µm 20 µm/4 µm 10 µm/10 µm 5 µm/5 µm 20 µm/2 µm 40 µm/5 µm 600 µm/4 µm 30 µm/4 µm 220 µm/1 µm 11 µm/1 µm 60 µm/10 µm

Table 3: Values of dc bias currents for emulating CPE with pseudo-capacitance around a center frequency 100 Hz (Io,V I = 19.1 nA).

Bias current Io (nA) Io1 (nA) Io2 (nA) IA (nA) IB2 (nA) IBo (nA)

α = 0.3 120 83.7 4.9 100 248 31

α = 0.5 200 127 6.7 100 520 13

{45.45nF/sec0.7 , 12.5nF/sec0.5 , 3.45nF/sec0.3 }

α = 0.7 380 200 9.6 100 1300 3.5

4. Simulation Results and Discussion 4.1. Simulation Results

The performance of the proposed CPE/FI emulator was evaluated using the Analog Design Environment of the Cadence software and the Design Kit provided by the AMS 0.35 µm CMOS process. The employed power supply voltages of the system are: VDD = 0.75 V , VSS = −0.75 V . The bias voltage of the cascode transistors was VC = 580 mV , while in the gain stage wasVDC = −0.6 V . These values have been chosen in order to keep the transistors operated in the sub-threshold region. Also, the bias voltage of MOS transistors which operate as capacitors has chosen as Vm = 2 V , in order to guarantee their operation in the inversion region. Assuming that the capacitor multiplication factor is K = 20, the aspect ratios of the MOS transistors in Figure 5 are summarized in Table 2. The layout design of the emulator, depicted in Figure 6, occupies a silicon area equal to 327 µm × 1049 µm. CPEs with capacitance C = 500 pF at center frequency fo = 100 Hz and order {0.3, 0.5, 0.7} were emulated. Thus, the corresponding values of the pseudo-capacitance were: 45.45 nF/sec0.7 , 12.5 nF/sec0.5 , and 3.45 nF/sec0.3 , respectively. Considering that the capacitors in both integrators have the same value equal to 30 pF , then the aspect ratio of the MOS transistors that implement the capacitors (i.e. M cap1, M cap2) was calculated using (10), equal to 335 µm/20 µm. Using the design equations in Table 1 and the expressions in (9), (12), and (13), the derived values of the bias currents are summarized in Table 3. The distribution of the bias currents is performed using multiple output current mirrors with nMOS and pMOS transistors sized as 10 µm/2 µm and 1.5 µm/2 µm, respectively. The obtained impedance magnitude and phase post-layout responses are provided in Figure 7, where the corresponding theoretically predicted plots are also given by dashed lines. The simulated impedance magnitude and phase of CPEs at 100 Hz were {2.99, 2.92, 2.98}M Ω and {−26.9o , −44.9o , −63.5o }, close to the corresponding theoretical values 3.18 M Ω and {−27o , −45o , −63o }, respectively. Also, an error less than 10% for both the magnitude and phase over frequency band from 22 Hz to 600 Hz was achieved. Let us consider the case of a FI emulation with inductance L = 5 kH at center frequency fo = 100 Hz , and variable orders {0.3, 0.5, 0.7}. The pseudo-inductance in this case are 454.5 kH/sec0.7 , 125.3 kH/sec0.5 , and 34.5 kH/sec0.3 , respectively. The values of the bias currents are summarized in Table 4. The impedance

4.1

8

Simulation Results

Figure 6: Layout design of the proposed CPE/FI emulator.

9

Simulation Results

20 18 16

ideal alpha=0.3 alpha=0.5 alpha=0.7

Z (MOhm)

14 12 10 8 6 4 2 0 1 10

2

10 freq (Hz)

3

10

(a)

0 −10 −20

ideal alpha=0.3 alpha=0.5 alpha=0.7

−30 phase (deg)

4.1

−40 −50 −60 −70 −80 −90 1 10

2

10 freq (Hz)

3

10

(b) Figure 7: Post-layout simulation results of impedance (a) magnitude, and (b) phase of the CPE emulator.

10

Simulation Results

20 18 16

ideal beta=0.3 beta=0.5 beta=0.7

Z (MOhms)

14 12 10 8 6 4 2 0 1 10

2

10 freq (Hz)

3

10

(a)

90 80 70

ideal beta=0.3 beta=0.5 beta=0.7

60 phase (deg)

4.1

50 40 30 20 10 0 1 10

2

10 freq (Hz)

3

10

(b) Figure 8: Post-layout simulation results of impedance (a) magnitude, and (b) phase of the FI emulator.

4.2

11

Discussion

Table 4:

Values of dc bias currents for emulating FI with pseudo-inductance 34.5 kH/sec0.3 } around a center frequency 100 Hz (Io,V I = 19.1 nA).

Bias current Io (nA) Io1 (nA) Io2 (nA) IA (nA) IB2 (nA) IBo (nA)

β = 0.3 35 33.3 1.9 100 34 239

β = 0.5 25 25 1.3 100 15 500

{454.5 kH/sec0.7 , 125.3 kH/sec0.5 , and

β = 0.7 20 19.5 0.7 100 8 1000

magnitude and phase post-layout responses along with the corresponding theoretical plots are provided in Figure 8, where the magnitude of the impedance at 100 Hz was simulated as {3.23, 3.25, 3.40}M Ω close to the theoretical value 3.14 M Ω . The corresponding simulated and theoretical values of the phase were {25.7o , 44.7o , 62.3o } and {27o , 45o , 63o }, respectively, conrming the accuracy of the phase response. The band, where an error less than 10% for both the magnitude and phase is achieved, is 15 Hz to 575 Hz . The time-domain behavior of the emulator has been evaluated through its stimulation by a sinusoidal input voltage with frequency 100Hz and 60 mV peak-to-peak amplitude. The derived input-output waveforms are plotted in Figure 9. The sensitivity performance of the emulator, in terms of MOS transistor parameters mismatching as well as process parameters variations, was simulated using the Monte-Carlo analysis in Cadence. The statistical plots (N = 100 runs) about the impedance magnitude and phase of CPE at the center frequency (i.e. 100 Hz ), with α = 0.5 are given in Figure 10. The standard deviation of the magnitude and phase were 317 kΩ and 7.25o , respectively. In the case of FI (β = 0.5), the corresponding plots are depicted in Figure 11, where the values of standard deviation were 258.5kΩ and 6.5o , conrming that both schemes have reasonable sensitivity characteristics. 4.2. Discussion

The proposed emulator in Figure 5 oers, for the rst time in literature, emulation of CPEs/FIs without the employment of passive capacitors. Thanks to the employment of the capacitor scaling technique the required total capacitance is equal to 60 pF , instead to 1200 pF that corresponds to the case without capacitor scaling. In addition, the utilization of MOS transistors for implementing the capacitors oers a further reduction of the required area of capacitors by a factor of about 5 for the specic process and, therefore, in terms of area the equivalent total capacitance will be 12 pF , leading to a signicant saving of the silicon area. Another important factor is the transistor count which in the proposed emulator is equal to 93. Considering the case of the scheme in [20], the corresponding values of the equivalent capacitance and transistor count were 240 pF and 82, respectively. Therefore, the important benet oered by the proposed emulator is the signicantly reduced (by a factor 20) capacitor area and this is achieved at the expense of the circuit complexity which is increased by 15%. It should be also mentioned at this point that capacitorless CPE/FI emulators could be also implemented using the gate-source capacitance of the MOS transistor [29]. Owing to the fact that this capacitance is given by the expression: Cgs = (2/3) · W · L · Cox + W · Lov · Cox , where W, L are the dimensions of the transistor, Cox is the gate oxide capacitance per unit area, and Lov is the gate overlap length, this technique is appropriate for implementing high frequency (i.e. in the order of M Hz ) CPE/FI emulators because, in this range, the area required by the transistors that implement the capacitors will be reasonable for integration. The proposed emulator is appropriate for low-frequency applications, e.g. for bio-impedance measurements [30, 31]. These can be made using either voltage-excitation (potentiostatic measurement) or current-excitation (galvanostatic measurement) [32]. The emulator in Figure 5 is suitable only for voltage excitation and a possible solution for being capable for current stimulating is that demonstrated in Figure 12.The OTA at the input is appropriately congured (i.e. has two inverted outputs that are connected to the same node, where they cancel in ideal case) in order to perform a sense of the input current and to feed the current-mode integration/dierentiation stage and, simultaneously, to establish a low-impedance input node.

12

Discussion

40.0

15.0 voltage

30.0

12.0

current

9.0

V1-V2 (mV)

20.0

6.0

10.0

3.0

0.0

0.0

I (nA)

4.2

-3.0

-10.0

-6.0

-20.0

-9.0

-30.0

-12.0

-40.0

-15.0 50.0

60.0

70.0

80.0

time (ms)

(a) 40.0

15.0 current

30.0

12.0

voltage

9.0 6.0

10.0

3.0

0.0

0.0

I (nA)

V1-V2 (mV)

20.0

-3.0

-10.0

-6.0

-20.0

-9.0

-30.0

-12.0

-40.0

-15.0 50.0

60.0

70.0

80.0

time (ms)

(b) Figure 9: Time-domain behavior of the emulator for FI with β = 0.5.

100Hz , 60 mV peak-to-peak input voltage (a) CPE with α = 0.5 , and (b)

4.2

13

Discussion

20.0

No. of Samples

15.0

10.0

5.0

0.0 2.0

2.5

3.0 Z (MOhm)

3.5

4.0

(a) 20.0

No. of Samples

15.0

10.0

5.0

0.0 -70.0

-60.0

-50.0

-40.0

-30.0

-20.0

phase (deg)

(b) Figure 10: Monte Carlo simulations (N

= 100) of the (a) magnitude and (b) phase responses of the emulated CPE (α = 0.5).

4.2

14

Discussion

20.0

No. of Samples

15.0

10.0

5.0

0.0 2.0

2.5

3.0 Z (MOhm)

3.5

4.0

(a) 20.0

No. of Samples

15.0

10.0

5.0

0.0 20.0

30.0

40.0

50.0

60.0

70.0

phase (deg)

(b) Figure 11: Monte Carlo simulations (N

= 100) of the (a) magnitude and (b) phase responses of the emulated FI (β = 0.5).

✂

i -

+

gm,VI

i2

- + +

i1 i1

i1

H(s)=(s/

✁✄r

+

Figure 12: Block diagram for the emulation of a current excited CPE/FI.

4.2

15

Discussion

12

10

ideal alpha=0.5 beta=0.5

Z (MOhm)

8

6

4

2

0 10 1

10 2 freq (Hz)

10 3

(a)

80 60

ideal alpha=0.5 beta=0.5

phase (deg)

40 20 0 -20 -40 -60 -80 10 1

10 2 freq (Hz)

10 3

(b) Figure 13: Post-layout simulation results of impedance (a) magnitude, and (b) phase of the CPE/FI current excited emulator for Ca = 12.5 nF/sec0.5 and Lβ = 125.3 kH/sec0.5 .

16 Assuming that gm,V I is the transconductance of the V /I converter in Figure 12, then the current i1 can be expressed as

i1 = i − i2 = gm,V I · υ

(14)

Taking into account that

 i2 =

s ωo

r

 − 1 · i1

(15)

then, after an algebraic manipulation of (14)-(15), it is derived that the emulated impedance (Zeq ) is given by the expression in (5). The behavior of the emulator in Figure 12 has been evaluated through post-layout simulation results under the same conditions as in the case of its voltage excited counterpart. The obtained impedance magnitude and phase responses in the cases of CPE with Ca = 12.5 nF/sec0.5 and FI with Lβ = 125.3 kH/sec0.5 are plotted in Figure 13. The magnitude and phase of the impedance of CPE/FI, at 100 Hz , were simulated as {2.99, 2.80}M Ω and {−44.3o , 46.2o } with the theoretical values being {3.14, 3.18}M Ω and {−45o , +45o }, respectively. The band where an error less than 10% for both the magnitude and phase of CPE has been achieved was 40 Hz to 600 Hz , while for FI the corresponding band was 25 Hz to 550 Hz . 5. Conclusion

A novel capacitorless scheme for emulating CPEs/FIs has been introduced in this work. Compared with the corresponding already published OTA-C structures it oers the benet of the signicant reduction (by a factor 20 in the provided design example) of the total capacitor area at the expense of the slightly increased circuit complexity. The given post-layout simulation results show that an accuracy level 10%, for both the magnitude and phase of voltage excited CPE, can be achieved in the band from 22Hz to 600Hz , while for FI the corresponding band was 15 Hz to 575 Hz . For current excited CPE/FI, similar accuracy is achieved from 40 Hz to 600 Hz and from 25 Hz to 550 Hz , respectively. In addition, the proposed emulator has reasonable sensitivity characteristics and therefore, it could be considered as an attractive candidate for employment in low-frequency applications, including biological [33], and control systems [34]. Acknowledgments

This article is based upon work from COST Action CA15225, a network supported by COST (European Cooperation in Science and Technology).

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