Design and application examples of CMOS fractional-order differentiators and integrators

Accepted Manuscript Design and application examples of CMOS fractional-order differentiators and integrators Panagiotis Bertsias, Costas Psychalinos, Ahmed Elwakil, Leila Safari, Shahram Minaei PII:

S0026-2692(18)30687-6

DOI:

https://doi.org/10.1016/j.mejo.2018.11.013

Reference:

MEJ 4452

To appear in:

Microelectronics Journal

Received Date: 11 September 2018 Revised Date:

16 November 2018

Accepted Date: 27 November 2018

Please cite this article as: P. Bertsias, C. Psychalinos, A. Elwakil, L. Safari, S. Minaei, Design and application examples of CMOS fractional-order differentiators and integrators, Microelectronics Journal (2018), doi: https://doi.org/10.1016/j.mejo.2018.11.013. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

ACCEPTED MANUSCRIPT

Design and Application Examples of CMOS Fractional-Order Differentiators and Integrators Panagiotis Bertsiasa , Costas Psychalinosa,∗, Ahmed Elwakilb , Leila Safaric , Shahram Minaeid a Department

of Physics, Electronics Laboratory, University of Patras, Patras, GR-26504,Greece. of Electrical and Computer Engineering, University of Sharjah, Sharjah, P.O. 27272, Emirates. c Independent Researcher, Tehran, Iran. d Department of Electronics and Communications Engineering, Dogus University, Kadikoy, 34722 Istanbul, Turkey.

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b Department

Abstract

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Reduced complexity CMOS fractional-order differentiator and integrator building blocks are introduced in this work, based on 2nd -order integer-order transfer function approximations. These blocks are then used for implementing fractional-order filters as well as a Leaky-Integrate-and-Fire Mihalas-Niebur neuron model. Cascading 1st and 2nd -order blocks to obtain 5th -order integer-order transfer functions, improved bandwidth of approximation accuracy is achieved. Furthermore, the realization of floating fractional-order capacitor and inductor emulators is demonstrated. Keywords: Fractional-order circuits, fractional-order integrators, fractional-order differentiators, filters, neuromorphic circuits.

1. Introduction

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Fractional-order calculus is utilized in a variety of interdisciplinary applications [1, 2, 3], and towards this goal differentiation and integration stages are essential building blocks for performing the required signal processing. Various applications of fractional-order circuits in filter design [4, 5, 6, 7, 8, 9, 10, 11, 12], oscillator design [13, 14], biological tissue modeling [15, 16, 17, 18, 19, 20, 21, 22, 23] as well as in automatic control [24, 25] have been introduced in the literature. Fractional-order differentiators and integrators offer attractive characteristics compared to their integer-order counterparts, including scaling of the time-constants as well as as phase difference between input and output which is ±απ/2, with (0 < α < 1). The straightforward way for implementing such blocks is the substitution of capacitors in the conventional (i.e. integer-order) structures by fractional-order capacitors, known also as Constant Phase Elements (CPEs). A fractional-order capacitor is characterized by two parameters {Ca , α}, where Cα is the pseudo-capacitance expressed in units of F arad/sec1−α and 0 < α < 1 is the (fractional) order [26]. The impedance of a CPE is described in the s-domain by (1), where the relation between pseudo-capacitance and the conventional capacitance (in F arad), can be expressed as in (2) Z(s) =

1  = Cα sα Cα ω α cos

1


απ 2

+ j sin

απ 2


 ,

(1)

Cα . (2) ω 1−α This direct substitution technique is not easily realizable, due to the absence of commercially available fractional-order elements despite the growing effort and clear progress towards this goal [27, 28, 29, 30]. Thus, appropriately configured RC networks [31] have been employed to approximate the behavior of fractional-order capacitors. However, this technique’s major drawback is that the complete RC network must be re-designed in order to change the approximated fractional capacitor’s pseudo-capacitance and/or its order. An alternative technique is the utilization of integer-order transfer functions, derived through an appropriate method, for approximating the integro-differential Laplacian operator (sα ) [19]. Discrete IC component implementations of fractional-order differentiators/integrators, where Operational Amplifiers (op-amps) or Current Feedback Operational Amplifiers (CFOAs) were used, have been presented in the literature, but they suffer from the absence of electronic tuning of their characteristics [32]. ∗ Corresponding

C=

author (e-mail:[email protected])

Preprint submitted to Microelectronics Journal

November 28, 2018

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Only integrated CMOS implementations [33, 34] offer such feature, as a result of employing, for example, the current-controlled small-signal transconductance parameter (gm ) of Operational Transconductance Amplifiers (OTAs) or Current-Mirrors (CMs). However, the CMOS implementations already reported in the literature suffer from increased complexity which limits the possibility of increasing the order of the underlying integer-order approximation. In order to overcome this obstacle, CMOS topologies which perform 2nd - and 5th -order approximations of fractional-order differentiators/integrators while offering significantly reduced circuit complexity, are presented in this paper. While some preliminary results have been reported in [35], here we develop a new systematic method for performing higher-order approximations of fractional-order differentiators/integrators and, in addition, validate the proposed design in application examples using both 2nd -order and 5th -order approximations. The paper is organized as follows: in Section 2, the topology of fractional-order differentiator/integrator, derived by implementing a 2nd -order transfer function that approximates the Laplacian operator, is demonstrated. Designs of fractional-order lowpass/highpass filters and the Leaky-Integrate-and-Fire Mihalas-Niebur neuron model are presented in Section 3. In Section 4, the implementation of a 5th -order transfer function that approximates the fractional Laplacian operator is demonstrated. As an application example, the realization of emulators of fractional-order capacitors and inductors is presented in Section 4.1. The behavior of all the proposed designs is verified in Cadence using the Design Kit provided by the Austria Mikro Systeme (AMS) 0.35µm CMOS process.

2. Realization of a fractional-order differentiator/integrator using a 2nd -order approximation The transfer function of a fractional-order differentiator/integrator is given by: r

(3)

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H(s) = (τ s)

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where r = α (0 < α < 1) is the order of the differentiator, while for the integrator r = −α (0 < α < 1). Also, the unity-gain frequency (ωo ) of the stage is defined as ωo = 1/τ , where (τ ) is a time-constant. r Using (3), the magnitude and phase frequency responses are given by the expressions |H(ω)| = (ω/ωo ) and 6 H(ω) = πr/2, respectively [36]. The transfer function in (3) can be approximated, around the unity-gain frequency, by appropriate integer-order transfer functions in order to be realizable by physical elements. An efficient tool for this purpose, in terms of circuit complexity and accuracy, is the 2nd -order expression derived using the Continued Fraction Expansion (CFE) method [37], which is given by the formula (4)  2  2 r +3r+2 s2 + τ1 ( r28−2r )s + τ12 2 −3r+2 r −3r+2 r ∼    . (τ s) = (4) 2 1 r 2 +3r+2 s2 + τ1 r28−2r −3r+2 s + τ 2 r 2 −3r+2 Figure 1 presents a proposed fractional-order differentiator/integrator topology implementation based on (4) [35]. The factors 2, Go , G1 , G2 in the figure indicate that the aspect ratio of the corresponding transistors are accordingly scaled with regards to the ratio of the associated diode-connected transistors with this factor. Routine analysis of the circuit leads to the realized intermediate transfer functions [38] (5)-(7) gm2 Go gm1 io1 C1 C2 = 2 2gm1 gm2 , iin s + C1 s + gm1 C1 C2

(5)

G1 2gm1 s io2 = 2 2gm1 C1 gm1 gm2 , iin s + C1 s + C1 C2

(6)

io3 = 2 iin s +

G2 s2 2gm1 gm1 gm2 C1 s + C1 C2

,

(7)

with gm1 and gm2 being the small-signal transconductances of MOS transistors Mp1 and Mn2, respectively.

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2

VDD

2G1

Go Mp5

Mp4 Mp3

iin

IB1

io3 VDD

VB

IB3

IB2

C1

io2

io1

Mn1 Mp1

Mp2

Mn4 Mn3

Mn5

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C2

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Figure 1: Realization of a fractional-order differentiator/integrator based on (4).

Performance factor number of transistors power dissipation

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Table 1: Comparison of the topology in Fig. 1 for r = ±0.5. (VDD is the power supply and Io is the bias current, respectively)

[11] 71 29.8 VDD Io

[33] 39 24.2 VDD Io

Proposed (Fig. 1) 21 15.2 VDD Io

Owing to the fact that the output current (iout ) is a sum of the intermediate currents (iout = io1 +io2 +io3 ), the realized transfer function takes the following form Go 1 G2 s2 + 2G iout τ1 s + τ1 τ2 = , iin s2 + τ21 s + τ11τ2

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H(s) ≡

(8)

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where τi = Ci /gmi (i = 1, 2) are the realized time-constants, and Gj (j = 0, 1, 2) are scaling factors implemented through an appropriate choice of the corresponding transistor aspect ratios. Compared to (4), the coefficients in (5)-(8) are as given by (9)-(10)  2    8 − 2r2 τ r − 3r + 2 τ1 = 2τ (9) , τ = 2 8 − 2r2 2 r2 + 3r + 2

G2 =

r2 + 3r + 2 , r2 − 3r + 2

G1 = 1,

Go =

r2 − 3r + 2 . r2 + 3r + 2

(10)

The topology of the fractional-order differentiator/integrator presented in Fig. 1 is compared with the corresponding topologies published in [11, 33], where 2nd -order approximation has been utilized. Assuming, just for comparison purposes, differentiation/integration stages of order 0.5 and the same bias current (Io ) for all stages, the derived results summarized in Table 1 show a significant reduction in both transistor count and power dissipation, and this conclusion is also valid for any other order of differentiation/integration.

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3. Application examples using the 2nd -order realization of the fractional-order differentiators/integrators

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3.1. Filter design example The Functional Block Diagram (FBD) of a fractional-order low/highpass filter, using a differentiator/integrator with unity gain frequency ωo = 1/τ as active core, is demonstrated in Fig. 2. In the case of r = α, then the highpass filter function given by (11) is implemented, while when r = −α the transfer function of the realized lowpass filter is given by (12). The desirable inverted output is also available, using an extra current-mirror at the output, as depicted in the full circuitry shown in Fig. 3. α

(τ s) iout , = α iin (τ s) + 1 iout 1 HLP (s) ≡ . = α iin (τ s) + 1

HHP (s) ≡

(11) (12)

ω ωo

2α

+2



HHP (ω) = απ/2 − tan−1  

ω ωo

α

cos

α

ω ωo α

,

απ 2

sin

απ 2

απ 2

cos







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ω ωo

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+2  

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HLP (ω) = − tan−1  

ω ωo



ω ωo

α

α

ω ωo α

cos

sin

cos

απ 2

απ 2

απ 2




(13)

+1




 ,

(14)

,

(15)

+1

1

|HLP (jω)| = r

6

ω ωo





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The magnitude and phase responses in the case of the fractional-order high-pass filter are given by the expressions in (13)-(14), while the corresponding responses of the fractional-order low-pass filter are given by (15)-(16) [11]  







+1  .

(16)

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The expressions of the half-power frequency (ωh ) (i.e. the frequency where a drop of the gain equal to 3dB from its maximum value is observed) are given by (17) and (18), respectively r

ωh,HP

= ωo

ωh,LP

= ωo

1 + cos2

 απ  2

+ cos

 απ 1/α

(17)

2

r  απ 1/α  απ  1 + cos2 − cos . 2 2

(18)

Also, the values of phase at half-power frequency are calculated by the following expressions

HHP (ω) |ω=ωh

6

6

HLP (ω) |ω=ωh

sin απ απ 2 = − tan−1 q 2 1 + cos2 −1

= − tan

iin


(19) απ 2





sin απ 2
q 2 cos απ + 1 + cos2 2

απ 2


.

iout

s

 
1s

r

iout

Figure 2: FBD of the low/highpass filter using a FO differentiator/integrator

(20)

Filter design example

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Figure 3: Lowpass/highpass fractional-order filter using the building block in Fig.1

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Filter design example

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Table 2: Aspect ratios of the diode-connected MOS transistors in Fig. 3.

Aspect ratio (µm/µm) 20/2 10/2 2/2 20/2 80/0.8 40/2 20/2 20/2

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Transistor M n1 − M n2 M n3 − M n5 M nb1 − M nb2 M p1 − M p2 M p3 M p4 M p5 M pb1

Table 3: Values of dc bias currents and their scaling factors for the topology in Fig. 3. α = 0.5

44 103 400 50 0.398 1 2.513

34 68 400 50 0.2 1 5

α = 0.7

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α = 0.3

26 35 400 50 0.085 1 11.77

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Parameter IB1 (pA) IB2 (pA) IB3 (pA) Io (pA) G2 G1 Go

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The behavior of the designed filters was evaluated, in the case of the fractional-order low-pass filter (i.e. r = −α) , using the Cadence IC design suite and the Design Kit from Austria Mikro Systeme (AMS) 0.35µm CMOS process. The time-constant was set as τ = 20ms, while the simulated orders were α = {0.3, 0.5, 0.7}. The power supply voltages were VDD = 1.5V , VSS = 0V , and VB = 0.4V and the capacitor values were C1 = 20pF and C2 = 200pF . Considering that the MOS transistors operate in the subthreshold region, then the transconductances gm1 and gm2 are expressed as: gm1 = IB1 /nVT and gm2 = IB2 /nVT , where IB1 , IB2 are the corresponding bias currents, n is the subthreshold factor of a MOS transistor (1 < n < 2), and VT is the thermal voltage (26 mV at 27o C). Therefore, the timeconstants are electronically tunable through these dc bias currents offering the attractive benefit of the adjustable characteristics of the filters. The aspect ratios of the diode-connected MOS transistors are provided in Table 2, while in Table 3 the values of the bias currents as well as their scaling factors, are summarized. The obtained frequency responses for both the gain and the phase of the fractional-order low-pass filter, along with those theoretically predicted using (15) and (16) (given by dashed lines), are provided by the plots in Fig. 4. The deviations observed above 20Hz are caused by the limitations of the employed 2nd -order approximation [32]. The most important frequency characteristics are summarized in Table 4, with the corresponding theoretically predicted values given in parentheses. Table 4: Simulated frequency characteristics of the LPF.

Parameter

half-power frequency fh (Hz) phase at half-power frequency (deg)

α = 0.3

α = 0.5

α = 0.7

0.75(0.6) −7.5(−8.3)

2.6(2.1) −16.5(−15)

4.6(4.3) −24.8(−23.9)

The behavior of the proposed topology in terms of the effect of MOS transistors parameters and process variations has been evaluated using the Monte-Carlo analysis tool for N = 100 runs. The corresponding statistical histograms are provided in Fig.A1 of the Appendix. The standard deviation in the half-power frequency and phase at this frequency are measured to be 0.15Hz and 0.47o , respectively.

Filter design example

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approximation = 0.3 simulation = 0.5 simulation = 0.7 simulation

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-15

-20 10-1

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Freq (Hz) (b) Figure 4: Simulated frequency responses versus theoretical responses of the FO low-pass filter (a) gain, and (b) phase.

3.2

Implementation of the Leaky-Integrate-and-Fire Mihalas-Niebur model

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3.2. Implementation of the Leaky-Integrate-and-Fire Mihalas-Niebur model

j = 1, 2, ..., N

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The first mathematical model of neural dynamics was proposed by Hodgkin and Huxley [39], which was versatile to several types of human behaviors. However, this model suffers from increased circuit complexity, as a large number of parameters need to be defined. In order to overcome this obstacle, another model known as the generalized Leaky-Integrate-and-Fire model is often used. This model is less complex and describes the fundamental properties of neurons. The Izhikevich and Mihalas–Niebur models belong to this category [40, 41] with the latter offering the benefit of biophysical interpretation of the employed state variables as well as modularity with minimal interference between the state variables. According to the Mihalas–Niebur model [41], the fundamental variables, describing the state of the neuron, are the following: the membrane voltage Vmem (Vmem0 is the membrane resting potential), the instantaneous threshold θ (θ0 is the resting threshold), and an arbitrary number N of internal currents Ij . Considering their time-domain behavior, the membrane voltage depends on the internal currents, the instantaneous threshold depends on the membrane voltage, while the internal currents are independent of the other variables, as they are exponentially decaying. Assuming an excitatory input current Iex , the fundamental equations of the neural dynamics are given by (21)-(23)

i X dVmem (t) 1 h = Iex (t) + Ij (t) − GVmem (t) , dt Cmem

(21) (22)

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dθ (t) = aVmem (t) − bθ (t) , (23) dt where Cmem P is the capacitance of the employed membrane, and a, b, G are model associated parameters. Choosing Ij = 0 and considering the threshold θ being stable over time, then by transposing the expression in (22) into the s-domain and representing it in a manner suitable for current-mode implementation [42], the Mihalas–Niebur model could be described by the following equation Iex + Imem0 , τmem s + 1

(24)

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where variables Imem and Imem0 in (24) are the membrane voltage and resting potential related currents, respectively, and τmem ≡ Cmem /G is a time-constant associated with the time-domain behavior of the membrane with a typical value equal to 20ms. [43] Inspecting the expression in (24), it is clearthat it can be implemented by an appropriately configured low-pass stage. The classical way for this type of implementation is to use an integer-order low-pass filter, realizing the above transfer function. However, fractional-order dynamics have recently been shown to be important for modeling neural activity [44]. Therefore, the Mihalas–Niebur model can be generalized to the form Imem =

Iex + Imem0 , (τmem s)α + 1

(25)

which can be realized through the proposed fractional-order low-pass filter, described by the transfer function in (12) and presented through the circuit structure in Fig. 3, having a time-constant equal to the time-constant of the membrane (τmem ). Let us consider the plot in Fig. 5, where the step responses of a lowpass filter with τ = 20ms and orders α = {0.3, 0.5, 0.7} are provided. It is obvious that as the order increases, the response tends faster towards the threshold activating the reset mechanism and, hence, starting again the cycle of operation. Thus, it is expected that the spiking frequency will increase as the order of the filter is also increased. The implementation of this model also requires a comparator which is shown in Fig. 6. Its operation is described as follows: if iIN > 0, then υOU T = VDD,DIG , whereas if iIN < 0, then υOU T = 0V . The full implementation of the Leaky-Integrate-and-Fire Mihalas-Niebur neuron model with constant threshold is presented in Fig. 7, where a reset stage is employed for updating the value of Imem . In order to evaluate the behavior of the presented circuit, the time-constant of the topology was set to be τ = 20ms, i.e. equal to the time-constant of the membrane, while the simulated orders were α = {0.3, 0.5, 0.7}. The values of the bias currents as well as their scaling factors have been already provided in Table 3. The aspect ratios of the MOS transistors of the comparator, biased at VDD, DIG = 1V , and the reset stage are provided in Table 5. For an input pulse, with amplitude 100pA, as the excitation

3.2

Implementation of the Leaky-Integrate-and-Fire Mihalas-Niebur model

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1 0.9 0.8

0.6 alpha=0.3 alpha=0.5 alpha=0.7 alpha=1

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output

0.7

0.5 0.4 0.3 0.2

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Figure 5: Step response of a fractional lowpass filter of order α = {0.3, 0.5, 0.7} compared to the integer-order filter.

VDD,DIG

Mnc1

iIN

Mpc3

υOUT

Mnc2

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Mpc2

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Figure 6: Comparator circuit used for implementing the fractional-order Mihalas-Niebur model.

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input current Iex and threshold Iθ = 50pA, the derived waveforms that correspond to a tonic spiking for the three different orders are depicted in Fig. 8, where the waveform that corresponds to the 1st -order lowpass filter is also provided. It must be mentioned at this point that, owing to the lowpass filter operation, the input signal in the comparator, which is the output signal of the lowpass filter, will be less than or equal to the input excitation. Therefore, the threshold current must be smaller than the input signal in order for the comparator to be functional. Obviously, there is a freedom of choice of the value of this current, and the case of 50pA is presented here for demonstration purposes. Inspecting these plots it is concluded that as the order (α) increases, indeed the frequency of the derived spikes also increases. Table 5: Aspect ratios of the MOS transistors of the comparator and the reset stages in Fig. 7.

Transistor Mnc1 Mnc2 − Mnc3 Mpc1 Mpc2 − Mpc3 Mnr1 − Mnr3

Aspect ratio (µm/µm) 0.4/0.35 0.5/0.35 0.4/0.35 1/0.35 80/20

Implementation of the Leaky-Integrate-and-Fire Mihalas-Niebur model

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Figure 7: Full circuitry of the Leaky-Integrate-and-Fire Mihalas-Niebur model.

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Implementation of the Leaky-Integrate-and-Fire Mihalas-Niebur model

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100 input threshold imem (α=0.3) imem (α=1)

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I (pA)

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time (ms)

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(b)

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input threshold imem (α=0.7) imem (α=1)

I (pA)

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time (ms)

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(c) Figure 8: Output waveforms of the membrane current for (a) α = 0.3, (b) α = 0.5, (c) α = 0.7, compared with that of the corresponding integer-order (α = 1)

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ACCEPTED MANUSCRIPT 4. Fractional-order differentiator/integrator using a 5th -order approximation

Although the 2nd -order CFE approximation offers circuit simplicity, its accuracy for an error in phase less than 10%, is restricted to the range [fo /10, 10fo ], where fo is the center frequency of the CFE approximation. In order to extend this frequency range, a higher-order approximation must be utilized. The integer-order transfer function in the case of a 5th -order CFE approximation is given by

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A5 s5 + A4 s4 + A3 s3 + A2 s2 + A1 s + Ao . (26) (τ s)r ∼ = B5 s5 + B4 s4 + B3 s3 + B2 s2 + B1 s + Bo The values of coefficients Ai (i = 0, 1, 2, ... 5) and Bi (i = 0, 1, 2, ... 5) in (26) are summarized in Table 6. The transfer function in (26) can be decomposed into a product of 2nd and 1st -order sections. Assuming Table 6: Coefficients of (a) numerator and (b) denominator of the transfer function (26) for approximating the fractionalorder Laplacian operator

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(a)

Coefficient

Expression

−r 5 −15r 4 −85r 3 −225r 2 −274r−120

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5r +45r +5r −1005r −3250r−3000 r 5 −15r 4 +85r 3 −225r 2 +274r−120

1 τ

A4



1 τ2

A3

−10r 5 −30r 4 +410r 3 +1230r 2 −4000r−12000 r 5 −15r 4 +85r 3 −225r 2 +274r−120



1 τ3

A2 Ao

10r 5 −30r 4 −410r 3 +1230r 2 +4000r−12000 r 5 −15r 4 +85r 3 −225r 2 +274r−120



1 τ4

A1



−5r 5 +45r 4 −5r 3 −1005r 2 +3250r−3000 r 5 −15r 4 +85r 3 −225r 2 +274r−120 1 τ5







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Coefficient B5

1 τ

B4

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B1 Bo

1 τ2

1 τ3

1 





Expression

−5r 5 +45r 4 −5r 3 −1005r 2 +3250r−3000 r 5 −15r 4 +85r 3 −225r 2 +274r−120



10r 5 −30r 4 −410r 3 +1230r 2 +4000r−12000 r 5 −15r 4 +85r 3 −225r 2 +274r−120



−10r 5 −30r 4 +410r 3 +1230r 2 −4000r−12000 r 5 −15r 4 +85r 3 −225r 2 +274r−120

1 τ4 1 τ5



5r 5 +45r 4 +5r 3 −1005r 2 −3250r−3000 r 5 −15r 4 +85r 3 −225r 2 +274r−120



−r 5 −15r 4 −85r 3 −225r 2 −274r−120 r 5 −15r 4 +85r 3 −225r 2 +274r−120







that the poles (p1 , p2 ...p5 ) are poles with descending order of their quality factor and (z1 , z2 ... z5 ) are their associated nearest zeros [45], then the expression in (26) can be written as: (s − z1 ) · (s − z2 ) · (s − z3 ) · (s − z4 ) · (s − z5 ) (τ s)r ∼ , =K (s − p1 ) · (s − p2 ) · (s − p3 ) · (s − p4 ) · (s − p5 )

(27)

where K = A5 /B5 = A5 . This can alternatively be expressed as a product of two 2nd -order transfer functions and one 1st -order (bilinear) transfer function in the form       F2 s2 + F1 s + Fo L1 s + Lo D2 s2 + D1 s + Do · · . (28) (τ s)r ∼ = s2 + E1 s + Eo s2 + H1 s + Ho s + Mo The 2nd -order transfer functions in (28) can be implemented by the topology in Fig. 1, while the 1st order (bilinear) transfer function can be realized by the topology depicted in Fig. 9, which is actually a simplified version of that in Fig. 1. Its realized transfer function is given by the following expression H(s) ≡

o G1 s + G iout 2τ = 1 iin s + 2τ

(29)

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2G1

2

Go

Mp3

Mp4

iin

IB1

IB2

io2

io1 Mp2

Mn3 Mn2

C VSS

2G1

iout

Mn1

Go

RI PT

Mp1

VB

SC

Figure 9: Implementation of a 1st -order bilinear transfer function

G2a s2 +

iout = H(s) ≡ iin

2G1a Goa τ1 s + τ1 τ2 2 s + τ11τ2 τ1

!

G2b s2 +

·

s2 +

D

s2 +

M AN U

where the time constant is given by the expression: τ = C/gm , and gm is the small-signal transconductance of the transistor Mn1. Bilinear only transfer functions have been also used for approximating the behavior of fractional-order capacitors in [46, 47, 48]. The overall proposed topology of the decomposed 5th -order transfer function is demonstrated in Fig. 10, where it is readily obtained that the number of required MOS transistors and dc current sources is equal to 57 and 8, respectively. Using (8) and (29), the derived transfer function is given by the expression in (30) Gob 2G1b τ3 s + τ3 τ4 2 1 τ3 s + τ3 τ4

! ·

Go 2τ5 1 2τ5

G1 s + s+

! ,

(30)

TE

where τi = Ci /gmi (i = 1, 2, ... 5) are time-constants, with Ci (i = 1, 2, ... 5) being the passive capacitors, and gmi (i = 1, 2, ... 5) being the small-signal transconductances of the transistors Mp1a, Mn2a, Mp1b, Mn2b, and Mn1 respectively, and Gja,b (j = 0, 1, 2), Gk (k = 0, 1) being the scaling factors. Comparing the coefficients of (30) and (28), the derived design equations are given by (31) 2 , E1

τ2 =

EP

τ1 =

AC C

G2a = D2 ,

E1 , 2Eo

G1a =

Gob =

D1 , E1 Fo , Ho

τ3 =

2 , H1

Goa =

Do , Eo

G1 = L1 ,

τ4 =

H1 , 2Ho

G2b = F2 ,

Go =

τ5 =

1 2Mo

G1b =

F1 , H1

(31)

Lo . Mo

The behavior of the proposed fractional-order differentiator/integrator in Fig. 10, was evaluated setting fo = 10kHz, while the simulated orders were r = {±0.3, ±0.5, ±0.7}. The values of the coefficients in (28), that correspond to this center frequency are summarized in Table 7. The power supply voltages were VDD = −VSS = 1.5V , and VB = 0.2V . The capacitor values for the differentiator were: C1 = 80pF , C2 = 330pF , C3 = 2nF , C4 = 8nF and C5 = 6nF , while for the integrator the only value that changes is C5 = 24nF . Considering, now, that the MOS transistors operate q in the strong inversion region, their transconductances (gm1 ) and (gm2 ) are expressed as: gm1 = 2Kp (W/L)M p1 IB1 and gm2 = p 2Kn (W/L)M n2 IB2 , where Kp and Kn are the transconductance factors of Mp1 and Mn2, respectively, and IB1 , IB2 are the corresponding bias currents. Therefore, the time-constants are electronically tunable through the dc bias currents offering adjustable characteristics of the proposed differentiator/integrator topology. The MOS transistor aspect ratios are provided in Table 8. Using (31) and Table 7, the calculated values of the bias currents as well as their scaling factors, for the differentiator and integrator (between parentheses), are summarized in Table 9.

SC G2a

VB

2G1a

VDD

Mp4a

IB1

Mp1a

Mn4a Mn3a

VSS

2

C1

Mp2a

second-order section

Mn1a

Mp3a

M AN U Go

iout1

IB5

VDD

2G1a

C2

Mp5a

IB2

Goa

Goa

Mn2a

D

RI PT Mp4

IB7

Mn1

Mn5a

G2a

IB5

VDD

iout2

Mn5b

G2b

G2b

TE

2

iin

Mp2

first-order section VDD Mp3

IB6

Mp1

C5 Go

VB

2G1b

2G1b

VDD Mp4b

IB3

Mp1b

Mn4b Mn3b

VSS

2

C3

Mp2b

second-order section

Mp3b

Mn1b

EP

VB Mn3 Mn2

VSS

AC C

2G1

2G1

C4

Mp5b

IB4

Gob

Mn2b

Gob

iout

Figure 10: Full circuitry of the proposed 5th -order approximation of a fractional-order differentiator/integrator

14

ACCEPTED MANUSCRIPT

15

ACCEPTED MANUSCRIPT Table 7: Values of the coefficients of the polynomials in (28) atfo = 10kHz.

r = 0.3 (−0.3)

r = 0.5 (−0.5)

r = 0.7 (−0.7)

D2 D1 Do E1 Eo F2 F1 Fo H1 Ho L1 Lo Mo

4 (0.25) 4.3E+06 (5.66E+05) 6.19E+11 (1.3E+11) 2.28E+06 (1.07E+06) 5.22E+11 (1.54E+11) 1 (1) 6.82E+04 (9.75E+04) 8.08E+08 (1.71E+09) 9.75E+04 (6.82E+04) 1.71E+09 (8.08E+08) 1 (1) 1956 (4419) 4419 (1956)

11 (0.09) 9.69E+06 (3.04E+05) 1.22E+12 (8.32E+10) 3.34E+06 (8.81E+05) 9.16E+11 (1.11E+11) 1 (1) 6.03E+04 (1.1E+05) 6.18E+08 (2.17E+09) 1.1E+05 (6.03E+04) 2.17E+09 (6.18E+08) 1 (1) 1299 (5417) 5417 (1299)

35.74 (0.17) 2.65E+07 (9.93E+05) 2.92E+12 (3.31E+11) 5.84E+06 (7.41E+05) 1.95E+12 (8.17E+10) 1 (0.17) 5.3E+04 (2.1E+04) 4.66E+08 (4.68E+08) 1.23E+05 (5.3E+04) 2.76E+09 (4.66E+08) 1 (1) 719.9 (6519) 6519 (719.9)

M AN U

SC

RI PT

Coefficient

Table 8: Aspect ratios of the MOS transistors in Fig. 10.

TE

D

Transistor M n1a − M n5a M n1b − M n5b M p1a − M p2a and M p1b − M p2b M p3a, M p3b M p4a − M p5a and M p4b − M p5b M n1 M n2 − M n3 M p1 − M p2 M p3 M p4

Aspect ratio (µm/µm) 10/2 10/2 20/2 4/1 10/2 10/2 5/1 5/0.5 5/2 10/2

EP

Table 9: Values of dc bias currents and their scaling factors for the topology in Fig. 10 for implementing fractional order differentiators (integrators).

AC C

Parameter IB1 (µA) IB2 (µA) IB3 (µA) IB4 (µA) IB5 (µA) IB6 (µA) IB7 (µA) G2a G1a Goa G2b G1b Gob G1 Go

r = 0.3 (−0.3)

r = 0.5 (−0.5)

r = 0.7 (−0.7)

9 (2) 15 (5.3) 8.2 (4) 46.3 (21) 5 (30) 2 (5) 2 (5.2) 4(0.25) 1.9(0.53) 1.2(0.84) 1(1) 0.7(1.43) 0.47(2.1) 1(1) 0.44(2.26)

16 (1.3) 19 (4) 10 (3) 59 (16) 5 (30) 2 (5) 5 (4) 11(0.1) 2.9(0.3) 1.3(0.7) 1(1) 0.55(1.8) 0.3(3.5) 1(1) 0.23(4)

40 (1) 26(3) 13(3) 75(12) 5(30) 2(5) 7(1) 36(0.17) 4.5(1.3) 1.5(4) 1(0.17) 0.4(0.4) 0.18(1) 1(1) 0.1(9)

The simulated frequency responses are demonstrated in Fig.11, where an error less than 10% in phase is achieved in the range (270Hz, 310kHz) for the differentiator and (260Hz, 310kHz) for the integrator.

16

30 approximation = 0.3 simulation = 0.5 simulation = 0.7 simulation

Integrator

SC

20 10 0 -10 -20 Differentiator -30 10

3

M AN U

Gain (dB)

RI PT

ACCEPTED MANUSCRIPT

10

4

10

5

Freq (Hz)

D

(a)

100

approximation = 0.3 simulation

= 0.5 simulation = 0.7 simulation

EP

Phase (deg)

50

TE

Differentiator

AC C

0

-50

Integrator

-100

103

104

105

Freq (Hz)

(b)

Figure 11: Frequency responses of the 5th -order differentiator/integrator (a) gain and (b) phase.

17

ACCEPTED MANUSCRIPT 1.5 Input

Differentiator

1

Integrator

0 -0.5 -1

0.55

0.6

0.65

Time (ms)

0.7

0.75

0.8

SC

-1.5 0.5

RI PT

I ( A)

0.5

M AN U

Figure 12: Time-domain output waveforms for the 5th -order differentiator/integrator (r = ±0.5) stimulated by a (10kHz, 1µA) input current

Table 10: Comparison results of the topology in Fig.10 for r = ±0.5.

Topology

Proposed (Fig.10)

131 123.7 VDD Io

57 44.7 VDD Io

D

number of transistors power dissipation

[25]

AC C

EP

TE

Evidently, the frequency range in which the CFE method is valid, in the case of 5th -order topology, is wider than the corresponding of 2nd -order as expected according [32]. The time-domain behavior of the proposed differentiator/integrator topology in Fig. 10 is evaluated through its stimulation by a sinusoidal signal with 10kHz frequency and 1µA amplitude. The simulated output waveforms are shown in Fig. 12, where the time shift (∆t) between the peaks of the input and output waveforms is 12.6µs for the differentiator and −13.1µs for the integrator. Using the formula: φ = 360o · (∆t/T ) for calculating the phase shift and considering that T = 100µs, the calculated values are 45.4o and −47.2o , close to the theoretically predicted values +45o and −45o , respectively. The electronic tuning capability of the proposed topology is demonstrated by the gain plots in Fig. 13, for (IB1 , IB2 , IB3 , IB4 , IB7 ) equal to{(8, 9, 5, 30, 2.5) , (16, 19, 10, 59, 5) , (32, 38, 20, 118, 10)} µA in the case of differentiator and {(0.8, 2, 1.5, 8, 2) , (1.3, 4, 3, 16, 4) , (2.6, 8, 6, 32, 8)}µA in the case of integrator. The corresponding unity-gain frequencies are {6.9, 9.8, 15.7}kHz for the differentiator, while the corresponding values for the integrator are {6.3, 10, 13.8}kHz. These are the limits of the tuning range at the given bias scheme, in order for the MOS transistors to remain biased in the saturation region. Obviously, increasing the bias voltages and/or MOS transistors aspect ratios, this range can be expanded at the expense of power dissipation and/or occupied silicon area. The behavior of the proposed topology in terms of the effect of MOS transistors parameters process variations was evaluated using the Monte-Carlo analysis tool, for N = 100 runs . The corresponding statistical histograms are provided in Figs. A2 and A3 of the Appendix. In the case of a differentiator (r = 0.7), the standard deviation in the gain and phase were measured to be 0.36dB and 0.4o respectively. The corresponding values of standard deviation in the case of the integrator (r = −0.3) were 0.18dB and 0.2o , respectively. Therefore, the proposed topology in Fig. 10 offers reasonable sensitivity characteristics. The topology in Fig. 10 is compared with the corresponding topology introduced in [25], where multifeedback integer-order filter structures implemented using OTAs as active elements have been used for performing 5th -order approximation of fractional-order differentiators/integrators according to the Oustaloup approximation method. Assuming that the order is α = 0.5 and Io is the common bias current of all stages, the derived results are given in Table 10 from which the significant reduction in terms of the number of transistors and the power dissipation is clear.

4.1

Application example

ACCEPTED MANUSCRIPT

18

20 Integrator

fo/ 2

15

fo fo 2

5 0

RI PT

Gain (dB)

10

-5 -10 -15

Differentiator 103

104

105

Freq (Hz)

SC

-20

M AN U

Figure 13: Electronic tuning capability of the 5th -order differentiator/integrator (r = ±0.5)

4.1. Application example

As an application of the proposed 5th -order differentiator/integrator, the implementation of a fractionalorder capacitor (CPE) or fractional-order inductor (FI) emulator is considered, based on the functional block diagram depicted in Fig. 14. The realized equivalent impedance Zeq ≡ υ/i, is given by the expression in (32) Zeq,CP E,F I (s) =

1 r, gm,V I · (τ s)

(32)

TE

D

where r = α (0 < α < 1) is the order of the differentiator, resulting in a CPE emulator, while for the integrator r = −α (0 < α < 1), resulting in a FI emulator. The equations for the pseudo-capacitance (in F arad/sec1−α ) and the pseudo-inductance (in Henry/sec1−α ) of the CPE and the FI emulator, respectively, are given by (33) Lα =

τα gm,V I

.

(33)

EP

Cα = gm,V I · τ α ,

AC C

De-normalizing at the unity-gain frequency ωo , the capacitance and the inductance take the forms of (34) gm, I 1 C = α V1−α , L= . (34) ωo · ω gm,V I · ωoα · ω 1−α Selecting ω = ωo in (34), the values of the de-normalized effective capacitance and inductance take the forms gm,V I 1 , L= . (35) C= ωo gm,V I · ωo 

i



i






i



gm,VI

Hs=s r

Figure 14: FBD for the emulation of fractional-order capacitor/inductor [23, 34].

4.1

Application example

19

ACCEPTED MANUSCRIPT VDD Mpb2

Mpb1

Ibias

i

RI PT

Mnb2

Mnb1



Ibias VSS

SC

Figure 15: Voltage-to-current (V /I) converter.

Table 11: Simulated frequency characteristics of the CPE emulator at 10kHz

Z (kΩ) P hase (deg)

α = 0.3

α = 0.5

α = 0.7

M AN U

Parameter

32.3(31.2) −25.5(−27)

30.1(31.2) −42.2(−45)

32.3(31.2) −60.1(−63)

D

According to (35), the impedance at the unity gain frequency is Z(ωo ) = 1/gm,V I and, therefore, the transconductance of the V /I converter (gm,V I ) determines the impedance of the emulated element at this frequency. A simple structure for implementing the V /I converter is depicted in Fig. 15. Considering that the MOS transistors operate in the strong inversion region, the expression for the small-signal p transconductance of the implemented V /I converter is given by gm,V I = 2Kn (W/L) Ibias where W and L are the width and the length of the transistor Mnb1, while Ibias is the dc bias current.

AC C

EP

TE

The performance of the proposed CPE/FI emulator was evaluated through the implementation of CPEs with pseudo-capacitances {1.1µF/sec0.7 , 125.3nF/sec0.5 , 13.8nF/sec0.3 }, and FIs with pseudoinductances {1.1kH/sec0.7 , 125.3H/sec0.5 , 13.8H/sec0.3 }. The topology in Fig. 10, with the same bias conditions and transistor aspect ratios given in Table 8 utilized. The aspect ratio of all the MOS transistors in Fig. 15 is 2µm/2µm, while the value for Ibias is equal to 3µA. The simulated impedance magnitude and phase responses for the CPE emulator are provided in Fig. 16, where the corresponding theoretically predicted plots are also given by dashed lines. The simulated impedance magnitude and phase values of CPEs at 10kHz are summarized in Table 11, where the corresponding theoretical values are also given between parentheses. For the FI emulator, the obtained impedance magnitude and phase responses along with the corresponding theoretical plots are also provided in Fig. 16, while the magnitude and phase values of the impedance at 10kHz are provided in Table 12. The time-domain behavior of the emulator has been evaluated through its stimulation by a 100mVpp sinusoidal input voltage with frequency 10kHz. The simulated input-output waveforms for the CPE emulator (r = 0.5) are demonstrated in Fig. 17a, while the corresponding plots for the FI emulator (r = −0.5) are depicted in Fig. 17b. Finally, the sensitivity performance of the emulator was simulated using the Monte-Carlo analysis in Cadence, with the corresponding statistical histograms provided in Figs. A4 and A5 in the Appendix. For the CPE realizations, the standard deviation of the magnitude and phase were 1.2kΩ and 0.2o , respectively while in the case of FI, the corresponding values were 1.6kΩ and 0.5o . Table 12: Simulated frequency characteristics of the FI emulator at 10kHz

Parameter Z (kΩ) P hase (deg)

α = 0.3

α = 0.5

α = 0.7

30.3(31.2) 26.6(27)

32.5(31.2) 42.3(45)

31.8(31.2) 62.3(63)

Application example

20

ACCEPTED MANUSCRIPT

500 ideal = 0.3 simulation = 0.5 simulation = 0.7 simulation

400

FI

SC

CPE

RI PT

4.1

Z (k )

300

M AN U

200

100

0

103

104

105

Freq (Hz)

D

(a)

FI

= 0.5 simulation = 0.7 simulation

EP

ideal = 0.3 simulation

0

AC C

Phase (deg)

50

TE

100

-50

CPE

-100

103

104

105

Freq (Hz) (b) Figure 16: Simulation results of impedance (a) magnitude, and (b) phase of the implemented CPE/FI emulator

0

-50 0.5

0.55

0.6

0.65

0.7

0.75

-2 0.8

Time (ms)

50

2

0

0

-50 0.5

RI PT

0

V (mV)

2

I ( A)

V (mV)

50

0.55

0.6

0.65

0.7

0.75

I ( A)

21

ACCEPTED MANUSCRIPT

-2 0.8

Time (ms)

SC

(a)

(b)

Figure 17: Time-domain behavior of the emulator for a 10kHz, 100mVpp input voltage (a) CPE , and (b) FI (r = ±0.5)

M AN U

5. Conclusions

D

Application design examples including the realization of fractional-order filters, a fractional-order neuron model and emulators of fractional-order capacitor/inductor have been demonstrated and verified in this work. These applications rely on optimized and reduced complexity fractional-order differentiator/integrator stages that are also electronically tunable. Compared to already published CMOS structures, there is a significant reduction in the number of transistor employed which facilitates the move towards higher-order approximations of the fractional-order Laplacian operator. The proposed differentiator/integrator stages could be also utilized and in other applications, particularly P I λ Dβ controllers.

TE

Acknowledgment

AC C

EP

This work is supported by the General Secretariat for Research and Technology (GSRT) and the Hellenic Foundation for Research and Innovation (HFRI). This article is based upon work from COST Action CA15225, a network supported by COST (European Cooperation in Science and Technology).

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ACCEPTED MANUSCRIPT Appendix

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Figure A1: Monte-Carlo analysis histograms of the (a) half-power frequency, and (b) phase at half-power frequency of the LP filter in Fig.3.

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Figure A2: Monte-Carlo analysis histograms of the (a) gain, and (b) phase at unity-gain frequency of the differentiator (r = 0.7) in Fig.10.

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Figure A3: Monte-Carlo analysis histograms of the (a) gain, and (b) phase at unity-gain frequency of the integrator (r = −0.3) in Fig.10.

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Figure A5: Monte-Carlo analysis histograms of the (a) impedance, and (b) phase of emulated FI (order 0.5) at fo = 10kHz.