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Libraries and compilers for CMOS IC design
Newsfile to achieve a simple two-chip design. For increased performance, the device implements its own buffer management scheme to process receive and transmit packets in system memory. Features include a 32 bit nonmultiplexed address and data bus, two independent 32 byte transmit and receive FIFOs, 32 bit general purpose timer, full duplex Ioopback diagnostics and integrated support for bridge and repeater applications. (National Semiconductor (UK) Ltd, The Maple, Kembrey Park, Swindon, Wiltshire SN2 6UT, UK. Tel: +44 (0) 793 614141) Gate array family extended Four devices have been added to Hitachi's HG62G family of gate arrays, considerably extending the range of gate and pin-counts available. For larger designs, three devices added to the top of the range provide gate counts of 54 200; 51 100 and 70 500 with I/O capabilities of 264, 288 and 336 pads respectively. For applications requiring a smaller gate count, such as glue logic in systems design, a 10000 gate device has also been introduced, with 136 I/O pads. The company's HG62G series is its fastest gate array family. Fabricated in 0.8pm CMOS, it offers high speed operation (down to 0.3 ns for an internal two-input power NAND gate and 1.8 ns for an output gate, into 50 pF). Its staggered I/O pad layout provides a high pin/gate ratio, and lower cost per pin. Devices qualified for operation from 5.5 V down to 2.7 V are available, and its low power consumption makes it suitable for battery powered applications. (Hitachi Europe Ltd, Electronics Components Division, Whitebrook Park, Lower Cookham Road, Maidenhead, Berks, SL6 8YA, UK. Tel: +44 (0) 628 585000) Fast cache for 486 and P5 systems The latest 32k x 9 CacheRAM from IDT provides zero wait-state operation for 50 MHz Intel 486 and 67 MHz Intel P5 systems. Packaged in a 32-pin BiCMOS SOL with clock-to-
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data timing of 10.5 ns, self-timed write and on-board burst counter, the IDT71B589 is claimed to be the fastest and smallest high-performance cache. Using the small footprint 32-pin SOJ package instead of 44-pin PLCC solutions saves approximately 33% of board space and enhances electrical characteristics. In addition, the company has tailored those parameters critical to 50MHz and 67 MHz designs, resulting in a short address setup time (1 ns) and a fast output enable time (5 ns). A 10 ns 8k × 8 companion cache tag, the IDT71 B74, is also available, in 10.5 ns, 12 ns and 14 ns versions. IDT has also released the IDT71589SA, a low cost version of its original 486 CacheRAM. The IDT71589SA provides greatly improved performance in 25 and 33 MHz Intel 486 SX/DX/DX2 and OverDrive systems. The 24 ns CacheRAM is housed in the same 32-pin SOJ package as the IDT71B589 with timing parameters tailored for slower clock speeds. Three other high-density modules incorporating the IDT71589 are available including the IDT7MP6086 (128kB plus parity in a 72-lead SIMM), the IDT7MP6085 (128kB with parity in an 80-lead SIMM) and the IDT7MP6087 (256 kB with parity in an 80-lead SIMM). (Integrated Device Technology Europe, 21 The Crescent, Leatherhead, Surrey, KT22 8DY, UK. Tel: +44 (0) 372 377375)
Libraries and compilers for CMOS IC design The Liberty Series, a family of physical layout libraries and compilers for the design of CMOS integrated circuits, has been announced by Compass Design Automation. The series is claimed to be the first offering of general-purpose libraries and compilers from an electronic design automation (EDA) company that provides foundry flexibility and support for multiple design environments. Designers have the flexibility to select the foundry and CMOS process of their choice for chip
production. In addition to being tightly integrated with Compass'ASIC Navigator top-down design system, the libraries can be used with a variety of design tools and environments, including those from Cadence Design Systems, GenRad, Mentor Graphics, Synopsys and Zycad. IC design productivity and timeto-market is improved by eliminating the need to create low-level design elements and layout for different designs and foundry processes. The series enables chip designers to focus on designing the high-level functions that ultimately distinguish their products in the marketplace rather than on the development of basic building blocks. Fully portable gate array and standard cell libraries are included as well as RAM and multiplier compilers and Compass' optimized Datapath Compiler. The libraries have in-depth functionality. For example, the high performance gate array library contains up to 265 macros and 105 I/Os. The standard cell libraries include configurations optimized for both high performance and density. The Datapath Compiler enables designers to compile a highly optimized multibit block of up to 128 bits using complete library elements such as ALUs, multipliers, barrel shifters, comparators and FIFOs. The libraries provide all the components necessary for a complete design solution including schematic descriptions, functional models, physical layouts, footprints, simulation models and icons. Access to the physical layout of the Liberty Series, beyond the SPICE-based simulation models which typically accompany an ASIC foundry library, gives designers good flexibility and control over the design and selection of a silicon vendor. The company can quickly retarget these libraries to specific physical design rules for a chosen vendor with minimal effort and assistance from the foundry. In addition, access to the physical layout allows designers to easily modify the library for greater density and performance as required. (Compass Design Automation, Exchange House, Central Milton Keynes MK9 2EW, UK. Tel: +44 (0) 908-661729)
Microprocessors and Microsystems
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data timing of 10.5 ns, self-timed write and on-board burst counter, the IDT71B589 is claimed to be the fastest and smallest high-performance cache. Using the small footprint 32-pin SOJ package instead of 44-pin PLCC solutions saves approximately 33% of board space and enhances electrical characteristics. In addition, the company has tailored those parameters critical to 50MHz and 67 MHz designs, resulting in a short address setup time (1 ns) and a fast output enable time (5 ns). A 10 ns 8k × 8 companion cache tag, the IDT71 B74, is also available, in 10.5 ns, 12 ns and 14 ns versions. IDT has also released the IDT71589SA, a low cost version of its original 486 CacheRAM. The IDT71589SA provides greatly improved performance in 25 and 33 MHz Intel 486 SX/DX/DX2 and OverDrive systems. The 24 ns CacheRAM is housed in the same 32-pin SOJ package as the IDT71B589 with timing parameters tailored for slower clock speeds. Three other high-density modules incorporating the IDT71589 are available including the IDT7MP6086 (128kB plus parity in a 72-lead SIMM), the IDT7MP6085 (128kB with parity in an 80-lead SIMM) and the IDT7MP6087 (256 kB with parity in an 80-lead SIMM). (Integrated Device Technology Europe, 21 The Crescent, Leatherhead, Surrey, KT22 8DY, UK. Tel: +44 (0) 372 377375)
Libraries and compilers for CMOS IC design The Liberty Series, a family of physical layout libraries and compilers for the design of CMOS integrated circuits, has been announced by Compass Design Automation. The series is claimed to be the first offering of general-purpose libraries and compilers from an electronic design automation (EDA) company that provides foundry flexibility and support for multiple design environments. Designers have the flexibility to select the foundry and CMOS process of their choice for chip
production. In addition to being tightly integrated with Compass'ASIC Navigator top-down design system, the libraries can be used with a variety of design tools and environments, including those from Cadence Design Systems, GenRad, Mentor Graphics, Synopsys and Zycad. IC design productivity and timeto-market is improved by eliminating the need to create low-level design elements and layout for different designs and foundry processes. The series enables chip designers to focus on designing the high-level functions that ultimately distinguish their products in the marketplace rather than on the development of basic building blocks. Fully portable gate array and standard cell libraries are included as well as RAM and multiplier compilers and Compass' optimized Datapath Compiler. The libraries have in-depth functionality. For example, the high performance gate array library contains up to 265 macros and 105 I/Os. The standard cell libraries include configurations optimized for both high performance and density. The Datapath Compiler enables designers to compile a highly optimized multibit block of up to 128 bits using complete library elements such as ALUs, multipliers, barrel shifters, comparators and FIFOs. The libraries provide all the components necessary for a complete design solution including schematic descriptions, functional models, physical layouts, footprints, simulation models and icons. Access to the physical layout of the Liberty Series, beyond the SPICE-based simulation models which typically accompany an ASIC foundry library, gives designers good flexibility and control over the design and selection of a silicon vendor. The company can quickly retarget these libraries to specific physical design rules for a chosen vendor with minimal effort and assistance from the foundry. In addition, access to the physical layout allows designers to easily modify the library for greater density and performance as required. (Compass Design Automation, Exchange House, Central Milton Keynes MK9 2EW, UK. Tel: +44 (0) 908-661729)
Microprocessors and Microsystems