Depletion V-groove MOS (VMOS) power transistors

Solid-SlateEkeclmnics,1976,Vol. 19,pp. 297-306. PergamonPress. Printed in Great Britain

DEPLETION V-GROOVE MOS (VMOS) POWER TRANSISTORS B. FARZANand C. A. T. SALAMA Department of Electrical Engineering, University of Toronto, Toronto MSS lA4, Ontario, Canada (Received 10July 1975;in revisedform 8 September 1975) Abstract-A new depletion MOS transistor is proposed. The structure uses anisotropic etching to define the channel in an n/p epitaxial silicon slice. A simple planar model is developed to explain the characteristics of the devices and is verified by measurements on experimental structures. Power devices are fabricated to illustrate the power capability of the structure. Parameters measured for this structure include: junction temperature, d.c. power dissipation, distortion, ac output power, efficiency. The devices were found to be capable of delivering up to 12W with a cutoff frequency of 80 MHz.

1. INTRODUCTION

NOTATION

effective channel depth drain-to-source breakdown voltage capacitance of oxide layer per unit area total gate capacitance geometrical channel depth electric field in the channel critical electric field in the channel MOS transistor cutoff frequency drain-to-source conductance transconductance drain current drain current in the saturationregion

Boltzmann’sconstant channel length acceptor and donor concentrations in the semiconductor respectively intrinsic carrier concentration transistor dc power dissipation transistor ac output power electronic charge oxide charge per unit area temperature ambient temperature channel temperature header temperature substrate to source voltage drain to source voltage drain to source saturation voltage flat-band voltage effective gate to source voltage applied gate to source voltage MOS gate pinch-off voltage at approximately zero drain voltage groove opening window depth of depletion region under the MOS gate thickness oi epitaxial layer denth of the source and drain II+ diffusion debth of depletion region of the substrate to channel p-n junction in the channel thickness of the gate oxide width of the channel permittivity of silicon dioxide permittivity of silicon ihermal re&tance low field bulk mobilitv of electrons low field surface mobility of electrons p-n junction built-in voltage metal-semiconductor work function tFor the purpose of this work power transistors are defined as those devices capable of handling a minimum of 1 W output power.

Until recently, silicon bipolar transistors were the main active components in powert amplifiers. These devices cover a broad power-frequency spectrum and can handle up to 100W at 400 MHz on the high power side (RCA 2N6104 and RCA2N6105) and 5 W at 4 GHz[l] on the low power side. Silicon power junction field effect transistors have been recently developed to operate at 1 GHz with an output power of 1 W [2]. GaAs field effect devices have also been reported handling 1.6 W at 2 GHz 131.These devices have found application in microwave communication systems. Up to now, relatively little work has been done on silicon MOS power transistors. The MOS transistors offer several attractive features as high-frequency power amplifiers. One of these features is the simplicity of the fabrication process. Another is the relative ease of assembling an amplifier circuit due to a lower feedback capacitance and a higher supply voltage compared with those of bipolars. Furthermore, in contrast to the bipolar transistor, the drain current of the MOS transistor has a negative temperature coefficient at high current levels, and thus tends to be thermally stable even when its area is large. This leads to uniform temperature distribution over the transistor and to freedom from thermal runaway and second breakdown which can be serious problems in the design of bipolar power transistors. Most of the original work on power MOS transistors was published by Josephy[4] who reported a p-channel power MOS transistor handling 6.1 W at a frequency of 30 MHz. More recently a n-channel depletion-type silicon UHF MOS power FET has been developed which handles 8.2 W at 1 GHz[5]. Another MOS device which is useful for power amplification is the double diffused MOS transistor (DMOS) which has been reported to handle up to 1.2 W at 2.1 GHz[6]. The last two devices mentioned involve fairly complex technologies and a double diffused process to reduce the channel length. Furthermore, in all of these devices the drain current is proportional to the surface mobility of carriers. This paper describes the operation and characteristics of a MOS power transistor which can achieve high power at high frequencies using simple readily available technology. The device is fabricated on n/p epitaxial silicon 297

B. FARZAN and C. A. T. SALAMA

298

substrates. The channel is defined by the use of anisotropic etching[7]. The device operates in the depletion mode and the drain current is proportional to the bulk mobility; resulting in high transconductance and high cutoff frequencies. 2. STRUCTUREAND OPERATIONOF TRE DEVICES

The cross-section of the depletion VMOS transistor is shown in Fig. 1. The device is an n-channel transistor fabricated within an n-type epitaxial layer (the channel) grown on a p-type substrate. An n t diffusion is provided to make source and drain contacts and reduce the series resistance of the channel to a negligible value. The structure has an MOS gate which is used to modulate the conductance of the channel along the groove and a p-n junction gate which is associated with the substrate. With the source grounded (at low values of drain-tosource voltage), a negative bias V, applied to the substrate causes a depletion region to form between the substrate and the channel. The depth of the depletion region extending into the channel is X,, as shown in Fig. 1. By applying a negative voltage to the MOS gate electrode a depletion region of depth X, is generated in the channel under the gate. Due to the geometry of the structure and the fact that the oxide thickness at the bottom of the groove is thicker than on the walls, the depletion region associated with the MOS gate does not extend uniformly along the groove but is narrower at its apex. Numerical calculations carried out by Parks [8] have shown that the depth of the depletion region at the bottom of the groove is about three times smaller than under the sidewalls of the groove. Under these conditions, the effective channel depth a is determined by the geometrical distance d between the bottom of the groove and the metallurgical boundary of the p-n junction as well as by the depletion regions associated with the MOS gate and the substrate channel p-n junction and is given by: a =d-X,-X,.

(1)

Below saturation, at low values of drain-to-source

voltage VD,there is a finite conductance between the drain and the source at zero gate voltage, namely g,. This conductance decreases when the depletion region under the MOS gate is increased by application of a negative voltage to the gate, and reaches zero when the two depletion regions meet at pinch-off (a = 0). The gate voltage required to pinch-off the device is VP,. If the channel depth d is large enough, pinch-off does not occur and the depth of the depletion region under the MOS gate increases with increasing negative gate voltage. At some critical voltage V, = V,, the surface potential becomes sticiently negative and an inversion layer of holes forms at the silicon-silicon dioxide interface. At V, = VcL the depletion region depth reaches a maximum X,,,, and any additional positive charge appears in the inversion layer[9]. The holes do not contribute to the conductance between the source and the drain due to the n+ source and drain contact islands which block hole conduction. In order to ensure that the device is operating in the depletion mode and is completely pinched off, the magnitude of pinch-off voltage VP, should be smaller than the voltage V,, required to invert the channel; in other words (d-X,,) should be smaller than X,,,,. As the drain voltage increases, the majority carriers (electrons in this case) travel from the source to the drain along the V-groove rather than parallel to the substrate. Thus, the full channel length L determines the characteristics of the device. Increasing the drain voltage, with a fixed negative voltage applied to the MOS gate, causes both depletion regions near the drain to increase, as shown in Fig. 2 until they meet and the drain current reaches its saturation value IDS.The two depletion regions meet somewhere near the bottom of the groove and the effective channel length in the saturation region L’ is reduced to almost half of L. If pinch-off occurs away from the bottom of the groove the pinch-off voltage in the saturation region may be different from the pinch-off voltage below saturation. However, the experimental results discussed in the next sections show that the pinch-off voltage is approximately the same below and above saturation, indicating

---,L--------_-_ / 0

Substrate

depletion reg,on

P

<>

1 Fig. 1. Cross-section of depletion VMOS transistor in depletion mode of operation, below saturation, (V, = 0; V, < 0, V, 5 0).

Fig. 2. Cross-section of depletion VMOS transistor in depletion mode of operation, above saturation, (V, > V, - V,,,,; V, < 0; v, 5 0).

V-Groove MOS power transistors

that pinch-off occurs very close to the bottom of the groove even in saturation. As discussed previously, if the magnitude of the pinch-off voltage of the MOS gate VP, is larger than the magnitude of the voltage V,, required to invert the surface layer, then the device does not pinch-off completely. At V, = VcL, an inversion layer just appears at the interface near the source. As 1Vc 1is increased this inversion layer extends further along the channel and for a critical voltage VoHIit extends completely and for a source to the drain. For 1Vc I> 1V,, 1any further increase in IV, ( simply changes the ptype inversion layer charge density. The charge, voltage and current in the undepleted portion of the n-type channel are no longer controlled by the MOS gate. However, saturation of the drain current will always be observed, although complete pinch-off by the MOS gate will not occur in this mode [9, lo].? The process of equilibration of holes in the inversion layer near the surface is determined by the minority carrier generation rate in and around the depleted region. For a given rate of generation of minority carriers, there will be a frequency above which the hole concentration in the inversion region cannot reach equilibrium or follow the gate voltage variation. In such a case, the depletion region depth will be modulated and therefore the electron contribution to the channel conductance will be affected by the gate voltage[lOl. When applying positive voltages to the MOS gate the potential everywhere in the channel will be positive with respect to the source contact. Therefore, an accumulation layer of electrons is formed under the MOS gate. The source to drain conductance increases with increasing MOS gate voltage. In this mode of operation, the transistor behaves as a square law device in a very similar manner to the standard enhancement mode MOS transistors. 3.

THEORY OF OPERATION

For simplicity a lirst order model of the device is considered in this section. The active portion of the actual device is shown bounded by the dotted line in Fig. 3. Assuming that the conduction from source to drain occurs along the groove side walls and that pinch-off occurs at point A as mentioned in the qualitative discussion of the operation, the device can be modeled by a simple planar structure obtained by opening the V-groove about CC’. The planar structure shown in Fig. 4 will be assumed to have an effective channel depth d’ = 1.7d and a channel tThe bottom p-n junction gate pinches-off the channel.

Mos gate deplellon r,~,o” xn

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cl

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Si02

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Fig. 4. Planar structure for a first order model of the depletion VMOS transistor. length L. The factor l-7 is determined by the geometry of

the groove. The channel length L is given by [11]: L = 2(0-865W - 1.23&),

(2)

where W is the groove opening and Xj is the depth of the n t diffusion. The geometrical channel depth d is given by: d=X,,i-l’7W, (3) where XePiis the thickness of the epitaxial layer. The validity of this model will be tested by comparing theoretical results derived in this section with experimental results obtained in the next section on the simple linear geometry devices. For the planar structure in Fig. 4, it is assumed that surface states can be neglected, that the channel is uniformly doped and that the gradual channel approximation is valid. The equation describing the Z-V characteristics of the device, as derived in Appendix I, is given by: Z

D

=~[(d’+~)V, t;~;(l+S(vo0

V,))“’

where ND is the channel doping, q is the electronic charge, CL.is the low field bulk mobility of electrons, Z is the channel width, d’ is the effective geometrical channel depth, L is the channel length, E,,l0are the permittivity of silicon and silicon dioxide respectively and X0 is the oxide thickness along the walls of the groove. VD is the drain voltage, Vs is the substrate bias and V, is the effective gate voltage defined in eqn (A3) and including the effect of the flat band voltage associated with the MOS gate. The parameters K0 and S are constants defined in the Appendix. The source-drain conductance gd can be found by differentiation of ZDwith respect to V, and is given by:

dL

3. Active portion of the depletion VMOS transistor.

/“’

b

;(

gd=dV, Fig.

299

I

= y[d’-K,(&

VDCLl

&X0

+y--((l+svGy2-1)

1.

t V,)“’

(5)

B. FARZANand C. A. T. SALAMA

300

If the effective channel depth a, at zero MOS gate voltage is defined as: a, = d’ -X,, = d’ - K,(&

t Vs)“*,

(6)

then (5) can be written as: g,=g,

[

1+% o ,((1+ 8VGP2-- I)],

voltage and is given in (8) and p Lis the surface mobility of the electrons in the accumulation layer. The transconductance in the saturation region is given by:

gm =gm+T (7)

where

(8) is the source to drain conductance at zero MOS gate voltage. The gate pinch-off voltage VP, is defined as the effective MOS gate voltage necessary to reduce g, to zero:

cow 3

v

G,

(13)

where gm, is the transconductance at zero effective MOS gate voltage and can be found from (11). In the previous analysis of the depletion mode of operation, it was assumed that the bulk mobility of electrons CL.is independent of the electric field in the channel. However, because of the relatively short channel lengths and the high pinch-off voltages encountered in the devices under consideration this assumption is not completely true and CL.is reduced by the electric field in the channel. An empirical relationship which defines the dependence of the mobility on the field has been suggested[l21 and is given by: (14)

The gate pinch-off voltage can therefore be controlled by the applied substrate voltage V, as well as by the channel depth d’. With increasing drain to source voltage, for a fixed MOS gate voltage, the device enters the saturation region, and the two depletion regions meet at the drain side of the channel. The drain saturation voltage V,, can be found by setting the effective channel depth at the drain side equal to zero: a =d’-X.(V,,)-X,(Vos)=O.

(10)

The transconductance in the saturation region gm is obtained by differentiation of 1, with respect to V, in the saturation region:

(11) As discussed in the qualitative description of the operation of the device, in the accumulation mode the transistor behaves like a standard enhancement mode MOS transistor. Therefore the conductance below saturation is given by[3]:

where pn is the low field mobility, EC is the critical field, typically 8 x lo3 V/cm, and E is electric field in the channel. To take into account the effect of the mobility variation with field, F Xshould be substituted instead of CL,, in the previous equations. In the VMOS structure, the n+ diffusions, which provide the source and the drain contacts, short the unmodulated portion of the channel and reduce the series resistances to a negligible value. There are two major parameters which are effected by temperature in the device: the drain current and the gate leakage current. The effect of temperature on the drain current is determined by two major factors: the carrier mobility EL.and the built-in potential & [13]. Since CL, decreases with increasing temperature, the effect of this is to decrease the drain current as the temperature rises. On the other hand, I&,] decreases with increasing temperature, causing the channel depth to increase, hence increasing the drain current. At high currents, the reduction in mobility predominates, and the drain current decreases with increasing temperature. Experimental results confirming this are presented in the next section. The leakage current associated with the MOS gate is extremely small, typically less than 10-14A and does not change noticeably with temperature. However, the leakage current of the substrate to channel p-n junction doubles for every 7°C increase in temperature. The maximum frequency of operation of a MOS transistor is given by[14]:

fo=$, where C, is the total gate capacitance of the device

(12) including the gate oxide capacitance as well as the where g, is the conductance at effective zero MOS gate

depletion layer capacitance associated with the MOS gate. In reality, there are stray capacitances which reduce the

V-Groove MOS power transistors

cut-off frequency of the device. The most important of these are: the gate to source and the gate to drain capacitances (due to the overlap of the gate electrode on the source and the drain) and the channel to substrate capacitance (due to depletion region associated with the substrate to channel p-n junction). The VMOS devices discussed here are designed to be compatible with the standard junction isolated integrated circuit process. However, if discrete high frequency power transistors are required the ideal situation would be to use intrinsic substrates instead of p-type substrates in order to reduce the substrate capacitance to a minimum value. 4. DESIGN CONSIDERATION

FOR MOS POWER

DEVICES

The previous sections dealt with the principle of operation of depletion VMOS transistors. This section deals with the application of the structure to power amplification and discusses the important device parameters including: power, current, voltage and thermal limitations. The ac output power POavailable from the transistor is proportional to the product of the maximum peak voltage swing which can be maintained across it and the peak current which it can safely pass. For a MOS transistor the maximum voltage swing which the device can withstand is the difference between the drain-source breakdown voltage SV,,s and the drain saturation voltage Vm at the maximum current. For a single device, operating in class B, the ac output power POwhich can be transferred to the load is given by: PO= &~,,(BVlJ,

- VDS).

(16)

It is desirable, therefore, to design a MOS power transistor with a large drain-source breakdown voltage, a small drain saturation voltage and a high current capability. The output power is also limited by the maximum channel temperature, the layout, the thermal properties of the device and package as well as the heat sinking capabilities of the assembly. In general, the two most important voltage limitations in the devices under consideration are destructive breakdown of the gate oxide and avalanche breakdown of the drain side of the substrate to channel p-n junction. In the saturation region the drain current of a depletion VMOS transistor is proportional to the carrier mobility p, the channel width 2, the channel depth d and is inversely proportional to the channel length L. A large field effect transistor is thermally stable for tThe edges of the source-drain regions are defined by a set of isolating grooves etched simultaneously with the gate grooves. The isolation grooves are etched down to the p-substrate. Special care should be taken to avoid inverting the p-substrate under the isolation grooves. Means of achieving this include: (1) The control of the oxide charge by growing the oxide in an HCI atmosphere. (2) The use of a p+-substrate instead of a p-substrate. (3) The use of p+ diffusion or implantation at the bottom of the isolation groove. (4) The use of a field plate.

301

fluctuations of current either over the surface of the device or with time. This is due to the negative temperature coefficient of the drain current resulting from the reduction in mobility with increasing temperature. The stability over the surface ensures that the distribution of current in the device will be uniform without the introduction of stabilizing resistances, which are often necessary in bipolar power transistors. The stability of the devices for transient changes of current, means that thermal run-away does not occur. The amount of heat which can be dissipated in the device is dependent on the geometry of the device as well as the type of header and the method of mounting the device. Heat generated in the channel is transferred to the supporting header and package through the silicon. The heat is then conducted away from the transistor package to the surrounding ambient. Assuming proportionality between heat flow and temperature gradient, the channel temperature Tc is related to both the ambient temperature T, and the internal power dissipation PD and is given by[l5]: (17)

where 13,,0, and 0, are the internal, header and heat sink thermal resistances respectively. The maximum power dissipation of the device is usually determined by the maximum allowable channel temperature, typically 175“C. 5. EXPERIMENTAL.

RESULTS

In order to test the model and obtain a better understanding of the operation of the devices, simple linear geometry devices as well as power devices were fabricated. The fabrication procedure is outlined in the following sections and the experimental results obtained are compared with theory. The devices were fabricated on 3-Xl-cm (100) n-type layers epitaxially grown on 5-lO&cm p-type silicon substrates. The processing steps for the three masks VMOS technology are shown in Fig. 5. These steps are illustrated for n-channel devices; however, the processing steps would equally well apply to the fabrication of p-channel devices. First, an unmasked phosphorous diffusion is performed. The phosphorous drive-in is carried out in an oxidizing ambient. Second, a 0.7 pm thick field oxide is thermally grown on the slice (Fig. Sa). The first mask is used to open windows in the oxide covering the n+ diffusion to define the channelt by anisotropically etching the grooves (Fig. 5b). Next, a 1SOOA gate oxide is thermally grown. The second mask is used to open contact holes for the source and drain (Fig. 5~). The final step consists of evaporation of aluminum and the last mask is used to define the metallization pattern. The final device cross-section is illustrated in Fig. 5d. The silicon etching procedure has been described in detail elsewhere [ 111,while the other processing steps have been described by Holmesll61. Figure 6 shows a photograph of a set of linear geometry devices, which were fabricated with groove openings

302

B. FARZAN and C. A. T.

(alunmasked

n+ dlffuslon

MS’02 fb)Slllcon

etch

P

(c)Gate

ox,de

SALAMA

power devices, the TO-5 cap was filled up with thermally conductive, electrically isolating epoxy+. To characterize the process, measurements were performed on lead slices. These involved: four-point probe measurements, beveling of junctions, as well as MOS C-V characteristics. The resultant processing parameters for the slice are listed in Table 1. Table 1. Processing parameters Substrate doping N,., Epitaxial layer doping ND Epitaxial layer thickness X,,, n + diffusion sheet resistance II+ diffusion depth x, gate oxide thickness x0 flat band voltage V, Oxide charge Q$,/q

3 X IO” to 5 X 10” cm-’ 1X 10” to 3 X 10” cm-’ 12.2pm 20 n/o 4pm ISOOW -1 to -2.sv 1 x IO” to 3.2 x IO” cm-’

growth

Linear geometry devices

Fig. 5. Processing steps for the fabrication of depletion VMOS transistor.

ranging from 7.6pm to 18pm and consequently had different channel depths. The alignment tolerance used in the fabrication was 12 pm. The layout of a single transistor is shown in Fig. 7, its dimensions are indicated in the figure. Figure 8 shows two power transistors used as test devices. The source to drain isolation in each was achieved by using a closed gate geometry. The smaller device (4.1 W)t has a channel width 2 = 860 pm and the larger one (25 W)i has a channel width Z = 1.25 cm. Both devices have a channel length L of 12 pm. The processing parameters were the same as for the simple linear geometry depletion VMOS devices. All the devices were mounted and bonded in TO-5 packages. To reduce the intrinsic thermal resistance in the

tThis power is the maximum dc power dissipation that results in a channel temperature of 175°C. $High viscosity SSE, Transene Co., Rowley, Mass.

Ir

_;“A 125ri

T 260

i

ks

Fig. 7. Layout of alineargeometry depletion VMOStransistor.

Figure 9 shows a typical set of low frequency I-V characteristic curves for the depletion VMOS linear geometry transistors fabricated with various geometric channel depths d. It can be seen that device T # 1, with the smallest channel (d = 1 pm), exhibits complete MOS gate pinch-off (Fig. 9a). It is also interesting to note that, as predicted, saturation of drain current does occur for all devices even though MOS gate pinch-off may not occur (Fig. 9b,c). It should be noticed that the I-V characteristics for transistor T# 1 (Fig. 9a) are plotted for both positive and negative gate voltages; i.e. depletion and accumulation modes of operation. The upper eight curves in the figure correspond to accumulation. Measurements carried out on the pinched-off devices include Z-V characteristics, conductance below saturation, transconductance and output conductance in the saturation region, pinch-off voltage, cut-off frequency and breakdown voltages. The small signal measurements were carried out on the device using a lock-in amplifier system (Brookdeal) and plotted directly using an X-Y recorder. The small signal drain-to-source channel conductance gd near zero drain-to-source bias was measured at 1 KHz as a function of the MOS gate voltage Vc. The resulting characteristic for the depletion mode of operation (V, < 0) is plotted in Fig. 10a. The theoretical results are also shown in the same figure as circular dots. The experimental and theoretical results are in good agreement. The carrier mobility determined from the experimental results is 1260cm*/V-set, in agreement with the reported value for the bulk mobility of electrons in silicon[l2,17]. The conductance at zero gate voltage g, was found to be 0.38 m ZTThe resulting characteristic for the accumulation mode of operation (V, > 0) is plotted in Fig. lob. The curve is linear in this mode of operation as predicted by theory. From the slope of the conductance curve, the carrier mobility was found to be 630 cm’/V-set, which is typical of the surface electron mobility in silicon[18]. At high positive MOS gate voltages, the conductance decreases due to decrease in the surface mobility as expected. The small signal transconductance gm in the saturation region was also measured at 1 KHz for the same device

Fig. 6. Photomicrograph of a set of linear geometry devices.

Fig. 8. Photomicrograph of a set of power devices.

[Facingpage 3021

CC,

Fig. 9. I-V characteristics of three typical linear geometry transistors: (a) T # 1, d = 1 ym and L = 17pm, (b) T # 2, d = 3 pm and L = 13 pm, and (c) T # 3, d = 6 pm and L = 6.5 pm, (for all transistors Z = 260 pm, X,, = 1500 A and V” = 0).

303

V-Groove MOS power transistors

Experlmenl Theory

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_ .

Experament Theory

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7 Experiment Theory 30

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Fig. 10. Small signal drain-to-source channel conductance below saturation: (a) in depletion mode of operatiov, and (b) in accumulation mode of operation, (X, = 1500A, L = 17qn, Z=260pm, d=lrm; g0=0.38mU, V,,=-4V; V,=O and VD= 0). discussed above. The experimental and theoretical curves for the completely pinched-off devices are shown in Fig. 11. In the depletion mode (i.e. negative gate voltages) the transconductance is fairly well described by assuming the effective channel length L’ to be L/2 and accounting for the reduction in the mobility due to the relatively high field in the channel (about 10 KVlcm). The transconductance in the accumulation mode of operation is also in good agreement with the theory as shown in Fig. llb. Since the source and the drain series resistances are small (less than 1 a), they are neglected in calculating the conductance and transconductance. The pinch-off voltage for the grounded substrate case was obtained from the intercept of the conductance and the transconductance curves with the gate voltage axis. Both pinch-off voltages were observed to be approximately the same. The pinch-off voltage was found to range from - 2 to - 4 volts for the linear geometry devices investigated. The output conductance of the transistors was also measured in the saturation region. The values were significantly smaller than those observed in an MOS transistor with planar geometry because most of the drain voltage is taken up along the drain side of the V-groove, resulting in a much smaller channel-shortening effect. For the same transistor discussed above, the output conductancewaslO~UatIn=2mA, VDs=12Vand V,=O. The total gate capacitance at zero gate voltage was measured and found to be 1.5 pf. The calculated maximum cut-off frequency of the device is 32 MHz. The experimental cut-off frequency was found to be 16.5MHz and is smaller than the theoretical cut-off frequency due

0

I........... 0.2 cbl

04

06

0.8

1.0

“G/I”POi

Fig. 11. Small signal transconductance in the saturation region: (a) in depletion mode of operation, and (b) in accumulation mode of operation, (X0 = 1500A, L = 17pm, Z = 260pm, d = 1pm; gm,=0~16mU,V,,,=-4V;VB=OandVo=20V). to parasitic capacitance especially the channel to sub-

strate capacitance. Typical drain-source breakdown voltages measured over a sample of devices on a slice ranged from 55 to 75 V. The destructive gate breakdown voltage was found to be larger than 1OOV. Power devices

Figures 12a and b show typical I-V characteristics for the low power and high power transistors illustrated in Fig. 8. In order to completely pinch-off the devices a biasing voltage of - 10V was applied to the substrate. The devices can also be pinched-off by connecting the MOS gate and the substrate together and using the devices as three terminal devices. The output conductance in the saturation region was typically 175F U (0.2 ~0 per unit channel width in pm) at IDS= 75 mA, V, = 25 V and Vc = 0 for the low power device and 2.6 m U(O.21 p Uper unit channel width in pm) at IDS= 750 mA, V, = 25 V and Vc = 0 for the high power device. The total MOS gate capacitance was measured at zero MOS gate bias, and was found to be 5pf for the low power transistors and 65 pf for the high power devices, resulting in calculated cutoff frequencies of 160MHz for both devices. The experimental cut-off frequencies were found to be 100MHz and 85 MHz for the low and high power devices respectively. The smaller experimental cut-off frequencies are due to parasitic capacitances, particularly the substrate to channel p-n junction capacitance. The drain-to-source breakdown voltage for these power

304

B.

FARZAN

and C. A. T.

devices was found to be the same as the drain-to-source breakdown voltage in the simple linear geometry devices ranging typically from 50 V to 75 V. In the depletion VMOS the channel temperature can be determined by measuring the forward voltage of the substrate to channel p-n junction at a fixed forward current (1 mA). Power is applied to the device under normal conditions. This power is then momentarily switched-off and the forward diode voltage measured by a gated voltmeter. The off-time is either kept negligibly small when possible, or else considered in determining the average input power[l9]. Figure 13 shows the power dissipation versus channel temperature, for the low power device, for the three cases of no heat sink, finite heat sink (Series 200 feather ‘weight Snap-On cooler #209,t 0,= 3O”C/W)and near infinite heat sink which consisted of a very large block of aluminum (0, = 0) which was kept as close as possible to ambient temperature. The values of the various thermal resistances were calculated from the curves and found to be: 8, = 35”ClW and 0,, = 7O”C/W. Assuming the maximum allowable channel temperature to be 17X, the maximum power dissipation of the device is 1.3 W without heat sink and 2.6 and 4.1 W with finite and near infinite heat sinks respectively (at an ambient temperature of 29°C). The power dissipation derating for this device versus ambient temperature is shown in Fig. 14. The same measurements were carried out for the high power devices. The transistors under test were found to

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100

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150

175

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Fig. 13. Power dissipation versus the channel temperature for low power transistor No. 4: (a) near infinite heat sink, (b) snap-on cooler, and(c) no heat sink. T.6

SALAMA

dissipate 5 W without a heat sink and 25 W with a near infinite heat sink. It should be noted that by choosing better packaging methods, the intrinsic and case thermal resistances can be reduced to improve the power handling capability of the device. The drain current in the saturation region was measured for different ambient temperatures. The measurements were carried out in a temperature controlled chamber. Figure 15 shows the results for one of the transistors measured at two different MOS gate voltages. As predicted the drain current has a negative temperature coefficient. The distribution of temperature over the surface of an inter-digitated depletion VMOS power transistor was measured using a liquid crystal. The surface to be tested was first coated with a water-soluble black paint to enhance the color pattern. A liquid crystal solution having the desired temperature range was then selected and applied to the surface and the solvent allowed to evaporate. Upon slowly heating through the mesomorphic range, the liquid crystal changes from colorless to red, on through the spectrum of colors to blue and back to colorless. The Vari-Light 71171$ liquid crystal was used to measure the surface temperature of the device. The structure was observed under the microscope for different operating points and power dissipations. The temperature distribution across the surface was found to be nearly uniform and no hot spots were observed on the surface. In order to obtain the harmonic distortion, the transistors were biased to operate in class A. The distortion was measured using a wave analyzer (Hewlett Packard model 310A) at different input frequencies and biasing points. The ratios of the second and third harmonic amplitude to the fundamental amplitude in db for different frequencies are listed in Table 2. The distortion was found to be almost independent of MOS gate biasing voltage, but increased with increasing fundamental frequency. The distortion also increased as a function of output power as expected. The distortion measured (less than - 30 db) indicates that these devices may be useful in communication system applications. From the measured maximum limitations of the devices including voltage, current and d.c. power dissipation, the maximum a.c. output power that the transistor can deliver to the load and the maximum efficiency can be estimated. These values are listed in Table 3 for the low and high power devices. 90 T.6 63. 70-

l-._

VG.O

l-._

.

6050ID(mA) T,(W)

Fig. 14. Power derating for transistor No. 4. tDelta-T Semiconductors. $3 M Co., Cincinnati, OH, 45242.This particular liquid crystal is red at 75°C yellow at 92.5”C,green at 102°Cand blue at 120°C.

40V( s-10 v

30-

.-•-.-._*

zo-

20

30

40

50

60

70

60

T,(%)

Fig. 15. Temperature dependence of drain current.

V-Groove MOS power transistors

was found to be 47% for both devices (slightly lower than the calculated value).

Table 2. Distortion measurements on power transistors

Fundamental frequency (KHz)

Second harmonic distortion (db)

Third harmonic distortion (db)

Total distortion (db)

Low power devicet 10 100 500

-55 -56 -48

- 40.9 -35 -30

-50 -43 -43

High power deviceS 10 100 500

-52 -53 -46

-48 -40 -41

-39 -33.9 -30

tOutput power= 0.4 W. $Output power = 4 W.

Table 3. Characteristics of power transistors Low power device Drain-to-source breakdown voltage SV,, (V) Drain saturation voltage V,, (V) Maximum drain current IDS,.. (4

High power device

55

55

15

15 1.4

0.26

dc power dissipation PD (W) Efficiency in class B operation Q (calculated) ac output power in class B P,(W) (calculated)

4.1

25

51

51%

1.7

13

305

In order to confirm these calculations, measurements were performed on the devices. The output power and efficiency of the transistors were measured. The low and high power devices were capable of delivering 1.6 would 12 W respectively (!90%of the calculated value) with a cut-off frequency of 80 MHz. The experimental efficikncy

6. SUMMARY AND CONCLUSIONS

In this paper, a new depletion MOS transistor was proposed. The structure uses anisotropic etching of silicon to define the channel in an n-type epitaxial layer grown on a p-type substrate. A simple planar structure was used to develop a first order model to explain the behaviour of the device. The model was sufficient to describe the operation of the depletion VMOS transistor, as verified by measurements on experimental devices. The new structure offers many advantages including: short channel length, low output conductance and high transconductance in the saturation region, small MOS gate capacitance and hence high cut-off frequency, high and controllable pinch-off voltage, high drain breakdown voltage and high packing density. These advantages as well as the negative temperature coefficient of the drain current (due to reduction of mobility with increasing temperature) make the depletion VMOS transistor suitable for power amplification. Devices were fabricated to illustrate the power capability of the structure. The high current handling and high drain-to-source breakdown make the devices capable of delivering up to 12 W to the load with a cut-off frequency of 80MHz and low output distortion. The results obtained on the devices are summarized in Table 4, and compared with some MOS power transistors that have been reported in the literature. The output power per unit area obtained from the depletion VMOS transistor is higher than that obtained from the other structures under similar conditions, except for the vertical double diffused MOS transistor which involves very complex technology including angle evaporation to define the gate region. The cut-off frequency of the VMOS is not as high as that of the UHF power device. However, by using insulating or very high resistivity substrates and by proper care in the design of masks it is possible to achieve much higher cut-off frequencies of the order of 1 GHz.

Acknowledgements-Thiswork was supported by the Canadian Defence Research Board and the National Research Council of Canada.

Table 4. Comparison of MOS transistors

Area (mm*) C0 (PO Gm) Z (cm) SV,, (V) I~~rnnr(A) PO(W) PO/A (W/mm’)

fo (MHz)

VMOSt n-channel

MOSFETS p-channel

Si UHF MOSFETB n-channel

Vertical MOSFET’ n-channel

1.21 62 12 1.25 55 I.4 11.6 9.5 80

5.88 130 16 4.2 90 0.69 6.1 1.2 >30

1.4 50.5 5 1 55 1.1 8.2 5.8 1000

0.1 1 0.62 1 1.2 12 2100

tThis work: VMOS technology. *Ref. [4]: standard p-channel technology. @Ref.[5]: modified n-channel technology. URef.[6]: double diffused technology.

306

B. FARZAN and C. A. T. SALAMA

v, = vy;- v,,,

REFERENCES

1. E. T. Casterline and J. A. Benjamin, Solid-St. Tech. 51 (April 1975). 2. D. P. Lecrosnier and G. P. Pelous, IEEE Trans. Electron Devices ED-21, 113 (1974). 3. M. Fukuta, T. Mimura, I. Tujimura and A. Furumoto, ISSCC, paper THAM 7.6. Philadelphia (1973). 4. R. D. Josephy, Philips Tech. Reo. 31, 251 (1970). 5. Y. Morita, H. Takahashi, H. Matayoshi and M. Fukuta, IEEE Trans. Electron Devices ED-21, 733 (1974). 6. T. M. S. Hena and H. C. Nathanson. Electronics Letters 10, 4% (1974). 7. D. B. Lee, J. Appl. Phys. 40, 4569 (1969). 8. C. M. Parks and C. A. T. Salama. Solid-St. Electron. 18, 1061 (1975). 9. S. R. Hofstein, IEEE Trans. on Electron Devices ED-13,846 (1966). 10. V. G. K. Reddi, IEEE Trans. on Electron Devices ED-12,581 (1965). II. F. E. Holmes and C. A. T. Salama, Solid-St. Electron. 17,791 (1974). 12. D. M. Caughey and R. E. Thomas, Proc. IEEE 55, 2192 (1967). 13. R. S. C. Cobbold, Theory and Application of Field Efect Transistors. Wiley, New York (1970). 14. C. T. Sah, IEEE Trans. on Electron Devices ED-11, 324

(1964). 15. R. D. Thornton, D. Dewitt, E. R. Chenette and P. E. Gray, Characteristics and Limitations of Transistors. Wiley, New York (1966). 16. F. E. Holmes, A photo-MOSFET imaging array element. M.A.Sc. Thesis Universitv of Toronto (1971). 17. S. M. Sze, Physics of Semiconductor Devices. Wiley, New York (1969). 18. A. Many, Y. Goldstein and N. B. Grover, Semiconductor Surfaces. Wiley, New York (1%5). 19. GE Transistor Manual. General Electric, New York (1964). 20. A. S. Grove, Physics and Technology of Semiconductor Devices. Wiley, New York (1967). APPENDIX I

For the planar structure in Fig. 4, assuming that surface states can be neglected, that the channel is uniformly doped and that the gradual channel approximation is valid. The differential equation describing the I-V characteristics of the device is given by: I&y = Nbq&‘a(y)dV(y),

(Al)

a(y)=d’-X.(y)-X,(y),

(A2)

where

N, is the channel doping, q is the electronic charge, +” is the low field bulk mobility of electrons, 2 is the channel width, d’ is the effective geometrical channel depth, X, and X. are the depths of depletion regions of the MOS gate and the substrate respectively, and V(y) is the potential in the channel at point y. This potential is zero at the source (y = 0), and it is equal to V, at the drain (y = L). The applied MOS gate voltage VT; is related to the effective MOS gate voltage V, by:

(A3)

where V,, is the flat-band voltage and is defined as: VFt?=b4,+,

(A4)

0

where &s is the metal-semiconductor work function, Qss is the oxide charge per unit area and Cois the oxide capacitance per unit area. In the following analysis all MOS gate voltages refered to will be effective MOS gate voltages including the flat-band voltage. The depth of the depletion region X, associated with the MOS gate is given by [lo]: x, = F[(l 0

+ 6( v, - V(y)))“‘- 11,

(A5)

where +!&&, “7

(A6)

D

X0 is the thickness of the MOS gate oxide and l,, co are the permittivity of silicon and silicon dioxide respectively. The maximum depth of the depletion region X,,,, is given by (101: 1,2

4kTe X dmar= --ihr(No/n,)

,

I

Lq’&

(A7)

where k is Boltzmann’s constant, T is the absolute temperature and n, is the intrinsic carrier concentration. The magnitude of the negative effective MOS gate voltage which results in this maximum depletion depth is: ~v&$[*+~x”x~~_].

(A8)

The depth of the substrate to channel depletion region X, is given by [20]: (A9)

X” = K”(& + V&l+ WYV2, where K,=

2e,NA

‘I2

( qND(NA+ ND)>

(Al’3

’

& = (kT/q) In (NaN,,/n,2) is the built-in potential, Vu is the substrate voltage and N, is the substrate doping. Substituting the values of X,, and X, in (Al) and integrating yields: I D =~[(d’+$$!jV~+;$;(l+6(1/,#(l

0

+ ;K,(I#J~

t 6V,)“3-;K~(~.

t Vn)*”

1

V,))“’

t V, t VD)2”

(All)